coreboot-gerrit November 2018

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Add ICL U and Y RVP DIMM configuration
by Aamir Bohra (Code Review) 21 Nov '18

21 Nov '18

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29770 ) Change subject: mb/intel/icelake_rvp: Add ICL U and Y RVP DIMM configuration ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/29770/1/src/mainboard/intel/icelake_rvp/Mak… File src/mainboard/intel/icelake_rvp/Makefile.inc: https://review.coreboot.org/#/c/29770/1/src/mainboard/intel/icelake_rvp/Mak… PS1, Line 24: romstage-y += romstage_fsp_params.c > extra line Done https://review.coreboot.org/#/c/29770/1/src/mainboard/intel/icelake_rvp/boa… File src/mainboard/intel/icelake_rvp/board_id.c: https://review.coreboot.org/#/c/29770/1/src/mainboard/intel/icelake_rvp/boa… PS1, Line 31: /* Get Board ID via EC I/O port write/read */ : int get_board_id(void) : { > make single line comment Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7 Gerrit-Change-Number: 29770 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 11:21:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Add ICL U and Y RVP DIMM configuration
by Aamir Bohra (Code Review) 21 Nov '18

21 Nov '18

Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29770 to look at the new patch set (#2). Change subject: mb/intel/icelake_rvp: Add ICL U and Y RVP DIMM configuration ...................................................................... mb/intel/icelake_rvp: Add ICL U and Y RVP DIMM configuration List of ICL board variants 1. ICL-U DDR4 - All possible DDR4 memory type LPDDR4 - Memory down fixed DIMM configuration 2. ICL-Y All LPDDR4 DIMM on platform This patch ensures to have all proper SPD configuration. Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/Makefile.inc A src/mainboard/intel/icelake_rvp/board_id.c A src/mainboard/intel/icelake_rvp/board_id.h M src/mainboard/intel/icelake_rvp/spd/Makefile.inc A src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex M src/mainboard/intel/icelake_rvp/spd/spd_util.c 6 files changed, 212 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29770/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7 Gerrit-Change-Number: 29770 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: riscv: fix bug of sifive-gpt.py
by Jonathan Neuschäfer (Code Review) 21 Nov '18

21 Nov '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29767 ) Change subject: riscv: fix bug of sifive-gpt.py ...................................................................... Patch Set 2: Code-Review+1 Thanks! But please change "small end" to "little endian" in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/29767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib025197fc96f32823e687a89de0cee51c952b031 Gerrit-Change-Number: 29767 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 11:20:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Add ICL U and Y DIMM configuration
by Subrata Banik (Code Review) 21 Nov '18

21 Nov '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29770 ) Change subject: mb/intel/icelake_rvp: Add ICL U and Y DIMM configuration ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/29770/1/src/mainboard/intel/icelake_rvp/Mak… File src/mainboard/intel/icelake_rvp/Makefile.inc: https://review.coreboot.org/#/c/29770/1/src/mainboard/intel/icelake_rvp/Mak… PS1, Line 24: extra line https://review.coreboot.org/#/c/29770/1/src/mainboard/intel/icelake_rvp/boa… File src/mainboard/intel/icelake_rvp/board_id.c: https://review.coreboot.org/#/c/29770/1/src/mainboard/intel/icelake_rvp/boa… PS1, Line 31: /* : * Get Board ID via EC I/O port write/read : */ make single line comment -- To view, visit https://review.coreboot.org/c/coreboot/+/29770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7 Gerrit-Change-Number: 29770 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 21 Nov 2018 11:14:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Add ICL U and Y DIMM configuration
by Aamir Bohra (Code Review) 21 Nov '18

21 Nov '18

Hello Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/29770 to review the following change. Change subject: mb/intel/icelake_rvp: Add ICL U and Y DIMM configuration ...................................................................... mb/intel/icelake_rvp: Add ICL U and Y DIMM configuration List of ICL board variants 1. ICL-U DDR4 - All possible DDR4 memory type LPDDR4 - Memory down fixed DIMM configuration 2. ICL-Y All LPDDR4 DIMM on platform This patch ensures to have all proper SPD configuration. Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/Makefile.inc A src/mainboard/intel/icelake_rvp/board_id.c A src/mainboard/intel/icelake_rvp/board_id.h M src/mainboard/intel/icelake_rvp/spd/Makefile.inc A src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex M src/mainboard/intel/icelake_rvp/spd/spd_util.c 6 files changed, 215 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29770/1 diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc index ef0fb34..8d23451 100644 --- a/src/mainboard/intel/icelake_rvp/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/Makefile.inc @@ -21,10 +21,13 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c + romstage-y += romstage_fsp_params.c +romstage-y += board_id.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-y += board_id.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/icelake_rvp/board_id.c b/src/mainboard/intel/icelake_rvp/board_id.c new file mode 100644 index 0000000..62a1ad1 --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/board_id.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "board_id.h" +#include <boardid.h> +#include <ec/acpi/ec.h> +#include <stdint.h> +#include <ec/google/chromeec/ec.h> + +static int get_board_id_via_ext_ec(void) +{ + uint32_t id = BOARD_ID_INIT; + + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + + return id; +} + +/* + * Get Board ID via EC I/O port write/read + */ +int get_board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) { + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + id = get_board_id_via_ext_ec(); + else{ + uint8_t buffer[2]; + uint8_t index; + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + for (index = 0; index < sizeof(buffer); index++) + buffer[index] = recv_ec_data(); + id = (buffer[0] << 8) | buffer[1]; + } + } + } + + return id; +} diff --git a/src/mainboard/intel/icelake_rvp/board_id.h b/src/mainboard/intel/icelake_rvp/board_id.h new file mode 100644 index 0000000..3ccfe37 --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/board_id.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_BOARD_ID_H_ +#define _MAINBOARD_BOARD_ID_H_ + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0D + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc index 854a491..d92ce96 100644 --- a/src/mainboard/intel/icelake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/spd/Makefile.inc @@ -17,11 +17,11 @@ SPD_BIN = $(obj)/spd.bin -SPD_SOURCES = empty # 0b000 -SPD_SOURCES += empty # 0b001 -SPD_SOURCES += empty # 0b001 -SPD_SOURCES += empty # 0b011 -SPD_SOURCES += empty # 0b100 -SPD_SOURCES += empty # 0b101 -SPD_SOURCES += empty # 0b110 -SPD_SOURCES += empty # 0b111 +SPD_SOURCES = empty # 0b000 +SPD_SOURCES += samsung_K4F6E304HBMGCJ # 1b001 +SPD_SOURCES += empty # 2b010 +SPD_SOURCES += empty # 3b011 +SPD_SOURCES += samsung_K4F6E304HBMGCJ # 4b100 +SPD_SOURCES += empty # 5b101 +SPD_SOURCES += samsung_K4F6E304HBMGCJ # 6b110 +SPD_SOURCES += empty # 7b111 diff --git a/src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex b/src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex new file mode 100644 index 0000000..62dff16 --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex @@ -0,0 +1,32 @@ +23 11 10 0E 15 19 94 08 00 40 00 00 0A 22 00 00 +00 00 05 0F 92 54 01 00 8A 00 90 A8 90 A0 05 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/icelake_rvp/spd/spd_util.c b/src/mainboard/intel/icelake_rvp/spd/spd_util.c index 25f7f20..63b39fd 100644 --- a/src/mainboard/intel/icelake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/icelake_rvp/spd/spd_util.c @@ -13,11 +13,21 @@ * GNU General Public License for more details. */ #include <arch/byteorder.h> +#include <arch/cpu.h> #include <console/console.h> +#include <intelblocks/mp_init.h> #include <stdint.h> #include <string.h> +#include "../board_id.h" #include "spd.h" +enum icl_dimm_type { + icl_u_ddr4 = 0, + icl_u_lpddr4 = 1, + icl_u_lpddr4_type_3 = 4, + icl_y_lpddr4 = 6 +}; + void mainboard_fill_dq_map_ch0(void *dq_map_ptr) { /* DQ byte map Ch0 */ @@ -37,30 +47,61 @@ memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } +static uint8_t get_spd_index(void) +{ + uint8_t spd_index = (get_board_id() & 0x1F) & 0x7; + + return spd_index; +} + void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 }; + const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 }; + const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 }; + const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 }; + const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; - const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 }; - - if (IS_ENABLED(CONFIG_BOARD_INTEL_ICELAKE_RVPU)) - memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); - else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); + switch (get_spd_index()) { + case icl_u_ddr4: + memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + break; + case icl_u_lpddr4: + memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); + break; + case icl_u_lpddr4_type_3: + memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3, + sizeof(dqs_map_u_lpddr_type_3)); + break; + case icl_y_lpddr4: + memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + break; + default: + break; + } } void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 }; + const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 }; + const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6 }; + const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 }; - const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 }; - - if (IS_ENABLED(CONFIG_BOARD_INTEL_ICELAKE_RVPU)) - memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); - else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); + switch (get_spd_index()) { + case icl_u_ddr4: + memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + break; + case icl_u_lpddr4: + case icl_u_lpddr4_type_3: + memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); + break; + case icl_y_lpddr4: + memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + break; + default: + break; + } } void mainboard_fill_rcomp_res_data(void *rcomp_ptr) @@ -70,11 +111,45 @@ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); } +/* + * get processor id using cpuid eax=1 + * return value will be in EAX register + */ +static uint32_t get_cpuid(void) +{ + struct cpuid_result cpuidr; + + cpuidr = cpuid(1); + + return cpuidr.eax; +} + void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { /* Rcomp target */ - static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + static const u16 RcompTarget_DDR4[RCOMP_TARGET_PARAMS] = { + 100, 33, 32, 33, 28 }; + static const u16 RcompTarget_LPDDR4_Ax[RCOMP_TARGET_PARAMS] = { 80, 40, 40, 40, 30 }; + static const u16 RcompTarget_LPDDR4_Bx[RCOMP_TARGET_PARAMS] = { + 60, 20, 20, 20, 20 }; - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); + switch (get_spd_index()) { + case icl_u_ddr4: + memcpy(rcomp_strength_ptr, RcompTarget_DDR4, + sizeof(RcompTarget_DDR4)); + break; + case icl_y_lpddr4: + case icl_u_lpddr4: + case icl_u_lpddr4_type_3: + if (get_cpuid() == CPUID_ICELAKE_A0) + memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax, + sizeof(RcompTarget_LPDDR4_Ax)); + else + memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Bx, + sizeof(RcompTarget_LPDDR4_Bx)); + break; + default: + break; + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/29770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7 Gerrit-Change-Number: 29770 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Enable touchscreen wakeup
by Zhuohao Lee (Code Review) 21 Nov '18

21 Nov '18

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29769 ) Change subject: mb/google/fizz/variants/karma: Enable touchscreen wakeup ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0c9493dec367c7813047c7994cc83537aaef141 Gerrit-Change-Number: 29769 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 10:51:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Disable SD controller and update GPIO
by Zhuohao Lee (Code Review) 21 Nov '18

21 Nov '18

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29765 ) Change subject: mb/google/fizz/variants/karma: Disable SD controller and update GPIO ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8015fe35a4ff79469b5781942f588c3e1b88b751 Gerrit-Change-Number: 29765 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 10:51:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/dragonegg: Add initial mainboard code support
by Patrick Rudolph (Code Review) 21 Nov '18

21 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29749 ) Change subject: mb/google/dragonegg: Add initial mainboard code support ...................................................................... Patch Set 7: > > Please add Documentation for that board. > > For example: > > How to flash, required BLOBs, pictures if possible, everything > that > > is useful for coreboot development. > > I will let Shelley to answer this question. As this is early ICL > silicon, i'm not sure about board availability to able to build at > externally. That would be wonderful to have it in the Documentation :-). -- To view, visit https://review.coreboot.org/c/coreboot/+/29749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Gerrit-Change-Number: 29749 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 10:02:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/dragonegg: Add initial mainboard code support
by Subrata Banik (Code Review) 21 Nov '18

21 Nov '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29749 ) Change subject: mb/google/dragonegg: Add initial mainboard code support ...................................................................... Patch Set 7: > Please add Documentation for that board. > For example: > How to flash, required BLOBs, pictures if possible, everything that > is useful for coreboot development. I will let Shelley to answer this question. As this is early ICL silicon, i'm not sure about board availability to able to build at externally. -- To view, visit https://review.coreboot.org/c/coreboot/+/29749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Gerrit-Change-Number: 29749 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 09:57:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Enable touchscreen wakeup
by David Wu (Code Review) 21 Nov '18

21 Nov '18

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29769 Change subject: mb/google/fizz/variants/karma: Enable touchscreen wakeup ...................................................................... mb/google/fizz/variants/karma: Enable touchscreen wakeup Update GPIO GPP_B4 to enable touchscreen wakeup BUG=b:119594783 BRANCH=master TEST=can wake up with touchscreen. Change-Id: If0c9493dec367c7813047c7994cc83537aaef141 Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/fizz/variants/karma/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29769/1 diff --git a/src/mainboard/google/fizz/variants/karma/gpio.c b/src/mainboard/google/fizz/variants/karma/gpio.c index 29c6f88..c54f75c 100644 --- a/src/mainboard/google/fizz/variants/karma/gpio.c +++ b/src/mainboard/google/fizz/variants/karma/gpio.c @@ -51,7 +51,7 @@ /* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ /* CPU_GP2 */ PAD_CFG_GPO(GPP_B3, 0, DEEP), /* TOUCHSCREEN_RST# */ -/* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 0, DEEP), /* PCH_TS_EN */ +/* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* PCH_TS_EN */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLK_PCIE_LAN_REQ# */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, -- To view, visit https://review.coreboot.org/c/coreboot/+/29769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0c9493dec367c7813047c7994cc83537aaef141 Gerrit-Change-Number: 29769 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2018