coreboot-gerrit November 2018

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Change in ...coreboot[master]: util/cbfstool: Fix GCC error due to a shadowed declaration
by Werner Zeh (Code Review) 21 Nov '18

21 Nov '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29776 Change subject: util/cbfstool: Fix GCC error due to a shadowed declaration ...................................................................... util/cbfstool: Fix GCC error due to a shadowed declaration There is already a function with the name buffer_size(). Adding a local variable with the same name will lead to the following error on older GCC versions (e.g. version 4.4.7): declaration of 'buffer_size' shadows a global declaration To fix this rename the local variable to buffer_len. Change-Id: Ifae3a17152f2f9852d29a4ac038f7e5a75a41614 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M util/cbfstool/cbfs_image.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/29776/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 3c5d29c..7d78e39 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -1299,7 +1299,7 @@ unsigned int decompressed_size = 0; unsigned int compression = cbfs_file_get_compression_info(entry, &decompressed_size); - unsigned int buffer_size; + unsigned int guffer_len; decomp_func_ptr decompress; if (do_processing) { @@ -1308,11 +1308,11 @@ ERROR("looking up decompression routine failed\n"); return -1; } - buffer_size = decompressed_size; + guffer_len = decompressed_size; } else { /* Force nop decompression */ decompress = decompression_function(CBFS_COMPRESS_NONE); - buffer_size = compressed_size; + guffer_len = compressed_size; } LOG("Found file %.30s at 0x%x, type %.12s, compressed %d, size %d\n", @@ -1321,8 +1321,8 @@ decompressed_size); buffer_init(&buffer, strdup("(cbfs_export_entry)"), NULL, 0); - buffer.data = malloc(buffer_size); - buffer.size = buffer_size; + buffer.data = malloc(guffer_len); + buffer.size = guffer_len; if (decompress(CBFS_SUBHEADER(entry), compressed_size, buffer.data, buffer.size, NULL)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/29776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifae3a17152f2f9852d29a4ac038f7e5a75a41614 Gerrit-Change-Number: 29776 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/cpu/intel/Kconfig: Remove dead source
by Patrick Georgi (Code Review) 21 Nov '18

21 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29690 ) Change subject: src/cpu/intel/Kconfig: Remove dead source ...................................................................... src/cpu/intel/Kconfig: Remove dead source fsp_model_206ax was removed in Change-Id: I7b6bc4bfd Change-Id: If77426fcb9f30f3e8b79d7c134053276701a5ecc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/29690 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/cpu/intel/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jonathan Neuschäfer: Looks good to me, approved diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 26b9347..3fad796 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -11,7 +11,6 @@ source src/cpu/intel/model_1067x/Kconfig source src/cpu/intel/model_106cx/Kconfig source src/cpu/intel/model_206ax/Kconfig -source src/cpu/intel/fsp_model_206ax/Kconfig source src/cpu/intel/fsp_model_406dx/Kconfig source src/cpu/intel/model_2065x/Kconfig source src/cpu/intel/model_f2x/Kconfig -- To view, visit https://review.coreboot.org/c/coreboot/+/29690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If77426fcb9f30f3e8b79d7c134053276701a5ecc Gerrit-Change-Number: 29690 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/braswell: Disable OS use of HPET
by Patrick Georgi (Code Review) 21 Nov '18

21 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29655 ) Change subject: soc/intel/braswell: Disable OS use of HPET ...................................................................... soc/intel/braswell: Disable OS use of HPET The timer interrupts don't appear when HPET is enabled. This result in Linux reporting 'MP-BIOS bug: 8254 timer not connected to IO-APIC' Enabling CONFIG_DISABLE_HPET disables OS use of HPET. Intel issue 4800413 (doc #5965535) reports Windows7/Ubuntu Installation Hang or Slow Boot Issue. BUG=Intel #4800413 TEST=Portwell PQ7-M107 Change-Id: Ie9a78dcc736eb057c040a0a303c812adb1f76f3c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/29655 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/acpi/lpc.asl 3 files changed, 15 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Michał Żygowski: Looks good to me, but someone else must approve diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 50c2802..c383cdf 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -128,4 +128,11 @@ string default "soc/intel/braswell/bootblock/timestamp.inc" +config DISABLE_HPET + bool "Disable the HPET device" + default n + help + Enable this to disable the HPET support + Solves the Linux MP-BIOS bug timer not connected. + endif diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 820e56a..e791072 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -4,6 +4,7 @@ * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -486,8 +487,10 @@ acpi_header_t *ssdt2; global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - current = acpi_write_hpet(device, current, rsdp); - current = acpi_align_current(current); + if (!IS_ENABLED(CONFIG_DISABLE_HPET)) { + current = acpi_write_hpet(device, current, rsdp); + current = acpi_align_current(current); + } if (IS_ENABLED(CONFIG_INTEL_GMA_ADD_VBT)) { igd_opregion_t *opregion; diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 0a8b8bc..ce83009 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -47,6 +48,7 @@ }) } +#if !IS_ENABLED(CONFIG_DISABLE_HPET) Device (HPET) { Name (_HID, EISAID("PNP0103")) @@ -62,6 +64,7 @@ Memory32Fixed(ReadOnly, 0xfed00000, 0x400) }) } +#endif Device(PIC) /* 8259 Interrupt Controller */ { -- To view, visit https://review.coreboot.org/c/coreboot/+/29655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a78dcc736eb057c040a0a303c812adb1f76f3c Gerrit-Change-Number: 29655 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: nb/intel/haswell: Move MMCONF_BASE_ADDRESS to northbridge Kconfig
by Patrick Georgi (Code Review) 21 Nov '18

21 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/28603 ) Change subject: nb/intel/haswell: Move MMCONF_BASE_ADDRESS to northbridge Kconfig ...................................................................... nb/intel/haswell: Move MMCONF_BASE_ADDRESS to northbridge Kconfig Change-Id: I44f27405fc8ccbe54c7d19b70327da866390a156 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/28603 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/mainboard/asrock/h81m-hds/Kconfig M src/mainboard/google/beltino/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/intel/baskingridge/Kconfig M src/northbridge/intel/haswell/Kconfig 5 files changed, 4 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Tristan Corrick: Looks good to me, but someone else must approve diff --git a/src/mainboard/asrock/h81m-hds/Kconfig b/src/mainboard/asrock/h81m-hds/Kconfig index f93fcdb..00edd1c 100644 --- a/src/mainboard/asrock/h81m-hds/Kconfig +++ b/src/mainboard/asrock/h81m-hds/Kconfig @@ -74,10 +74,6 @@ int default 8 -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - # # Since this is a desktop board, the assumption is made that most users # would want CMOS configuration enabled by default. diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index aaec9f7..2f51461 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -53,10 +53,6 @@ default "X86 TRICKY TEST 4487" if BOARD_GOOGLE_TRICKY default "X86 ZAKO TEST 8602" if BOARD_GOOGLE_ZAKO -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 738735e..fe7e5b3 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -58,10 +58,6 @@ string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - config MAX_CPUS int default 8 diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index 1fd07c2..2119d47de 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -25,10 +25,6 @@ string default "BASKING RIDGE" -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - config MAX_CPUS int default 16 diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index f9c68f3..0362ffe 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -36,6 +36,10 @@ string default "8086,0166" +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + config CACHE_MRC_SIZE_KB int default 512 -- To view, visit https://review.coreboot.org/c/coreboot/+/28603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44f27405fc8ccbe54c7d19b70327da866390a156 Gerrit-Change-Number: 28603 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI
by Jenny Tc (Code Review) 21 Nov '18

21 Nov '18

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29775 Change subject: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI ...................................................................... SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI With Lazy SCI mask, EC and OS can take over iniitializing the SCI events done by B2_SMI interrupt. Change-Id: I43ca93972fa4d870632707cb9a9e74ab80cbd5d5 Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/ec/google/chromeec/smihandler.c M src/soc/intel/common/Kconfig 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/29775/1 diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c index cab7192..d608db5 100644 --- a/src/ec/google/chromeec/smihandler.c +++ b/src/ec/google/chromeec/smihandler.c @@ -99,6 +99,7 @@ google_chromeec_get_device_current_events(); } +#if IS_ENABLED(CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI) void chromeec_smi_apmc(int apmc, uint64_t sci_mask, uint64_t smi_mask) { switch (apmc) { @@ -114,3 +115,6 @@ break; } } +#else +void chromeec_smi_apmc(int apmc, uint64_t sci_mask, uint64_t smi_mask) { } +#endif diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 27d3f59..9097195 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -65,6 +65,10 @@ bool default n +config SOC_INTEL_BYPASS_PORT_B2_SMI + bool + default n + config TPM_TIS_ACPI_INTERRUPT int help -- To view, visit https://review.coreboot.org/c/coreboot/+/29775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ca93972fa4d870632707cb9a9e74ab80cbd5d5 Gerrit-Change-Number: 29775 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: hostevent: Enable lazy events for SCI mask
by Jenny Tc (Code Review) 21 Nov '18

21 Nov '18

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29774 Change subject: hostevent: Enable lazy events for SCI mask ...................................................................... hostevent: Enable lazy events for SCI mask With Lazy SCI events, dependancy on SMI handler for setting SCI events during boot can be avoided. On boot, coreboot notifies the SCI Lazy mask to EC. Once the EC driver is up in OS, it can notify the EC to convert SCI mask to ACTIVE SCI mask. Change-Id: I6ff3aea2e7f11f1196d8d9ece03ae000354e884b Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_commands.h 3 files changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29774/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index d2a0849..f2a68fd 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -65,6 +65,10 @@ [EC_HOST_EVENT_ALWAYS_REPORT_MASK] = { INVALID_HCMD, INVALID_HCMD, INVALID_HCMD, }, + [EC_HOST_EVENT_LAZY_SCI_MASK] = { + EC_CMD_HOST_EVENT_SET_SCI_MASK, INVALID_HCMD, + EC_CMD_HOST_EVENT_GET_SCI_MASK, + }, [EC_HOST_EVENT_ACTIVE_WAKE_MASK] = { EC_CMD_HOST_EVENT_SET_WAKE_MASK, INVALID_HCMD, EC_CMD_HOST_EVENT_GET_WAKE_MASK, @@ -483,11 +487,13 @@ google_chromeec_log_events(info->log_events | info->s5_wake_events); - if (google_chromeec_is_uhepi_supported()) + if (google_chromeec_is_uhepi_supported()) { google_chromeec_set_lazy_wake_masks (info->s5_wake_events, info->s3_wake_events, info->s0ix_wake_events); + google_chromeec_set_lazy_sci_mask(info->sci_events); + } } /* Clear wake event mask. */ @@ -819,6 +825,12 @@ return google_chromeec_set_mask(EC_HOST_EVENT_SCI_MASK, mask); } +int google_chromeec_set_lazy_sci_mask(uint64_t mask) +{ + printk(BIOS_DEBUG, "Chrome EC: Set SCI mask to 0x%016llx\n", mask); + return google_chromeec_set_mask(EC_HOST_EVENT_LAZY_SCI_MASK, mask); +} + int google_chromeec_set_smi_mask(uint64_t mask) { printk(BIOS_DEBUG, "Chrome EC: Set SMI mask to 0x%016llx\n", mask); diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 70b2b52..ea8cec0 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -28,6 +28,7 @@ uint8_t *buffer, int len, int is_read); uint64_t google_chromeec_get_wake_mask(void); int google_chromeec_set_sci_mask(uint64_t mask); +int google_chromeec_set_lazy_sci_mask(uint64_t mask); int google_chromeec_set_smi_mask(uint64_t mask); int google_chromeec_set_wake_mask(uint64_t mask); u8 google_chromeec_get_event(void); diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 140ba5a..daacb33 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -3465,6 +3465,9 @@ /* Active wake mask */ EC_HOST_EVENT_ACTIVE_WAKE_MASK, + /* Lazy SCI Mask */ + EC_HOST_EVENT_LAZY_SCI_MASK, + /* Lazy wake mask for S0ix */ EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX, -- To view, visit https://review.coreboot.org/c/coreboot/+/29774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff3aea2e7f11f1196d8d9ece03ae000354e884b Gerrit-Change-Number: 29774 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apollolake: Add Kconfig switch to enable max efficiency clock
by Werner Zeh (Code Review) 21 Nov '18

21 Nov '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29772 Change subject: soc/intel/apollolake: Add Kconfig switch to enable max efficiency clock ...................................................................... soc/intel/apollolake: Add Kconfig switch to enable max efficiency clock Add a Kconfig switch to be able to set the CPU clock to maximum efficiency mode. If enabled the CPU will be clocked with the lowest possible frequency while consuming as little power as possible. Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/apollolake/Kconfig 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29772/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0c0fca9..336847a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -370,12 +370,23 @@ config APL_SKIP_SET_POWER_LIMITS bool + depends on !APL_SET_MAX_EFFICIENCY_MODE default n help Some Apollo Lake mainboards do not need the Running Average Power Limits (RAPL) algorithm for a constant power management. Set this config option to skip the RAPL configuration. +config APL_SET_MAX_EFFICIENCY_MODE + bool + depends on !APL_SKIP_SET_POWER_LIMITS + default n + help + If the power budget of the mainboard is limited, it can be useful to + limit the CPU power dissipation at the cost of performance by setting + the lowest possible CPU clock. Enable this option if you need maximum + CPU efficiency. + # M and N divisor values for clock frequency configuration. # These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL -- To view, visit https://review.coreboot.org/c/coreboot/+/29772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073 Gerrit-Change-Number: 29772 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: siemens/mc_apl4: Set CPU clock to maximum efficiency
by Werner Zeh (Code Review) 21 Nov '18

21 Nov '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29773 Change subject: siemens/mc_apl4: Set CPU clock to maximum efficiency ...................................................................... siemens/mc_apl4: Set CPU clock to maximum efficiency The power budget for this mainboard is very limited while the performance demand is low. Set the CPU clock to the lowest value to enable maximum efficiency and thus lowest power dissipation. Change-Id: I23c7c5393deb676b94f2b0ac25e21a7a44cd8cb3 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29773/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index 8e933f2..421c9d3 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -4,5 +4,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select DRIVER_INTEL_I210 + select APL_SET_MAX_EFFICIENCY_MODE endif # BOARD_SIEMENS_MC_APL4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23c7c5393deb676b94f2b0ac25e21a7a44cd8cb3 Gerrit-Change-Number: 29773 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: intelblocks/cpu: Add function to enable maximum efficiency
by Werner Zeh (Code Review) 21 Nov '18

21 Nov '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29771 Change subject: intelblocks/cpu: Add function to enable maximum efficiency ...................................................................... intelblocks/cpu: Add function to enable maximum efficiency Provide a library function to set the CPU frequency to maximum efficiency value. This will result in the lowest possible CPU clock with the lowest possible power consumption. This can be useful in mobile devices where the power dissipation is limited. Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/29771/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 0c042df..1e50dc9 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -141,6 +141,25 @@ } /* + * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with the value + * for maximum efficiency. This value is reported in PLATFORM_INFO MSR (0xCE) + * in Bits 47:40 and is extracted with cpu_get_min_ratio(). + */ +void cpu_set_p_state_to_max_efficiency_ratio(void) +{ + uint32_t min_ratio; + msr_t perf_ctl; + + /* Read the minimum ratio for the best efficiency. */ + min_ratio = cpu_get_min_ratio(); + perf_ctl.lo = (min_ratio << 8) & 0xff00; + perf_ctl.hi = 0; + wrmsr(IA32_PERF_CTL, perf_ctl); + printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", + ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); +} + +/* * Get the Burst/Turbo Mode State from MSR IA32_MISC_ENABLE 0x1A0 * Bit 38 - TURBO_MODE_DISABLE Bit to get state ENABLED / DISABLED. * Also check for the cpuid 0x6 to check whether Burst mode unsupported. diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 88f04b4..8e3313c 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -73,6 +73,13 @@ void cpu_set_p_state_to_max_non_turbo_ratio(void); /* + * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with the value + * for maximum efficiency. This value is reported in PLATFORM_INFO MSR (0xCE) + * in Bits 47:40 and is extracted with cpu_get_min_ratio(). + */ +void cpu_set_p_state_to_max_efficiency_ratio(void); + +/* * Get the Burst/Turbo Mode State from MSR IA32_MISC_ENABLE 0x1A0 * Bit 38 - TURBO_MODE_DISABLE Bit to get state ENABLED / DISABLED. * Also check for the cpuid 0x6 to check whether Burst mode unsupported. -- To view, visit https://review.coreboot.org/c/coreboot/+/29771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Gerrit-Change-Number: 29771 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: payloads/seabios: Update stable from 1.11.2 to 1.12.0
by Philipp Deppenwiese (Code Review) 21 Nov '18

21 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29724 ) Change subject: payloads/seabios: Update stable from 1.11.2 to 1.12.0 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f8364977ce957d3e8d84d7b046d1cec36b8da6a Gerrit-Change-Number: 29724 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-Reviewer: Martin Kepplinger <martink(a)posteo.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 11:46:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2018