coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: Kconfig: Unify power-after-failure options
by Nico Huber (Code Review) 21 Nov '18

21 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29680 ) Change subject: Kconfig: Unify power-after-failure options ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/29680/3/src/soc/intel/common/block/pmc/pmcl… File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/#/c/29680/3/src/soc/intel/common/block/pmc/pmcl… PS3, Line 590: return CONFIG_MAINBOARD_POWER_FAILURE_STATE; > we are ignoring "Keep Previous State" options ? `config MAINBOARD_POWER_FAILURE_STATE` is an `int` taking either 0, 1 or 2. Just what this function used to return. -- To view, visit https://review.coreboot.org/c/coreboot/+/29680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Gerrit-Change-Number: 29680 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 21 Nov 2018 15:02:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/.../Kconfig: Drop SOC_INTEL_COMMON_BLOCK_I2C_DEBUG
by Nico Huber (Code Review) 21 Nov '18

21 Nov '18

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29679 ) Change subject: soc/intel/.../Kconfig: Drop SOC_INTEL_COMMON_BLOCK_I2C_DEBUG ...................................................................... soc/intel/.../Kconfig: Drop SOC_INTEL_COMMON_BLOCK_I2C_DEBUG It's dead. Change-Id: I1fc051937a36878eab23f6022bc42028d5606c83 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/29679 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/i2c/Kconfig 1 file changed, 0 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/common/block/i2c/Kconfig b/src/soc/intel/common/block/i2c/Kconfig index e70796a..b0deb084 100644 --- a/src/soc/intel/common/block/i2c/Kconfig +++ b/src/soc/intel/common/block/i2c/Kconfig @@ -3,11 +3,3 @@ select DRIVERS_I2C_DESIGNWARE help Intel Processor Common I2C support - -config SOC_INTEL_COMMON_BLOCK_I2C_DEBUG - bool "Enable debug output for LPSS I2C transactions" - default n - depends on SOC_INTEL_COMMON_BLOCK_I2C - help - Enable debug output for I2C transactions. This can be useful - when debugging I2C drivers. -- To view, visit https://review.coreboot.org/c/coreboot/+/29679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fc051937a36878eab23f6022bc42028d5606c83 Gerrit-Change-Number: 29679 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/.../Kconfig: Drop SOC_INTEL_COMMON_BLOCK_I2C_DEBUG
by Angel Pons (Code Review) 21 Nov '18

21 Nov '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29679 ) Change subject: soc/intel/.../Kconfig: Drop SOC_INTEL_COMMON_BLOCK_I2C_DEBUG ...................................................................... Patch Set 1: Code-Review+2 According to grep, this thing is used nowhere. Can disappear. -- To view, visit https://review.coreboot.org/c/coreboot/+/29679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fc051937a36878eab23f6022bc42028d5606c83 Gerrit-Change-Number: 29679 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 14:45:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: siemens/mc_apl4: Set CPU clock to minimum ratio
by Nico Huber (Code Review) 21 Nov '18

21 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29773 ) Change subject: siemens/mc_apl4: Set CPU clock to minimum ratio ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23c7c5393deb676b94f2b0ac25e21a7a44cd8cb3 Gerrit-Change-Number: 29773 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Uwe Pöche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 14:37:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratio
by Nico Huber (Code Review) 21 Nov '18

21 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29772 ) Change subject: soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratio ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29772/4/src/soc/intel/apollolake/Kconfig File src/soc/intel/apollolake/Kconfig: https://review.coreboot.org/#/c/29772/4/src/soc/intel/apollolake/Kconfig@388 PS4, Line 388: possible CPU clock. Please mention here too that the OS can/will override. -- To view, visit https://review.coreboot.org/c/coreboot/+/29772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073 Gerrit-Change-Number: 29772 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 21 Nov 2018 14:37:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 21 Nov '18

21 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 16: (2 comments) https://review.coreboot.org/#/c/29563/16/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/16/src/include/memlayout.h@168 PS16, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/16/src/include/memlayout.h@168 PS16, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 16 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 14:34:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: intelblocks/cpu: Add function to set CPU clock to minimum value
by Nico Huber (Code Review) 21 Nov '18

21 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29771 ) Change subject: intelblocks/cpu: Add function to set CPU clock to minimum value ...................................................................... Patch Set 3: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/29771/3/src/soc/intel/common/block/cpu/cpul… File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/#/c/29771/3/src/soc/intel/common/block/cpu/cpul… PS3, Line 159: ((perf_ctl.lo >> 8) & 0xff) this should be `min_ratio`? -- To view, visit https://review.coreboot.org/c/coreboot/+/29771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Gerrit-Change-Number: 29771 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 14:32:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: siemens/mc_apl4: Set CPU clock to minimum ratio
by Werner Zeh (Code Review) 21 Nov '18

21 Nov '18

Hello Mario Scheithauer, Uwe Pöche, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29773 to look at the new patch set (#4). Change subject: siemens/mc_apl4: Set CPU clock to minimum ratio ...................................................................... siemens/mc_apl4: Set CPU clock to minimum ratio The power budget for this mainboard is very limited while the performance demand is low. Set the CPU clock to the lowest value to enable maximum efficiency and thus lowest power dissipation. Change-Id: I23c7c5393deb676b94f2b0ac25e21a7a44cd8cb3 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29773/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23c7c5393deb676b94f2b0ac25e21a7a44cd8cb3 Gerrit-Change-Number: 29773 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Pöche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratio
by Werner Zeh (Code Review) 21 Nov '18

21 Nov '18

Hello Mario Scheithauer, Huang Jin, build bot (Jenkins), Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29772 to look at the new patch set (#4). Change subject: soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratio ...................................................................... soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratio Add a Kconfig switch to be able to set the CPU clock to the lowest possible ratio. If enabled the CPU will consume as little power as possible while providing the lowest performance. Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/cpu.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29772/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073 Gerrit-Change-Number: 29772 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: intelblocks/cpu: Add function to set CPU clock to minimum value
by Werner Zeh (Code Review) 21 Nov '18

21 Nov '18

Hello Mario Scheithauer, Huang Jin, build bot (Jenkins), Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29771 to look at the new patch set (#3). Change subject: intelblocks/cpu: Add function to set CPU clock to minimum value ...................................................................... intelblocks/cpu: Add function to set CPU clock to minimum value Provide a library function to set the CPU frequency to minimum value. This will result in the lowest possible CPU clock with the lowest possible power consumption. This can be useful in mobile devices where the power dissipation is limited. This setting can be overruled by the OS if it has an p-state driver which can adjust the clock to it's need. Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/29771/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Gerrit-Change-Number: 29771 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2018