Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29547 )
Change subject: security/vboot: Add measured boot mode
......................................................................
Patch Set 15:
(4 comments)
https://review.coreboot.org/#/c/29547/12/src/security/vboot/vboot_crtm.c
File src/security/vboot/vboot_crtm.c:
https://review.coreboot.org/#/c/29547/12/src/security/vboot/vboot_crtm.c@70
PS12, Line 70: romstage"
> We do not need the leading slash here.
Done
https://review.coreboot.org/#/c/29547/12/src/security/vboot/vboot_crtm.c@77
PS12, Line 77: romstage"
> We do not need the leading slash here.
Done
https://review.coreboot.org/#/c/29547/12/src/security/vboot/vboot_crtm.c@93
PS12, Line 93: verstage"
> We do not need the leading slash here.
Done
https://review.coreboot.org/#/c/29547/12/src/security/vboot/vboot_crtm.c@100
PS12, Line 100: verstage"
> We do not need the leading slash here.
Done
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Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29771 )
Change subject: intelblocks/cpu: Add function to set CPU clock to minimum value
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/29771/3/src/soc/intel/common/block/cpu/cpul…
File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/#/c/29771/3/src/soc/intel/common/block/cpu/cpul…
PS3, Line 159: ((perf_ctl.lo >> 8) & 0xff)
> this should be `min_ratio`?
Yes Nico, you are so right. I totally overseen it. Thanks for catching, will update.
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Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29772 )
Change subject: soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratio
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/29772/4/src/soc/intel/apollolake/Kconfig
File src/soc/intel/apollolake/Kconfig:
https://review.coreboot.org/#/c/29772/4/src/soc/intel/apollolake/Kconfig@388
PS4, Line 388: possible CPU clock.
> Please mention here too that the OS can/will override.
Sure, will do.
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 )
Change subject: security/tpm: Fix TCPA log feature
......................................................................
Patch Set 19:
(2 comments)
https://review.coreboot.org/#/c/29563/19/src/include/memlayout.h
File src/include/memlayout.h:
https://review.coreboot.org/#/c/29563/19/src/include/memlayout.h@168
PS19, Line 168: #define VBOOT2_TPM_LOG(addr, size) \
Macros with multiple statements should be enclosed in a do - while loop
https://review.coreboot.org/#/c/29563/19/src/include/memlayout.h@168
PS19, Line 168: #define VBOOT2_TPM_LOG(addr, size) \
macros should not use a trailing semicolon
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 )
Change subject: security/tpm: Fix TCPA log feature
......................................................................
Patch Set 18:
(2 comments)
https://review.coreboot.org/#/c/29563/18/src/include/memlayout.h
File src/include/memlayout.h:
https://review.coreboot.org/#/c/29563/18/src/include/memlayout.h@168
PS18, Line 168: #define VBOOT2_TPM_LOG(addr, size) \
Macros with multiple statements should be enclosed in a do - while loop
https://review.coreboot.org/#/c/29563/18/src/include/memlayout.h@168
PS18, Line 168: #define VBOOT2_TPM_LOG(addr, size) \
macros should not use a trailing semicolon
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 )
Change subject: security/tpm: Fix TCPA log feature
......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/#/c/29563/17/src/include/memlayout.h
File src/include/memlayout.h:
https://review.coreboot.org/#/c/29563/17/src/include/memlayout.h@168
PS17, Line 168: #define VBOOT2_TPM_LOG(addr, size) \
Macros with multiple statements should be enclosed in a do - while loop
https://review.coreboot.org/#/c/29563/17/src/include/memlayout.h@168
PS17, Line 168: #define VBOOT2_TPM_LOG(addr, size) \
macros should not use a trailing semicolon
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29682 )
Change subject: soc/intel/skylake: Use real common code for VMX init
......................................................................
Patch Set 3:
while there is no issue with using the common VMX implementation (tested on Librem 13v2), selecting the VMX lock function (which is selected by default) will prevent the use of SGX on supported platforms due to both being controlled by the IA32_FEATURE_CONTROL msr.
The locking of IA32_FEATURE_CONTROL should really be broken out into a separate function and performed after both VMX and SGX configuration if enabled, preferably as an antecedent to this commit.
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Hello Chris Wang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/29779
to review the following change.
Change subject: mb/google/kahlee: Enable 2T mode for liara in DVT phase
......................................................................
mb/google/kahlee: Enable 2T mode for liara in DVT phase
Change the board id detection to support rev5, since the 2T mode still
needed in DVT build.
BUG=b:116082728
TEST=verify by ODM.
Change-Id: Ibb4cc1fd2bb54984cb7a8856ed7b9f49b78eddce
Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com>
---
M src/mainboard/google/kahlee/OemCustomize.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/29779/1
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index 12e5072..fc8ff32 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -58,7 +58,7 @@
void OemPostParams(AMD_POST_PARAMS *PostParams)
{
- if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 4))
+ if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 5))
PostParams->MemConfig.PlatformMemoryConfiguration =
(PSO_ENTRY *)DDR4LiaraMemoryConfiguration;
else
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Joel Kitching has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29776 )
Change subject: util/cbfstool: Fix GCC error due to a shadowed declaration
......................................................................
Patch Set 2: Code-Review+2
Thanks for catching this, Werner! Although I do wonder, is buffer_size the best name for a function?
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