coreboot-gerrit November 2018

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Change in ...coreboot[master]: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI
by Jenny Tc (Code Review) 22 Nov '18

22 Nov '18

Jenny Tc has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29775 ) Change subject: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29775/1/src/ec/google/chromeec/smihandler.c File src/ec/google/chromeec/smihandler.c: https://review.coreboot.org/#/c/29775/1/src/ec/google/chromeec/smihandler.c… PS1, Line 102: #if IS_ENABLED(CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI) > one alternative way to achieve this is https://review.coreboot. […] Okay.. What about using CONFIG_REDUCED_SMI just to remove the function definition in order to reduce the image size? -- To view, visit https://review.coreboot.org/c/coreboot/+/29775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ca93972fa4d870632707cb9a9e74ab80cbd5d5 Gerrit-Change-Number: 29775 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 22 Nov 2018 04:42:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI
by Dhaval Sharma (Code Review) 22 Nov '18

22 Nov '18

Dhaval Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29775 ) Change subject: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29775/1/src/ec/google/chromeec/smihandler.c File src/ec/google/chromeec/smihandler.c: https://review.coreboot.org/#/c/29775/1/src/ec/google/chromeec/smihandler.c… PS1, Line 102: #if IS_ENABLED(CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI) one alternative way to achieve this is https://review.coreboot.org/#/c/coreboot/+/28696/2/src/soc/intel/skylake/ac…. In that case you can leave these hooks as is; just ensure that while filling up ACPI table you don't provide port B2 entry. Making it 0 causes OS to know that SMI is not supported. -- To view, visit https://review.coreboot.org/c/coreboot/+/29775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ca93972fa4d870632707cb9a9e74ab80cbd5d5 Gerrit-Change-Number: 29775 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 22 Nov 2018 03:47:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI
by Dhaval Sharma (Code Review) 22 Nov '18

22 Nov '18

Dhaval Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29775 ) Change subject: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI ...................................................................... Patch Set 1: Let us add a bit more description: "Port B2 SMI is used to enable ACPI mode when OS is ACPI aware. This patch provides a way to make SW SMI optional using alternative communication mechanism between OS and EC" -- To view, visit https://review.coreboot.org/c/coreboot/+/29775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ca93972fa4d870632707cb9a9e74ab80cbd5d5 Gerrit-Change-Number: 29775 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 22 Nov 2018 03:44:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI
by Nico Huber (Code Review) 21 Nov '18

21 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29775 ) Change subject: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI ...................................................................... Patch Set 1: (1 comment) If the Kconfig option is used in ec/google/chromeec, it should also be defined there (and named accordingly). https://review.coreboot.org/#/c/29775/1/src/ec/google/chromeec/smihandler.c File src/ec/google/chromeec/smihandler.c: https://review.coreboot.org/#/c/29775/1/src/ec/google/chromeec/smihandler.c… PS1, Line 103: A nicer way to code it in C would be to put something like this here: if (IS_ENABLED(CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI)) return; The compiler would take care of the dead code but it would still be compile tested (no matter the config state). -- To view, visit https://review.coreboot.org/c/coreboot/+/29775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ca93972fa4d870632707cb9a9e74ab80cbd5d5 Gerrit-Change-Number: 29775 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 21 Nov 2018 23:03:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/octopus/var/phaser: Deprecate board id 0
by Furquan Shaikh (Code Review) 21 Nov '18

21 Nov '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29787 Change subject: mb/google/octopus/var/phaser: Deprecate board id 0 ...................................................................... mb/google/octopus/var/phaser: Deprecate board id 0 This change gets rid of bid0_override_table as part of clean up effort to deprecate bid0. Additionally, it updates the touchscreen enable GPIO in overridetree and gets rid of variant.c to update enable gpio at runtime. BUG=b:119885949 Change-Id: I527973747e7d81ec47997da57eeb15f38d3ac2fd Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/phaser/gpio.c M src/mainboard/google/octopus/variants/phaser/overridetree.cb M src/mainboard/google/octopus/variants/phaser/variant.c 3 files changed, 11 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/29787/1 diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c index 2a5dfbc..322b44b 100644 --- a/src/mainboard/google/octopus/variants/phaser/gpio.c +++ b/src/mainboard/google/octopus/variants/phaser/gpio.c @@ -68,36 +68,19 @@ PAD_NC(GPIO_214, DN_20K), }; -static const struct pad_config bid0_override_table[] = { - PAD_NC(GPIO_52, UP_20K), - PAD_NC(GPIO_53, UP_20K), - PAD_NC(GPIO_67, UP_20K), - PAD_NC(GPIO_117, UP_20K), - PAD_NC(GPIO_143, UP_20K), - PAD_NC(GPIO_161, DN_20K), - PAD_NC(GPIO_214, DN_20K), -}; - const struct pad_config *variant_override_gpio_table(size_t *num) { const struct pad_config *c; uint32_t sku_id = SKU_UNKNOWN; - switch (board_id()) { - case 0: - case UNDEFINED_STRAPPING_ID: - c = bid0_override_table; - *num = ARRAY_SIZE(bid0_override_table); - break; - default: - google_chromeec_cbi_get_sku_id(&sku_id); - if (sku_id == 1) { - c = sku1_default_override_table; - *num = ARRAY_SIZE(sku1_default_override_table); - } else { - c = default_override_table; - *num = ARRAY_SIZE(default_override_table); - } + google_chromeec_cbi_get_sku_id(&sku_id); + if (sku_id == 1) { + c = sku1_default_override_table; + *num = ARRAY_SIZE(sku1_default_override_table); + } else { + c = default_override_table; + *num = ARRAY_SIZE(default_override_table); } + return c; } diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index cd92dcb..f996d8b 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -99,7 +99,7 @@ register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" device i2c 10 on end @@ -110,7 +110,7 @@ register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" register "generic.reset_delay_ms" = "45" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" diff --git a/src/mainboard/google/octopus/variants/phaser/variant.c b/src/mainboard/google/octopus/variants/phaser/variant.c index 996ea1f..494b3ad 100644 --- a/src/mainboard/google/octopus/variants/phaser/variant.c +++ b/src/mainboard/google/octopus/variants/phaser/variant.c @@ -13,75 +13,26 @@ * GNU General Public License for more details. */ -#include <arch/acpi_device.h> #include <baseboard/variants.h> -#include <boardid.h> -#include <device/device.h> -#include <drivers/i2c/generic/chip.h> -#include <drivers/i2c/hid/chip.h> -#include <soc/gpio.h> #include <soc/pci_devs.h> #include <string.h> #include <ec/google/chromeec/ec.h> #define SKU_UNKNOWN 0xFFFFFFFF -extern struct chip_operations drivers_i2c_generic_ops; -extern struct chip_operations drivers_i2c_hid_ops; - void variant_update_devtree(struct device *dev) { - uint32_t bid; uint32_t sku_id = SKU_UNKNOWN; struct device *touchscreen_i2c_host; - struct device *child; - const struct bus *children_bus; - static const struct acpi_gpio new_enable_gpio = - ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146); - - bid = board_id(); - - /* Nothing to update. */ - if (bid == UNDEFINED_STRAPPING_ID || bid < 1) - return; touchscreen_i2c_host = dev_find_slot(0, PCH_DEVFN_I2C7); if (touchscreen_i2c_host == NULL) return; - /* According to the sku id decide whether update touch - * screen device information: - * 1. sku id is 1 then dev->enabled = 0. - */ + /* SKU ID 1 does not have a touchscreen device, hence disable it. */ google_chromeec_cbi_get_sku_id(&sku_id); if (sku_id == 1) { touchscreen_i2c_host->enabled = 0; - return; - } - - children_bus = touchscreen_i2c_host->link_list; - child = NULL; - - /* Find all children on bus to update touchscreen enable gpio. */ - while ((child = dev_bus_each_child(children_bus, child)) != NULL) { - struct drivers_i2c_generic_config *cfg; - - /* No configration to change. */ - if (child->chip_info == NULL) - continue; - - if (child->chip_ops == &drivers_i2c_generic_ops) - cfg = child->chip_info; - else if (child->chip_ops == &drivers_i2c_hid_ops) { - struct drivers_i2c_hid_config *hid_cfg; - hid_cfg = child->chip_info; - cfg = &hid_cfg->generic; - } else - continue; - - /* Update the enable gpio. */ - memcpy(&cfg->enable_gpio, &new_enable_gpio, - sizeof(new_enable_gpio)); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/29787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I527973747e7d81ec47997da57eeb15f38d3ac2fd Gerrit-Change-Number: 29787 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus/var/fleex: Deprecate bid 0
by Furquan Shaikh (Code Review) 21 Nov '18

21 Nov '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29785 Change subject: mb/google/octopus/var/fleex: Deprecate bid 0 ...................................................................... mb/google/octopus/var/fleex: Deprecate bid 0 This change gets rid of bid0_override_table as part of clean up effort to deprecate bid0. Additionally, it updates the touchscreen enable GPIO in overridetree and gets rid of variant.c to update enable gpio at runtime. BUG=b:119885949 Change-Id: If14abb324d9422720ca4d0f0859e092319d454ee Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/fleex/Makefile.inc M src/mainboard/google/octopus/variants/fleex/gpio.c M src/mainboard/google/octopus/variants/fleex/overridetree.cb D src/mainboard/google/octopus/variants/fleex/variant.c 4 files changed, 4 insertions(+), 106 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/29785/1 diff --git a/src/mainboard/google/octopus/variants/fleex/Makefile.inc b/src/mainboard/google/octopus/variants/fleex/Makefile.inc index d54ed40..9fb63f5 100644 --- a/src/mainboard/google/octopus/variants/fleex/Makefile.inc +++ b/src/mainboard/google/octopus/variants/fleex/Makefile.inc @@ -1,4 +1,3 @@ bootblock-y += gpio.c -ramstage-y += variant.c ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 920d2c2..39d239b 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -52,37 +52,9 @@ PAD_NC(GPIO_214, DN_20K), }; -static const struct pad_config bid0_override_table[] = { - PAD_NC(GPIO_50, UP_20K), - PAD_NC(GPIO_51, UP_20K), - PAD_NC(GPIO_52, UP_20K), - PAD_NC(GPIO_53, UP_20K), - PAD_NC(GPIO_67, UP_20K), - PAD_NC(GPIO_117, UP_20K), - PAD_NC(GPIO_138, DN_20K), - PAD_NC(GPIO_139, DN_20K), - PAD_NC(GPIO_140, UP_20K), - PAD_NC(GPIO_143, UP_20K), - PAD_NC(GPIO_144, UP_20K), - PAD_NC(GPIO_145, UP_20K), - PAD_NC(GPIO_161, UP_20K), - PAD_NC(GPIO_214, DN_20K), -}; - const struct pad_config *variant_override_gpio_table(size_t *num) { - const struct pad_config *c; + *num = ARRAY_SIZE(default_override_table); - switch (board_id()) { - case 0: - case UNDEFINED_STRAPPING_ID: - c = bid0_override_table; - *num = ARRAY_SIZE(bid0_override_table); - break; - default: - c = default_override_table; - *num = ARRAY_SIZE(default_override_table); - } - - return c; + return default_override_table; } diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 9383662..bcf771b 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -78,7 +78,7 @@ register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" device i2c 10 on end @@ -90,7 +90,7 @@ register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "130" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" register "generic.enable_delay_ms" = "2" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" diff --git a/src/mainboard/google/octopus/variants/fleex/variant.c b/src/mainboard/google/octopus/variants/fleex/variant.c deleted file mode 100644 index 7ba9401..0000000 --- a/src/mainboard/google/octopus/variants/fleex/variant.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi_device.h> -#include <baseboard/variants.h> -#include <boardid.h> -#include <device/device.h> -#include <drivers/i2c/generic/chip.h> -#include <drivers/i2c/hid/chip.h> -#include <soc/gpio.h> -#include <soc/pci_devs.h> -#include <string.h> - -extern struct chip_operations drivers_i2c_generic_ops; -extern struct chip_operations drivers_i2c_hid_ops; - -void variant_update_devtree(struct device *dev) -{ - uint32_t bid; - struct device *touchscreen_i2c_host; - struct device *child; - const struct bus *children_bus; - static const struct acpi_gpio new_enable_gpio = - ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146); - - bid = board_id(); - - /* Nothing to update. */ - if (bid == UNDEFINED_STRAPPING_ID || bid < 1) - return; - - touchscreen_i2c_host = dev_find_slot(0, PCH_DEVFN_I2C7); - - if (touchscreen_i2c_host == NULL) - return; - - children_bus = touchscreen_i2c_host->link_list; - child = NULL; - - /* Find all children on bus to update touchscreen enable gpio. */ - while ((child = dev_bus_each_child(children_bus, child)) != NULL) { - struct drivers_i2c_generic_config *cfg; - - /* No configration to change. */ - if (child->chip_info == NULL) - continue; - - if (child->chip_ops == &drivers_i2c_generic_ops) - cfg = child->chip_info; - else if (child->chip_ops == &drivers_i2c_hid_ops) { - struct drivers_i2c_hid_config *hid_cfg; - hid_cfg = child->chip_info; - cfg = &hid_cfg->generic; - } else - continue; - - /* Update the enable gpio. */ - memcpy(&cfg->enable_gpio, &new_enable_gpio, - sizeof(new_enable_gpio)); - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/29785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If14abb324d9422720ca4d0f0859e092319d454ee Gerrit-Change-Number: 29785 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus/var/bobba: Deprecate board id < 2
by Furquan Shaikh (Code Review) 21 Nov '18

21 Nov '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29786 Change subject: mb/google/octopus/var/bobba: Deprecate board id < 2 ...................................................................... mb/google/octopus/var/bobba: Deprecate board id < 2 This change deprecates boards with id < 2. It updates touchscreen enable GPIO in overridetree and gets rid of variant.c to update enable GPIO at runtime. Additionally, it configures old enable GPIO as NC. BUG=b:119885949 Change-Id: I42fb7ef90e421118a8fdfa0d343d0bcf4a9bc087 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/bobba/Makefile.inc M src/mainboard/google/octopus/variants/bobba/gpio.c M src/mainboard/google/octopus/variants/bobba/overridetree.cb D src/mainboard/google/octopus/variants/bobba/variant.c 4 files changed, 7 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/29786/1 diff --git a/src/mainboard/google/octopus/variants/bobba/Makefile.inc b/src/mainboard/google/octopus/variants/bobba/Makefile.inc index d54ed40..9fb63f5 100644 --- a/src/mainboard/google/octopus/variants/bobba/Makefile.inc +++ b/src/mainboard/google/octopus/variants/bobba/Makefile.inc @@ -1,4 +1,3 @@ bootblock-y += gpio.c -ramstage-y += variant.c ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index 1b5c0bb..acdcf97 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -32,20 +32,13 @@ /* EN_PP3300_WLAN_L */ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), + + PAD_NC(GPIO_213, DN_20K), }; const struct pad_config *variant_override_gpio_table(size_t *num) { - const struct pad_config *c = NULL; - switch (board_id()) { - case 0: - case 1: - case UNDEFINED_STRAPPING_ID: - *num = 0; - break; - default: - c = default_override_table; - *num = ARRAY_SIZE(default_override_table); - } - return c; + *num = ARRAY_SIZE(default_override_table); + + return default_override_table; } diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index dab13a5..c0f37e2 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -102,7 +102,7 @@ register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" device i2c 10 on end @@ -114,7 +114,7 @@ register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "1" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" register "enable_delay_ms" = "50" register "has_power_resource" = "1" device i2c 39 on end diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c deleted file mode 100644 index 200f460..0000000 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi_device.h> -#include <baseboard/variants.h> -#include <boardid.h> -#include <device/device.h> -#include <drivers/i2c/generic/chip.h> -#include <drivers/i2c/hid/chip.h> -#include <soc/gpio.h> -#include <soc/pci_devs.h> -#include <string.h> - -extern struct chip_operations drivers_i2c_generic_ops; -extern struct chip_operations drivers_i2c_hid_ops; - -void variant_update_devtree(struct device *dev) -{ - uint32_t bid; - struct device *touchscreen_i2c_host; - struct device *child; - const struct bus *children_bus; - static const struct acpi_gpio new_enable_gpio = - ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146); - - bid = board_id(); - - /* Nothing to update. */ - if (bid == UNDEFINED_STRAPPING_ID || bid < 2) - return; - - touchscreen_i2c_host = dev_find_slot(0, PCH_DEVFN_I2C7); - - if (touchscreen_i2c_host == NULL) - return; - - children_bus = touchscreen_i2c_host->link_list; - child = NULL; - - /* Find all children on bus to update touchscreen enable gpio. */ - while ((child = dev_bus_each_child(children_bus, child)) != NULL) { - struct drivers_i2c_generic_config *cfg; - - /* No configration to change. */ - if (child->chip_info == NULL) - continue; - - if (child->chip_ops == &drivers_i2c_generic_ops) - cfg = child->chip_info; - else if (child->chip_ops == &drivers_i2c_hid_ops) { - struct drivers_i2c_hid_config *hid_cfg; - hid_cfg = child->chip_info; - cfg = &hid_cfg->generic; - } else - continue; - - /* Update the enable gpio. */ - memcpy(&cfg->enable_gpio, &new_enable_gpio, - sizeof(new_enable_gpio)); - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/29786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42fb7ef90e421118a8fdfa0d343d0bcf4a9bc087 Gerrit-Change-Number: 29786 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/google/octopus: Update GPIO_178 in early_gpio_table in baseboard
by Furquan Shaikh (Code Review) 21 Nov '18

21 Nov '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29784 Change subject: mb/google/octopus: Update GPIO_178 in early_gpio_table in baseboard ...................................................................... mb/google/octopus: Update GPIO_178 in early_gpio_table in baseboard This change updates the configuration of GPIO_178 to be active low as per latest revision on different octopus variants. This effectively: 1. Gets rid of early_gpio_table in different variants -- phaser, meep, fleex, bobba. 2. Deprecates board id < 2 for bobba, board id < 1 for fleex and phaser. 3. Adds special early_gpio_table in yorp which has GPIO_178 as an active high signal. BUG=b:119885949 Change-Id: I024199a8f1f96db57f8fa60c4d265789cd3a0493 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/bobba/gpio.c M src/mainboard/google/octopus/variants/fleex/gpio.c M src/mainboard/google/octopus/variants/meep/gpio.c M src/mainboard/google/octopus/variants/phaser/gpio.c A src/mainboard/google/octopus/variants/yorp/Makefile.inc A src/mainboard/google/octopus/variants/yorp/gpio.c 7 files changed, 55 insertions(+), 172 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29784/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 28dfaef..877cd76 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -308,7 +308,7 @@ PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ /* Enable power to wifi early in bootblock and de-assert PERST#. */ - PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ + PAD_CFG_GPO(GPIO_178, 0, DEEP), /* EN_PP3300_WLAN_L */ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index 6b471e5..1b5c0bb 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -49,48 +49,3 @@ } return c; } - -/* GPIOs needed prior to ramstage. */ -static const struct pad_config early_gpio_table[] = { - /* PCH_WP_OD */ - PAD_CFG_GPI(GPIO_190, NONE, DEEP), - /* H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, - DISPUPD), - /* H1_SLAVE_SPI_CLK_R */ - PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_CS_L_R */ - PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MISO */ - PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), - - /* WLAN_PE_RST */ - PAD_CFG_GPO(GPIO_164, 0, DEEP), - - /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak - * pull-up for proper operation. Since there is no external pull present - * on this platform, configure an internal weak pull-up. - */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, - ENPU), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - /* - * This is a hack to configure EN_PP3300_WLAN based on board id. Once - * board id 0/1 is deprecated, we can get rid of this. - */ - uint32_t bid = board_id(); - - if (bid == UNDEFINED_STRAPPING_ID || bid < 2) - gpio_output(GPIO_178, 1); - else - gpio_output(GPIO_178, 0); - - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index ea7faf3..920d2c2 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -86,48 +86,3 @@ return c; } - -/* GPIOs needed prior to ramstage. */ -static const struct pad_config early_gpio_table[] = { - /* PCH_WP_OD */ - PAD_CFG_GPI(GPIO_190, NONE, DEEP), - /* H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, - DISPUPD), - /* H1_SLAVE_SPI_CLK_R */ - PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_CS_L_R */ - PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MISO */ - PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), - - /* WLAN_PE_RST */ - PAD_CFG_GPO(GPIO_164, 0, DEEP), - - /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak - * pull-up for proper operation. Since there is no external pull present - * on this platform, configure an internal weak pull-up. - */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, - ENPU), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - /* - * This is a hack to configure EN_PP3300_WLAN based on board id. Once - * board id 0 is deprecated, we can get rid of this. - */ - uint32_t bid = board_id(); - - if (bid == UNDEFINED_STRAPPING_ID || bid < 1) - gpio_output(GPIO_178, 1); - else - gpio_output(GPIO_178, 0); - - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 823224c..7e57287 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -38,39 +38,3 @@ *num = ARRAY_SIZE(default_override_table); return default_override_table; } - -/* GPIOs needed prior to ramstage. */ -static const struct pad_config early_gpio_table[] = { - /* PCH_WP_OD */ - PAD_CFG_GPI(GPIO_190, NONE, DEEP), - /* H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, - DISPUPD), - /* H1_SLAVE_SPI_CLK_R */ - PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_CS_L_R */ - PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MISO */ - PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), - - PAD_CFG_GPO(GPIO_178, 0, DEEP), - - /* WLAN_PE_RST */ - PAD_CFG_GPO(GPIO_164, 0, DEEP), - - /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak - * pull-up for proper operation. Since there is no external pull present - * on this platform, configure an internal weak pull-up. - */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, - ENPU), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c index 4d3210c..2a5dfbc 100644 --- a/src/mainboard/google/octopus/variants/phaser/gpio.c +++ b/src/mainboard/google/octopus/variants/phaser/gpio.c @@ -101,48 +101,3 @@ } return c; } - -/* GPIOs needed prior to ramstage. */ -static const struct pad_config early_gpio_table[] = { - /* PCH_WP_OD */ - PAD_CFG_GPI(GPIO_190, NONE, DEEP), - /* H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, - DISPUPD), - /* H1_SLAVE_SPI_CLK_R */ - PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_CS_L_R */ - PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MISO */ - PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), - /* H1_SLAVE_SPI_MOSI_R */ - PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), - - /* WLAN_PE_RST */ - PAD_CFG_GPO(GPIO_164, 0, DEEP), - - /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak - * pull-up for proper operation. Since there is no external pull present - * on this platform, configure an internal weak pull-up. - */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, - ENPU), -}; - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - /* - * This is a hack to configure EN_PP3300_WLAN based on board id. Once - * board id 0 is deprecated, we can get rid of this. - */ - uint32_t bid = board_id(); - - if (bid == UNDEFINED_STRAPPING_ID || bid < 1) - gpio_output(GPIO_178, 1); - else - gpio_output(GPIO_178, 0); - - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} diff --git a/src/mainboard/google/octopus/variants/yorp/Makefile.inc b/src/mainboard/google/octopus/variants/yorp/Makefile.inc new file mode 100644 index 0000000..4b48156 --- /dev/null +++ b/src/mainboard/google/octopus/variants/yorp/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/yorp/gpio.c b/src/mainboard/google/octopus/variants/yorp/gpio.c new file mode 100644 index 0000000..5719888 --- /dev/null +++ b/src/mainboard/google/octopus/variants/yorp/gpio.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/gpio.h> + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */ + /* GSPI0_INT */ + PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, + DISPUPD), /* H1_PCH_INT_ODL */ + /* GSPI0_CLK */ + PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */ + /* GSPI0_CS# */ + PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */ + /* GSPI0_MISO */ + PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */ + /* GSPI0_MOSI */ + PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ + + /* Enable power to wifi early in bootblock and de-assert PERST#. */ + PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ + PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ + + /* + * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * pull-up for proper operation. Since there is no external pull present + * on this platform, configure an internal weak pull-up. + */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, + ENPU), /* ESPI_IO1 */ +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I024199a8f1f96db57f8fa60c4d265789cd3a0493 Gerrit-Change-Number: 29784 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: (console, drivers/uart)/Kconfig: Fix dependencies
by Nico Huber (Code Review) 21 Nov '18

21 Nov '18

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29572 ) Change subject: (console,drivers/uart)/Kconfig: Fix dependencies ...................................................................... (console,drivers/uart)/Kconfig: Fix dependencies The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART, because it's using its interface. The individual UART drivers select DRIVERS_UART, because they implement the interface and depend on the common UART code. Some guards had to be fixed (using CONSOLE_SERIAL now instead of DRIVERS_UART). Some other guards that were only about compilation of units were removed. We want to build test as much as possible, right? Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/29572 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/console/Kconfig M src/cpu/allwinner/a10/Makefile.inc M src/cpu/ti/am335x/Makefile.inc M src/drivers/uart/Kconfig M src/mainboard/google/gru/bootblock.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_rialto/bootblock.c M src/soc/broadcom/cygnus/Makefile.inc M src/soc/cavium/cn81xx/Makefile.inc M src/soc/imgtec/pistachio/Makefile.inc M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8183/Makefile.inc M src/soc/nvidia/tegra124/Makefile.inc M src/soc/nvidia/tegra210/Makefile.inc M src/soc/qualcomm/ipq40xx/Makefile.inc M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq806x/Makefile.inc M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/sdm845/Makefile.inc M src/soc/rockchip/rk3288/Makefile.inc M src/soc/rockchip/rk3399/Makefile.inc M src/soc/samsung/exynos5250/Makefile.inc M src/soc/samsung/exynos5420/Makefile.inc 24 files changed, 64 insertions(+), 102 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/console/Kconfig b/src/console/Kconfig index 318ca18..e7e3298 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -29,7 +29,7 @@ config CONSOLE_SERIAL bool "Serial port console output" default y - depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL + depends on DRIVERS_UART help Send coreboot debug output to a serial port. diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 152d765..a6cd4b4 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -21,11 +21,9 @@ ramstage-y += timer.c ramstage-y += twi.c -ifeq ($(CONFIG_DRIVERS_UART),y) -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c uart_console.c +bootblock-y += uart.c uart_console.c romstage-y += uart.c uart_console.c ramstage-y += uart.c uart_console.c -endif real-target: $(obj)/BOOT0 diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index 5b91981..24a79dd 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -12,11 +12,9 @@ ramstage-y += nand.c ramstage-y += cbmem.c -ifeq ($(CONFIG_DRIVERS_UART),y) -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +bootblock-y += uart.c romstage-y += uart.c ramstage-y += uart.c -endif $(call add-class,omap-header) $(eval $(call create_class_compiler,omap-header,arm)) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 1130aeb..1f23a19 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -1,7 +1,5 @@ config DRIVERS_UART bool - default y if CONSOLE_SERIAL - default n config DRIVERS_UART_8250IO # FIXME: Shouldn't have a prompt, should default to n, and @@ -11,6 +9,7 @@ default n if DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL default n if NO_UART_ON_SUPERIO default y + select DRIVERS_UART config DRIVERS_UART_8250IO_SKIP_INIT def_bool n @@ -37,6 +36,7 @@ config DRIVERS_UART_8250MEM bool default n + select DRIVERS_UART config DRIVERS_UART_8250MEM_32 bool @@ -46,6 +46,7 @@ config HAVE_UART_SPECIAL bool default n + select DRIVERS_UART config DRIVERS_UART_OXPCIE bool "Oxford OXPCIe952" diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 0013414..b2f7d57 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -49,16 +49,16 @@ if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) gpio_output(GPIO_P15V_EN, 1); /* Scarlet: EC-controlled */ -#if IS_ENABLED(CONFIG_DRIVERS_UART) - _Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE, - "CONSOLE_SERIAL_UART should be UART2"); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + _Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE, + "CONSOLE_SERIAL_UART should be UART2"); - /* iomux: select gpio4c[4:3] as uart2 dbg port */ - write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C); + /* iomux: select gpio4c[4:3] as uart2 dbg port */ + write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C); - /* grf soc_con7[11:10] use for uart2 select */ - write32(&rk3399_grf->soc_con7, UART2C_SEL); -#endif + /* grf soc_con7[11:10] use for uart2 select */ + write32(&rk3399_grf->soc_con7, UART2C_SEL); + } } static void configure_spi_flash(void) diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c index 5126ce5..8648a3c 100644 --- a/src/mainboard/google/veyron/bootblock.c +++ b/src/mainboard/google/veyron/bootblock.c @@ -31,11 +31,10 @@ void bootblock_mainboard_early_init() { - if (IS_ENABLED(CONFIG_DRIVERS_UART)) { + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); write32(&rk3288_grf->iomux_uart2, IOMUX_UART2); } - } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index 1110a0b..28f6b14 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -31,11 +31,10 @@ void bootblock_mainboard_early_init() { - if (IS_ENABLED(CONFIG_DRIVERS_UART)) { + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); write32(&rk3288_grf->iomux_uart2, IOMUX_UART2); } - } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index 1ba01fb..626d987 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -31,11 +31,10 @@ void bootblock_mainboard_early_init() { - if (IS_ENABLED(CONFIG_DRIVERS_UART)) { + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); write32(&rk3288_grf->iomux_uart2, IOMUX_UART2); } - } void bootblock_mainboard_init(void) diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc index cfbaaa7..21c5806 100644 --- a/src/soc/broadcom/cygnus/Makefile.inc +++ b/src/soc/broadcom/cygnus/Makefile.inc @@ -23,13 +23,13 @@ bootblock-y += hw_init.c bootblock-$(CONFIG_SPI_FLASH) += spi.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += ns16550.c +bootblock-y += ns16550.c endif verstage-y += i2c.c verstage-y += timer.c verstage-$(CONFIG_SPI_FLASH) += spi.c -verstage-$(CONFIG_DRIVERS_UART) += ns16550.c +verstage-y += ns16550.c romstage-y += cbmem.c romstage-y += i2c.c @@ -37,7 +37,7 @@ romstage-y += romstage.c romstage-y += sdram.c romstage-$(CONFIG_SPI_FLASH) += spi.c -romstage-$(CONFIG_DRIVERS_UART) += ns16550.c +romstage-y += ns16550.c romstage-y += ddr_init.c romstage-y += ddr_init_table.c romstage-y += shmoo_and28.c @@ -53,7 +53,7 @@ ramstage-y += soc.c ramstage-y += timer.c ramstage-$(CONFIG_SPI_FLASH) += spi.c -ramstage-$(CONFIG_DRIVERS_UART) += ns16550.c +ramstage-y += ns16550.c ramstage-y += usb.c CPPFLAGS_common += -Isrc/soc/broadcom/cygnus/include/ diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc index ede7d73..3a36bfa 100644 --- a/src/soc/cavium/cn81xx/Makefile.inc +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -25,9 +25,6 @@ bootblock-y += spi.c bootblock-y += uart.c bootblock-y += cpu.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += uart.c -endif ################################################################################ # verstage @@ -37,7 +34,7 @@ verstage-y += gpio.c verstage-y += timer.c verstage-y += spi.c -verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-y += uart.c verstage-y += cbmem.c ################################################################################ @@ -49,7 +46,6 @@ romstage-y += timer.c romstage-y += spi.c romstage-y += uart.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += cbmem.c romstage-y += sdram.c @@ -64,7 +60,6 @@ ramstage-y += timer.c ramstage-y += spi.c ramstage-y += uart.c -ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += sdram.c ramstage-y += soc.c ramstage-y += cpu.c diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index 78e7789..6e8d539 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -22,11 +22,9 @@ romstage-y += spi.c ramstage-y += spi.c -ifeq ($(CONFIG_DRIVERS_UART),y) -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +bootblock-y += uart.c romstage-y += uart.c ramstage-y += uart.c -endif bootblock-y += monotonic_timer.c diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index b2a5ebd..b004c27 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -23,9 +23,7 @@ bootblock-y += ../common/timer.c bootblock-y += timer.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c -endif +bootblock-y += ../common/uart.c bootblock-y += ../common/gpio.c gpio.c gpio_init.c bootblock-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c @@ -37,7 +35,7 @@ verstage-y += i2c.c verstage-y += ../common/spi.c spi.c -verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +verstage-y += ../common/uart.c verstage-y += ../common/timer.c verstage-y += timer.c @@ -53,7 +51,7 @@ romstage-y += timer.c romstage-y += i2c.c -romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +romstage-y += ../common/uart.c romstage-y += ../common/cbmem.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/spi.c spi.c @@ -72,7 +70,7 @@ ramstage-y += soc.c ../common/mtcmos.c ramstage-y += ../common/timer.c ramstage-y += timer.c -ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +ramstage-y += ../common/uart.c ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c i2c.c ramstage-y += mt6311.c ramstage-y += da9212.c diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index bd81258..9fff52f 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -6,9 +6,7 @@ bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c -endif +bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c decompressor-y += decompressor.c @@ -19,7 +17,7 @@ verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c -verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +verstage-y += ../common/uart.c verstage-y += ../common/wdt.c romstage-y += auxadc.c @@ -32,7 +30,7 @@ romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c -romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +romstage-y += ../common/uart.c romstage-y += ../common/wdt.c ramstage-y += auxadc.c @@ -43,7 +41,7 @@ ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += ../common/timer.c -ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 2f0f470..fb5389f 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -16,15 +16,13 @@ bootblock-y += ../tegra/pingroup.c bootblock-y += ../tegra/pinmux.c bootblock-y += ../tegra/apbmisc.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += uart.c -endif +bootblock-y += uart.c verstage-y += verstage.c verstage-y += dma.c verstage-y += monotonic_timer.c verstage-y += spi.c -verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-y += uart.c verstage-y += ../tegra/gpio.c verstage-y += ../tegra/i2c.c verstage-y += ../tegra/pinmux.c @@ -46,7 +44,7 @@ romstage-$(CONFIG_SOFTWARE_I2C) += ../tegra/software_i2c.c romstage-y += ../tegra/pinmux.c romstage-y += cache.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += uart.c ramstage-y += cbmem.c ramstage-y += clock.c @@ -65,7 +63,7 @@ ramstage-$(CONFIG_SOFTWARE_I2C) += ../tegra/software_i2c.c ramstage-y += ../tegra/pinmux.c ramstage-y += ../tegra/usb.c -ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += uart.c rmodules_$(ARCH-romstage-y)-y += monotonic_timer.c diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index a2b50c9..e213751 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -18,16 +18,14 @@ bootblock-y += ../tegra/pinmux.c bootblock-y += ../tegra/apbmisc.c bootblock-y += ../tegra/usb.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += uart.c -endif +bootblock-y += uart.c verstage-y += dma.c verstage-y += monotonic_timer.c verstage-y += spi.c verstage-y += padconfig.c verstage-y += funitcfg.c -verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-y += uart.c verstage-y += ../tegra/gpio.c verstage-y += ../tegra/i2c.c verstage-y += ../tegra/pinmux.c @@ -57,7 +55,7 @@ romstage-y += ../tegra/i2c.c romstage-y += ../tegra/pinmux.c romstage-y += ../tegra/usb.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += uart.c ramstage-y += addressmap.c ramstage-y += cbmem.c @@ -92,7 +90,7 @@ ramstage-y += ../tegra/pinmux.c ramstage-y += ramstage.c ramstage-y += mmu_operations.c -ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += uart.c ramstage-y += ../tegra/usb.c ramstage-$(CONFIG_HAVE_MTC) += mtc.c ramstage-y += stage_entry.S diff --git a/src/soc/qualcomm/ipq40xx/Makefile.inc b/src/soc/qualcomm/ipq40xx/Makefile.inc index d66a3d8..6447acf 100644 --- a/src/soc/qualcomm/ipq40xx/Makefile.inc +++ b/src/soc/qualcomm/ipq40xx/Makefile.inc @@ -20,7 +20,7 @@ bootblock-y += gpio.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += timer.c -bootblock-$(CONFIG_DRIVERS_UART) += uart.c +bootblock-y += uart.c verstage-y += clock.c verstage-y += gpio.c @@ -29,14 +29,14 @@ verstage-y += qup.c verstage-y += spi.c verstage-y += timer.c -verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-y += uart.c romstage-y += clock.c romstage-y += blobs_init.c romstage-y += gpio.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += timer.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += uart.c romstage-y += cbmem.c romstage-y += i2c.c romstage-y += blsp.c diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index fcca4ec..491332b7 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -107,7 +107,6 @@ return MSM_BOOT_UART_DM_E_SUCCESS; } -#if IS_ENABLED(CONFIG_DRIVERS_UART) static unsigned int msm_boot_uart_dm_init(void *uart_dm_base); /* Received data is valid or not */ @@ -116,7 +115,6 @@ /* Received data */ static unsigned int word = 0; - void uart_tx_byte(int idx, unsigned char data) { int num_of_chars = 1; @@ -135,7 +133,6 @@ /* And now write the character(s) */ write32(MSM_BOOT_UART_DM_TF(base, 0), data); } -#endif /* CONFIG_SERIAL_UART */ /** * @brief msm_boot_uart_dm_reset - resets UART controller @@ -270,7 +267,6 @@ ; } -#if IS_ENABLED(CONFIG_DRIVERS_UART) /** * ipq40xx_serial_getc - reads a character * @@ -286,7 +282,6 @@ return byte; } -#endif #ifndef __PRE_RAM__ /* TODO: Implement function */ diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index b14db03..8a428b2 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -19,7 +19,7 @@ bootblock-y += gpio.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += timer.c -bootblock-$(CONFIG_DRIVERS_UART) += uart.c +bootblock-y += uart.c verstage-y += clock.c verstage-y += gpio.c @@ -28,14 +28,14 @@ verstage-y += qup.c verstage-y += spi.c verstage-y += timer.c -verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-y += uart.c romstage-y += clock.c romstage-y += blobs_init.c romstage-y += gpio.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += timer.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += uart.c romstage-y += cbmem.c romstage-y += i2c.c romstage-y += gsbi.c diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 3af7958..3805c87 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -109,7 +109,6 @@ return MSM_BOOT_UART_DM_E_SUCCESS; } -#if IS_ENABLED(CONFIG_DRIVERS_UART) static unsigned int msm_boot_uart_dm_init(void *uart_dm_base); /* Received data is valid or not */ @@ -212,7 +211,6 @@ /* And now write the character(s) */ write32(MSM_BOOT_UART_DM_TF(base, 0), tx_data); } -#endif /* CONFIG_SERIAL_UART */ /* * msm_boot_uart_dm_reset - resets UART controller @@ -380,7 +378,6 @@ } #endif -#if IS_ENABLED(CONFIG_DRIVERS_UART) /** * ipq806x_serial_getc - reads a character * @@ -401,7 +398,6 @@ return byte; } -#endif #ifndef __PRE_RAM__ /* TODO: Implement fuction */ diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index e603177..507d913 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -7,7 +7,7 @@ bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += gpio.c -bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +bootblock-y += uart_bitbang.c ################################################################################ verstage-y += spi.c diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 100c00e..7e4c5b4 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -19,9 +19,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/cbmem.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c -endif +bootblock-y += ../common/uart.c bootblock-y += timer.c bootblock-y += clock.c bootblock-y += ../common/spi.c @@ -33,7 +31,7 @@ verstage-y += ../common/spi.c verstage-y += timer.c -verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +verstage-y += ../common/uart.c verstage-y += ../common/gpio.c verstage-y += gpio.c verstage-y += clock.c @@ -43,7 +41,7 @@ romstage-y += ../common/cbmem.c romstage-y += timer.c -romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +romstage-y += ../common/uart.c romstage-y += ../common/i2c.c romstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c romstage-y += clock.c @@ -72,7 +70,7 @@ ramstage-y += ../common/edp.c ramstage-y += hdmi.c ramstage-y += display.c -ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +ramstage-y += ../common/uart.c CPPFLAGS_common += -Isrc/soc/rockchip/rk3288/include CPPFLAGS_common += -Isrc/soc/rockchip/common/include diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 83936e8..854eb84 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -22,9 +22,7 @@ bootblock-y += ../common/i2c.c bootblock-y += ../common/spi.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c -endif +bootblock-y += ../common/uart.c bootblock-y += ../common/gpio.c bootblock-y += ../common/pwm.c bootblock-y += bootblock.c @@ -39,7 +37,7 @@ verstage-y += sdram.c verstage-y += ../common/i2c.c verstage-y += ../common/spi.c -verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +verstage-y += ../common/uart.c verstage-y += clock.c verstage-y += timer.c @@ -48,7 +46,7 @@ romstage-y += ../common/cbmem.c romstage-y += sdram.c romstage-y += ../common/spi.c -romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +romstage-y += ../common/uart.c romstage-y += clock.c romstage-y += ../common/pwm.c romstage-y += timer.c @@ -64,7 +62,7 @@ ramstage-y += ../common/cbmem.c ramstage-y += sdram.c ramstage-y += ../common/spi.c -ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +ramstage-y += ../common/uart.c ramstage-y += clock.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/edp.c diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc index 2731f17..a6eb9ee 100644 --- a/src/soc/samsung/exynos5250/Makefile.inc +++ b/src/soc/samsung/exynos5250/Makefile.inc @@ -4,11 +4,9 @@ bootblock-y += bootblock.c bootblock-y += pinmux.c timer.c power.c # Clock is required for UART -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c -ifeq ($(CONFIG_DRIVERS_UART),y) -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c -endif +bootblock-y += clock_init.c +bootblock-y += clock.c +bootblock-y += uart.c bootblock-y += wakeup.c bootblock-y += gpio.c @@ -20,7 +18,7 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += timer.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += uart.c romstage-y += wakeup.c romstage-y += gpio.c romstage-y += trustzone.c @@ -33,7 +31,7 @@ ramstage-y += clock_init.c ramstage-y += pinmux.c ramstage-y += power.c -ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += uart.c ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += timer.c diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc index 498e8d1..b41e9f9 100644 --- a/src/soc/samsung/exynos5420/Makefile.inc +++ b/src/soc/samsung/exynos5420/Makefile.inc @@ -4,11 +4,9 @@ bootblock-y += bootblock.c bootblock-y += pinmux.c timer.c power.c # Clock is required for UART -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c -ifeq ($(CONFIG_DRIVERS_UART),y) -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c -endif +bootblock-y += clock_init.c +bootblock-y += clock.c +bootblock-y += uart.c bootblock-y += wakeup.c bootblock-y += gpio.c @@ -21,7 +19,7 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += timer.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += uart.c romstage-y += wakeup.c romstage-y += gpio.c romstage-y += i2c.c @@ -34,7 +32,7 @@ ramstage-y += clock_init.c ramstage-y += pinmux.c ramstage-y += power.c -ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += uart.c ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += timer.c -- To view, visit https://review.coreboot.org/c/coreboot/+/29572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Gerrit-Change-Number: 29572 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: grunt: Default SPK_PA_EN to LOW
by Raul Rangel (Code Review) 21 Nov '18

21 Nov '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29783 Change subject: grunt: Default SPK_PA_EN to LOW ...................................................................... grunt: Default SPK_PA_EN to LOW We need to default this to low so the speakers don't activate in S3. BUG=b:118248953 TEST=Used a scope to look at the line and made sure depthcharge still beeps. Change-Id: I70d2f4a3261d212b62e784fa7414e45b1d575612 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/29783/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 95064bc..2d48efe 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -207,7 +207,7 @@ PAD_NF(GPIO_118, SPI_CS1_L, PULL_NONE), /* GPIO_119 - SPK_PA_EN */ - PAD_GPO(GPIO_119, HIGH), + PAD_GPO(GPIO_119, LOW), /* GPIO_126 - DMIC_CLK2_EN */ PAD_GPO(GPIO_126, HIGH), -- To view, visit https://review.coreboot.org/c/coreboot/+/29783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70d2f4a3261d212b62e784fa7414e45b1d575612 Gerrit-Change-Number: 29783 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2018