coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

1 participants
1699 discussions

Change in ...coreboot[master]: mb/google/dragonegg: Add initial mainboard code support
by Patrick Rudolph (Code Review) 22 Nov '18

22 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29749 ) Change subject: mb/google/dragonegg: Add initial mainboard code support ...................................................................... Patch Set 9: > Patch Set 9: > > > Patch Set 9: > > > > > > > Please add Documentation for that board. > > > > > For example: > > > > > How to flash, required BLOBs, pictures if possible, everything > > > > that > > > > > is useful for coreboot development. > > > > > > > > I will let Shelley to answer this question. As this is early ICL > > > > silicon, i'm not sure about board availability to able to build > > > at > > > > externally. > > > > > > That would be wonderful to have it in the Documentation :-). > > > > Patrick, do you have any sample documentation that can be referred here > > Patrick, > > Flashing is the same as other Intel boards: > > $ dut-control spi2_vref:pp3300 spi2_buf_en:on spi2_buf_on_flex_en:on warm_reset:on > $ sudo flashrom -n -p ft2232_spi:type=servo-v2 -w <bios_image> > $ dut-control spi2_vref:off spi2_buf_en:off spi2_buf_on_flex_en:off warm_reset:off > > Sorry, I do not have the pointers to the blobs as they are in the Intel VIP site and I can't post photos of the board as it is a early development board. How to write documentation can be found here: https://doc.coreboot.org/getting_started/writing_documentation.html Sample documentation can be found in git, here: Documentation/mainboard/*/*.md All those facts mentioned should go into the documentation. Also: Will it be available for purchase ? Will it be available as reference platform for OEMs ? Is it an internal project only ? If the blobs aren't available, the code wont work at all, that should be mentioned in the Documentation and fixed once the BLOBs are available. Are there schematics or other documents you can reference ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Gerrit-Change-Number: 29749 Gerrit-PatchSet: 9 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Nov 2018 08:01:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI
by Jenny Tc (Code Review) 22 Nov '18

22 Nov '18

Jenny Tc has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29775 ) Change subject: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29775/1/src/ec/google/chromeec/smihandler.c File src/ec/google/chromeec/smihandler.c: https://review.coreboot.org/#/c/29775/1/src/ec/google/chromeec/smihandler.c… PS1, Line 102: #if IS_ENABLED(CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI) > You will still have to populate 0 to SMI PORT in FADT to ensure OS doesn't expose that port. […] If CONFIG_REDUCED_SMI is enabled, https://review.coreboot.org/#/c/coreboot/+/28696/2/src/soc/intel/skylake/ac… will do populating the FADT right? -- To view, visit https://review.coreboot.org/c/coreboot/+/29775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ca93972fa4d870632707cb9a9e74ab80cbd5d5 Gerrit-Change-Number: 29775 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 22 Nov 2018 07:05:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Comment-In-Reply-To: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI
by Dhaval Sharma (Code Review) 22 Nov '18

22 Nov '18

Dhaval Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29775 ) Change subject: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29775/1/src/ec/google/chromeec/smihandler.c File src/ec/google/chromeec/smihandler.c: https://review.coreboot.org/#/c/29775/1/src/ec/google/chromeec/smihandler.c… PS1, Line 102: #if IS_ENABLED(CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI) > Okay.. […] You will still have to populate 0 to SMI PORT in FADT to ensure OS doesn't expose that port. wrt naming I think what you have should work (one config per feature). That way one can easily select/de-select specific SMI feature. But may be we should use a naming convention like NO_SMI or something like that so that we know that the implementation belongs to same family/purpose which is to reduce SMI usage on platform. -- To view, visit https://review.coreboot.org/c/coreboot/+/29775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ca93972fa4d870632707cb9a9e74ab80cbd5d5 Gerrit-Change-Number: 29775 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 22 Nov 2018 06:59:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Comment-In-Reply-To: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src/soc/intel/braswellsouthcluster.c: Replace fixed values by defines
by Frans Hendriks (Code Review) 22 Nov '18

22 Nov '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29788 Change subject: src/soc/intel/braswellsouthcluster.c: Replace fixed values by defines ...................................................................... src/soc/intel/braswellsouthcluster.c: Replace fixed values by defines The GPIO and ACPI base sizes have defines, but they are not used. Use GPIO_BASE_SIZE and ACPI_BASE_SIZE. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I348eda57ab9dc0bd45f8dc9ab0e7c47c462102fe Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/southcluster.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/29788/1 diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index ae4b8c5..0c88004 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -126,10 +126,10 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* GPIO */ - sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE); + sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE); /* ACPI */ - sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); + sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); } static void sc_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/29788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I348eda57ab9dc0bd45f8dc9ab0e7c47c462102fe Gerrit-Change-Number: 29788 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/intel/icelake_rvp: Add ICL U and Y RVP DIMM configuration
by Shelley Chen (Code Review) 22 Nov '18

22 Nov '18

Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29770 ) Change subject: mb/intel/icelake_rvp: Add ICL U and Y RVP DIMM configuration ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7 Gerrit-Change-Number: 29770 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Nov 2018 06:12:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/google/dragonegg: Add initial mainboard code support
by Shelley Chen (Code Review) 22 Nov '18

22 Nov '18

Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29749 ) Change subject: mb/google/dragonegg: Add initial mainboard code support ...................................................................... Patch Set 9: > Patch Set 9: > > > > > Please add Documentation for that board. > > > > For example: > > > > How to flash, required BLOBs, pictures if possible, everything > > > that > > > > is useful for coreboot development. > > > > > > I will let Shelley to answer this question. As this is early ICL > > > silicon, i'm not sure about board availability to able to build > > at > > > externally. > > > > That would be wonderful to have it in the Documentation :-). > > Patrick, do you have any sample documentation that can be referred here Patrick, Flashing is the same as other Intel boards: $ dut-control spi2_vref:pp3300 spi2_buf_en:on spi2_buf_on_flex_en:on warm_reset:on $ sudo flashrom -n -p ft2232_spi:type=servo-v2 -w <bios_image> $ dut-control spi2_vref:off spi2_buf_en:off spi2_buf_on_flex_en:off warm_reset:off Sorry, I do not have the pointers to the blobs as they are in the Intel VIP site and I can't post photos of the board as it is a early development board. -- To view, visit https://review.coreboot.org/c/coreboot/+/29749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Gerrit-Change-Number: 29749 Gerrit-PatchSet: 9 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Nov 2018 05:36:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratio
by Werner Zeh (Code Review) 22 Nov '18

22 Nov '18

Hello Mario Scheithauer, Huang Jin, build bot (Jenkins), Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29772 to look at the new patch set (#5). Change subject: soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratio ...................................................................... soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratio Add a Kconfig switch to be able to set the CPU clock to the lowest possible ratio. If enabled the CPU will consume as little power as possible while providing the lowest performance. This setting can be overruled by the OS if it has an p-state driver which can adjust the clock to it's need. Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/cpu.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29772/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/29772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073 Gerrit-Change-Number: 29772 Gerrit-PatchSet: 5 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: intelblocks/cpu: Add function to set CPU clock to minimum value
by Werner Zeh (Code Review) 22 Nov '18

22 Nov '18

Hello Mario Scheithauer, Huang Jin, build bot (Jenkins), Nico Huber, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29771 to look at the new patch set (#4). Change subject: intelblocks/cpu: Add function to set CPU clock to minimum value ...................................................................... intelblocks/cpu: Add function to set CPU clock to minimum value Provide a library function to set the CPU frequency to minimum value. This will result in the lowest possible CPU clock with the lowest possible power consumption. This can be useful in mobile devices where the power dissipation is limited. This setting can be overruled by the OS if it has an p-state driver which can adjust the clock to it's need. Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/29771/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Gerrit-Change-Number: 29771 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: intelblocks/cpu: Add function to set CPU clock to minimum value
by Werner Zeh (Code Review) 22 Nov '18

22 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29771 ) Change subject: intelblocks/cpu: Add function to set CPU clock to minimum value ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/29771/3/src/soc/intel/common/block/cpu/cpul… File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/#/c/29771/3/src/soc/intel/common/block/cpu/cpul… PS3, Line 144: * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with the value > nit: bit 15:8 If I have a look at the APL EDS Vol. 2, it tells me that bit 15 is reserved. -- To view, visit https://review.coreboot.org/c/coreboot/+/29771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Gerrit-Change-Number: 29771 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Nov 2018 05:20:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Huang Jin <huang.jin(a)intel.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/google/dragonegg: Add initial mainboard code support
by Subrata Banik (Code Review) 22 Nov '18

22 Nov '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29749 ) Change subject: mb/google/dragonegg: Add initial mainboard code support ...................................................................... Patch Set 9: > > > Please add Documentation for that board. > > > For example: > > > How to flash, required BLOBs, pictures if possible, everything > > that > > > is useful for coreboot development. > > > > I will let Shelley to answer this question. As this is early ICL > > silicon, i'm not sure about board availability to able to build > at > > externally. > > That would be wonderful to have it in the Documentation :-). Patrick, do you have any sample documentation that can be referred here -- To view, visit https://review.coreboot.org/c/coreboot/+/29749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Gerrit-Change-Number: 29749 Gerrit-PatchSet: 9 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Nov 2018 04:58:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2018