coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Disable SD controller and update GPIO
by David Wu (Code Review) 23 Nov '18

23 Nov '18

Hello Zhuohao Lee, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29765 to look at the new patch set (#4). Change subject: mb/google/fizz/variants/karma: Disable SD controller and update GPIO ...................................................................... mb/google/fizz/variants/karma: Disable SD controller and update GPIO The SD cardreader is on USB bus, not on SDIO/SDXC. BUG=b:119798840 BRANCH=master TEST=Compiles successfully and boot on DUT. Change-Id: I8015fe35a4ff79469b5781942f588c3e1b88b751 Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/fizz/overridetree.cb M src/mainboard/google/fizz/variants/karma/gpio.c M src/mainboard/google/fizz/variants/karma/overridetree.cb 4 files changed, 43 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/29765/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8015fe35a4ff79469b5781942f588c3e1b88b751 Gerrit-Change-Number: 29765 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Documentation: Fix referencing warnings
by Felix Singer (Code Review) 23 Nov '18

23 Nov '18

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29803 Change subject: Documentation: Fix referencing warnings ...................................................................... Documentation: Fix referencing warnings This commit fixes several "'any' reference target not found" warnings and the resulting links that are created. Change-Id: I617eddc99a681d721b7652c37ee28e233b7e01a6 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M Documentation/mainboard/lenovo/t420.md M Documentation/mainboard/lenovo/t430.md M Documentation/mainboard/lenovo/w530.md M Documentation/releases/coreboot-4.9-relnotes.md 4 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/29803/1 diff --git a/Documentation/mainboard/lenovo/t420.md b/Documentation/mainboard/lenovo/t420.md index ff7a0a9..edd1fef 100644 --- a/Documentation/mainboard/lenovo/t420.md +++ b/Documentation/mainboard/lenovo/t420.md @@ -12,5 +12,5 @@ Steps to access the flash IC are described here [T4xx series]. -[T4xx series]: t4xx_series.md -[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md +[T4xx series]:t4xx_series +[T420 / T520 / X220 / T420s / W520 common]:xx20_series diff --git a/Documentation/mainboard/lenovo/t430.md b/Documentation/mainboard/lenovo/t430.md index 787246f..43a1d51 100644 --- a/Documentation/mainboard/lenovo/t430.md +++ b/Documentation/mainboard/lenovo/t430.md @@ -11,5 +11,5 @@ Steps to access the flash IC are described here [T4xx series]. -[T4xx series]: t4xx_series.md -[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md +[T4xx series]:t4xx_series +[T430 / T530 / X230 / T430s / W530 common]:xx30_series diff --git a/Documentation/mainboard/lenovo/w530.md b/Documentation/mainboard/lenovo/w530.md index f91d9ce..889c701 100644 --- a/Documentation/mainboard/lenovo/w530.md +++ b/Documentation/mainboard/lenovo/w530.md @@ -24,4 +24,4 @@ [w530-2]: w530-2.jpg -[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md +[T430 / T530 / X230 / T430s / W530 common]:xx30_series diff --git a/Documentation/releases/coreboot-4.9-relnotes.md b/Documentation/releases/coreboot-4.9-relnotes.md index c59744e..7ceaac0 100644 --- a/Documentation/releases/coreboot-4.9-relnotes.md +++ b/Documentation/releases/coreboot-4.9-relnotes.md @@ -6,7 +6,7 @@ Update this document with changes that should be in the release notes. * Please use Markdown. -* See the [4.7](coreboot-4.7-relnotes.md) and [4.8](coreboot-4.8.1-relnotes.md) +* See the [4.7](coreboot-4.7-relnotes) and [4.8](coreboot-4.8.1-relnotes) release notes for the general format. * The chip and board additions and removals will be updated right before the release, so those do not need to be added. -- To view, visit https://review.coreboot.org/c/coreboot/+/29803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I617eddc99a681d721b7652c37ee28e233b7e01a6 Gerrit-Change-Number: 29803 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/x86/Kconfig.debug: Remove weird dependencies and comments
by Nico Huber (Code Review) 22 Nov '18

22 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29802 Change subject: cpu/x86/Kconfig.debug: Remove weird dependencies and comments ...................................................................... cpu/x86/Kconfig.debug: Remove weird dependencies and comments No need to hide prompts, it's a user choice anyway, they should know. The help texts were just rephrasing the prompts or stating the obvious. Change-Id: I5694a88f2da57af2a20357c4e22c7c648053cc26 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/x86/Kconfig.debug 1 file changed, 1 insertion(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/29802/1 diff --git a/src/cpu/x86/Kconfig.debug b/src/cpu/x86/Kconfig.debug index c5e21ef..1c615f9 100644 --- a/src/cpu/x86/Kconfig.debug +++ b/src/cpu/x86/Kconfig.debug @@ -2,14 +2,8 @@ bool config DEBUG_CAR - bool + bool "Output verbose Cache-as-RAM debug messages" depends on HAVE_DEBUG_CAR - # Only visible if debug level is DEBUG (7) or SPEW (8) as it does - # additional printk(BIOS_DEBUG, ...) calls. - prompt "Output verbose Cache-as-RAM debug messages" \ - if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 - help - This option enables additional CAR related debug messages. config HAVE_DISPLAY_MTRRS bool @@ -21,10 +15,3 @@ config DEBUG_SMM_RELOCATION bool "Debug SMM relocation code" depends on HAVE_SMI_HANDLER - help - This option enables additional SMM handler relocation related - debug messages. - - Note: This option will increase the size of the coreboot image. - - If unsure, say N. -- To view, visit https://review.coreboot.org/c/coreboot/+/29802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5694a88f2da57af2a20357c4e22c7c648053cc26 Gerrit-Change-Number: 29802 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common: Bring DISPLAY_MTRRS into the light
by Nico Huber (Code Review) 22 Nov '18

22 Nov '18

Hello build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29684 to look at the new patch set (#4). Change subject: soc/intel/common: Bring DISPLAY_MTRRS into the light ...................................................................... soc/intel/common: Bring DISPLAY_MTRRS into the light Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the "Debug" menu. It turned out, though, that the code looks rather generic and while it's not perfect, I see nothing to be ashamed of. No need to hide it in soc/intel/. To not bloat src/Kconfig up any further, start a new `Kconfig.debug` hierarchy just for debug options. If somebody wants to review the code if it's 100% generic, we could even get rid of HAVE_DISPLAY_MTRRS. Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Documentation/Intel/Board/Galileo_checklist.html M Documentation/Intel/SoC/soc.html M src/Kconfig M src/arch/x86/postcar.c A src/cpu/x86/Kconfig.debug M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/debug.c M src/cpu/x86/mtrr/earlymtrr.c M src/drivers/intel/fsp1_1/after_raminit.S M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/include/fsp/ramstage.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/stack.c M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/notify.c M src/include/cpu/x86/mtrr.h M src/soc/intel/common/Kconfig M src/soc/intel/common/Makefile.inc D src/soc/intel/common/util.c D src/soc/intel/common/util.h M src/soc/intel/quark/Makefile.inc M src/soc/intel/quark/bootblock/bootblock.c M src/soc/intel/quark/include/soc/ramstage.h M src/soc/intel/quark/romstage/mtrr.c M src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat M src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat M src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat M src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat 28 files changed, 251 insertions(+), 313 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29684/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Gerrit-Change-Number: 29684 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86: drop special case cbfs locator
by Patrick Georgi (Code Review) 22 Nov '18

22 Nov '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29801 Change subject: arch/x86: drop special case cbfs locator ...................................................................... arch/x86: drop special case cbfs locator CBFS used to have a special region for the x86 bootblock, which also contained a pointer to a CBFS master header, which describes the layout of the CBFS. Since we adopted other architectures, we got rid of the bootblock region as a separate entity and add the x86 bootblock as a CBFS file now. The master header still exists for compatibility with old cbfstool versions, but it's neatly wrapped in either the bootblock file or in a file carefully crafted at the right location (on all other architectures). All the layout information we need is now available from FMAP, a core part of a contemporary coreboot image, even on x86, so we can just use the generic master header locator in src/lib/cbfs.c and get rid of the special version. Among the advantages: the x86 header locator reduced the size of the CBFS by 64 bytes assuming that there's the bootblock region of at least that size - this breaks assumptions elsewhere (eg. when walking CBFS in cbfs_boot_locate() because the last file, the bootblock, will exceed the CBFS region as seen by coreboot (since it's CBFS - 64bytes). TEST=emulation/qemu-q35 still boots Change-Id: I6fa78073ee4015d7769ed588dc67f9b019d42d07 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reported-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/mmap_boot.c 1 file changed, 0 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/29801/1 diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index 168b17d..2432201 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -28,44 +28,3 @@ { return &boot_dev.rdev; } - -static int cbfs_master_header_props(struct cbfs_props *props) -{ - struct cbfs_header header; - int32_t offset; - const struct region_device *bdev; - - bdev = boot_device_ro(); - - rdev_readat(bdev, &offset, CONFIG_ROM_SIZE - sizeof(offset), - sizeof(offset)); - - /* The offset is relative to the end of the media. */ - offset += CONFIG_ROM_SIZE; - - rdev_readat(bdev, &header, offset, sizeof(header)); - - header.magic = ntohl(header.magic); - header.romsize = ntohl(header.romsize); - header.bootblocksize = ntohl(header.bootblocksize); - header.offset = ntohl(header.offset); - - if (header.magic != CBFS_HEADER_MAGIC) - return -1; - - props->offset = header.offset; - if (header.romsize != CONFIG_ROM_SIZE) - props->size = CONFIG_ROM_SIZE; - else - props->size = header.romsize; - props->size -= props->offset; - props->size -= header.bootblocksize; - props->size = ALIGN_DOWN(props->size, 64); - - return 0; -} - -const struct cbfs_locator cbfs_master_header_locator = { - .name = "Master Header Locator", - .locate = cbfs_master_header_props, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/29801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fa78073ee4015d7769ed588dc67f9b019d42d07 Gerrit-Change-Number: 29801 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/arch/x86/acpi.c: Create log area and extend TPM2 table
by Philipp Deppenwiese (Code Review) 22 Nov '18

22 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29800 ) Change subject: src/arch/x86/acpi.c: Create log area and extend TPM2 table ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3 Gerrit-Change-Number: 29800 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Nov 2018 16:09:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/arch/x86/acpi.c: Create log area and extend TPM2 table
by Michał Żygowski (Code Review) 22 Nov '18

22 Nov '18

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29800 Change subject: src/arch/x86/acpi.c: Create log area and extend TPM2 table ...................................................................... src/arch/x86/acpi.c: Create log area and extend TPM2 table According to newest TCG ACPI Specification for Family 1.2 and 2.0 Version 1.2, Revision 8, TPM2 ACPI table has two more fields LAML and LASA. Update the table structure definition, create the log area for TPM2 in coreboot tables and fill the missing fields in TPM2 table. TPM2 should be now probed well in SeaBIOS rel-1.12.0 or master. Tested on apu2 with Infineon SLB9665 TT2.0. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3 --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h M src/commonlib/include/commonlib/cbmem_id.h 3 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/29800/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index f54aa19..5c41d68 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -308,12 +308,43 @@ header->checksum = acpi_checksum((void *)tcpa, header->length); } +static void *get_tpm2_log(u32 *size) +{ + const struct cbmem_entry *ce; + const u32 tpm2_default_log_len = 0x10000; + void *lasa; + ce = cbmem_entry_find(CBMEM_ID_TPM2_TCG_LOG); + if (ce) { + lasa = cbmem_entry_start(ce); + *size = cbmem_entry_size(ce); + printk(BIOS_DEBUG, "TPM2 log found at %p\n", lasa); + return lasa; + } + lasa = cbmem_add(CBMEM_ID_TPM2_TCG_LOG, tpm2_default_log_len); + if (!lasa) { + printk(BIOS_ERR, "TPM2 log creation failed\n"); + return NULL; + } + + printk(BIOS_DEBUG, "TPM2 log created at %p\n", lasa); + memset(lasa, 0, tpm2_default_log_len); + + *size = tpm2_default_log_len; + return lasa; +} + static void acpi_create_tpm2(acpi_tpm2_t *tpm2) { acpi_header_t *header = &(tpm2->header); + u32 tpm2_log_len; + void *lasa; memset((void *)tpm2, 0, sizeof(acpi_tpm2_t)); + lasa = get_tpm2_log(&tpm2_log_len); + if (!lasa) + return; + /* Fill out header fields. */ memcpy(header->signature, "TPM2", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -330,6 +361,13 @@ /* coreboot only supports the TIS interface driver. */ tpm2->start_method = 6; memset(tpm2->msp, 0, sizeof(tpm2->msp)); + /* + * Log area fields are optional, but otherwise the table length will be + * to small and SeaBIOS will complain. Initialize the TPM2 log table + * and fill the fields. + */ + tpm2->laml = tpm2_log_len; + tpm2->lasa = (uintptr_t) lasa; /* Calculate checksum. */ header->checksum = acpi_checksum((void *)tpm2, header->length); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index b5205c0..050f0a4 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -198,6 +198,8 @@ u64 control_area; u32 start_method; u8 msp[12]; + u32 laml; + u64 lasa; } __packed acpi_tpm2_t; typedef struct acpi_mcfg_mmconfig { diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 042ea6e..2e0eeb6 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -65,6 +65,7 @@ #define CBMEM_ID_TCPA_LOG 0x54435041 #define CBMEM_ID_TCPA_TCG_LOG 0x54445041 #define CBMEM_ID_TIMESTAMP 0x54494d45 +#define CBMEM_ID_TPM2_TCG_LOG 0x54504d32 #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 @@ -121,6 +122,7 @@ { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \ { CBMEM_ID_TCPA_TCG_LOG, "TCPA TCGLOG" }, \ { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \ + { CBMEM_ID_TPM2_TCG_LOG, "TPM2 TCGLOG" }, \ { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \ { CBMEM_ID_VBOOT_SEL_REG, "VBOOT SEL " }, \ { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/29800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3 Gerrit-Change-Number: 29800 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN read
by Mario Scheithauer (Code Review) 22 Nov '18

22 Nov '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29799 Change subject: siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN read ...................................................................... siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN read An additional reading of PTN configuration data at the end of the ptn3460_init function is not necessary. Change-Id: I5f7f647242e94b1af13757d00e80ed9813d435d0 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c 2 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/29799/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c index e95b752..060a35c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c @@ -109,12 +109,6 @@ return (PTN_BUS_ERROR | status); } - /* Read PTN configuration data. */ - status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF, (uint8_t *)&cfg, sizeof(cfg)); - if (status) - return (PTN_BUS_ERROR | status); - return PTN_NO_ERROR; } diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c index 829af2a..01da624 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -110,12 +110,6 @@ return (PTN_BUS_ERROR | status); } - /* Read PTN configuration data. */ - status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, - PTN_CONFIG_OFF, (uint8_t *)&cfg, sizeof(cfg)); - if (status) - return (PTN_BUS_ERROR | status); - return PTN_NO_ERROR; } -- To view, visit https://review.coreboot.org/c/coreboot/+/29799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f7f647242e94b1af13757d00e80ed9813d435d0 Gerrit-Change-Number: 29799 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S
by Patrick Georgi (Code Review) 22 Nov '18

22 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29687 ) Change subject: drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S ...................................................................... drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S soc/car_setup.S is included when SKIP_FSP_CAR is enabled, but no chipset/SoC have car_setup.S available. Remove include and post_code() call always solving build errors. BUG=NA TEST=NA Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/29687 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Huang Jin <huang.jin(a)intel.com> --- M src/drivers/intel/fsp1_1/cache_as_ram.inc 1 file changed, 0 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Huang Jin: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index af6f3a9..934ae67 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -37,19 +37,6 @@ cache_as_ram: post_code(0x20) -#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) - - /* - * SOC specific setup - * NOTE: This has to preserve the registers - * mm0, mm1 and edi. - */ - #include <soc/car_setup.S> - - post_code(0x28) - -#endif - /* * Find the FSP binary in cbfs. * Make a fake stack that has the return value back to this code. -- To view, visit https://review.coreboot.org/c/coreboot/+/29687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61 Gerrit-Change-Number: 29687 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S
by Frans Hendriks (Code Review) 22 Nov '18

22 Nov '18

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29687 ) Change subject: drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S ...................................................................... Patch Set 1: > Patch Set 1: > > remove in src/drivers/intel/fsp1_1/after_raminit.S as well? No. In this file the function chipset_teardown_car() is called. This function is available, so might cause malfunction. -- To view, visit https://review.coreboot.org/c/coreboot/+/29687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61 Gerrit-Change-Number: 29687 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Thu, 22 Nov 2018 15:00:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2018