coreboot-gerrit November 2018

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Change in ...coreboot[master]: siemens/mc_apl5: Adjust the settings for the PCIe root ports
by Mario Scheithauer (Code Review) 23 Nov '18

23 Nov '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29810 Change subject: siemens/mc_apl5: Adjust the settings for the PCIe root ports ...................................................................... siemens/mc_apl5: Adjust the settings for the PCIe root ports This mainboard has four connected PCIe devices. The required root ports are switched on and configured. Change-Id: I82b13e1d245a172762ebd689ae136a762027033f Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/29810/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index f3e8a77..7dbeea1 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -7,12 +7,12 @@ register "sci_irq" = "SCIS_IRQ10" # Disable unused clkreq of PCIe root ports - register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge - register "pcie_rp_clkreq_pin[1]" = "2" # FPGA - register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY - register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY - register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" - register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[0]" = "1" # 14.0 + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" # 14.1 + register "pcie_rp_clkreq_pin[2]" = "0" # 13.0 + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" # 13.1 + register "pcie_rp_clkreq_pin[4]" = "2" # 13.2 + register "pcie_rp_clkreq_pin[5]" = "3" # 13.3 # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3. @@ -71,12 +71,12 @@ device pci 0e.0 off end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA - device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY - device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY - device pci 13.2 off end # - RP 4 - PCIe-A 2 - device pci 13.3 off end # - RP 5 - PCIe-A 3 - device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge - device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA + device pci 13.0 on end # - RP 2 - PCIe A 0 + device pci 13.1 off end # - RP 3 - PCIe A 1 + device pci 13.2 on end # - RP 4 - PCIe-A 2 + device pci 13.3 on end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 + device pci 14.1 off end # - RP 1 - PCIe-B 1 device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on # - I2C 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/29810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82b13e1d245a172762ebd689ae136a762027033f Gerrit-Change-Number: 29810 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Kconfig: Unify power-after-failure options
by Nico Huber (Code Review) 23 Nov '18

23 Nov '18

Hello HAOUAS Elyes, Subrata Banik, Tristan Corrick, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29680 to look at the new patch set (#4). Change subject: Kconfig: Unify power-after-failure options ...................................................................... Kconfig: Unify power-after-failure options The newest and most useful incarnation was hiding in soc/intel/common/. We move it into the Mainboard menu and extend it with various flags to be selected to control the default and which options are visible. Also add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the boolean to int conversion into Kconfig: 0 - S5 1 - S0 2 - previous state This patch focuses on the Kconfig code. The C code could be unified as well, e.g. starting with a common enum and safe wrapper around the get_option() call. TEST=Did what-jenkins-does with and without this commit and compared binaries. Nothing changed for the default configurations. Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/Kconfig M src/mainboard/asrock/h81m-hds/Kconfig M src/mainboard/asus/kcma-d8/Kconfig M src/mainboard/asus/kfsn4-dre/Kconfig M src/mainboard/asus/kgpe-d16/Kconfig M src/mainboard/msi/ms9652_fam10/Kconfig M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/stumpy/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmclib.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/amd8111/Kconfig M src/southbridge/amd/amd8111/acpi.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/sb700/Kconfig M src/southbridge/amd/sb700/sm.c M src/southbridge/amd/sb800/sm.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/fsp_rangeley/soc.h M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/nvidia/ck804/Kconfig M src/southbridge/nvidia/ck804/lpc.c M src/southbridge/nvidia/mcp55/Kconfig M src/southbridge/nvidia/mcp55/lpc.c M src/superio/nuvoton/nct5572d/Kconfig M src/superio/nuvoton/nct5572d/superio.c M src/superio/winbond/w83667hg-a/Kconfig M src/superio/winbond/w83667hg-a/superio.c 55 files changed, 121 insertions(+), 164 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29680/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Gerrit-Change-Number: 29680 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hellsenberg <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/intel/kblrvp: Add new Kaby lake RVP11 support
by PraveenX Hodagatta Pranesh (Code Review) 23 Nov '18

23 Nov '18

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29809 Change subject: mb/intel/kblrvp: Add new Kaby lake RVP11 support ...................................................................... mb/intel/kblrvp: Add new Kaby lake RVP11 support The RVP11 is a dual-channel DDR4 SO-DIMM on skylake H platform. This patch add following chages - Add devicetree.cb for RVP11 in the variants path. - Select cannonlake PCH-H chipset config for RVP11. - Add GPIO table as per board schematics. - Add audio verb table for RVP11. - Set the UserBd UPD to BOARD_TYPE_DESKTOP. BUG=None TEST= Build and flash, confirm boot into yocto OS on KBL RVP11 platform. verified PCI, USB, ethernet, SATA, display, audio and power functionalities. Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> Change-Id: Id86f56df06795601cc9d7830766e54396d218e00 --- M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/Kconfig.name M src/mainboard/intel/kblrvp/ramstage.c M src/mainboard/intel/kblrvp/romstage.c M src/mainboard/intel/kblrvp/smihandler.c A src/mainboard/intel/kblrvp/variants/rvp11/devicetree.cb A src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h A src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h 8 files changed, 806 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/29809/1 diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index bf17c4b..1af4e30 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 || BOARD_INTEL_KBLRVP8 +if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 || BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -8,9 +8,9 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER - select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 + select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_KBLRVP8 select SOC_INTEL_SKYLAKE - select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8 + select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 select MAINBOARD_USES_FSP2_0 select MAINBOARD_HAS_CHROMEOS select GENERIC_SPD_BIN @@ -32,6 +32,7 @@ default "rvp3" if BOARD_INTEL_KBLRVP3 default "rvp7" if BOARD_INTEL_KBLRVP7 default "rvp8" if BOARD_INTEL_KBLRVP8 + default "rvp11" if BOARD_INTEL_KBLRVP11 config MAINBOARD_PART_NUMBER string @@ -64,6 +65,7 @@ default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp3.bin" if BOARD_INTEL_KBLRVP3 default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp7.bin" if BOARD_INTEL_KBLRVP7 default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp8.bin" if BOARD_INTEL_KBLRVP8 + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp11.bin" if BOARD_INTEL_KBLRVP11 config ME_BIN_PATH string @@ -71,6 +73,7 @@ default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp3.bin" if BOARD_INTEL_KBLRVP3 default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp7.bin" if BOARD_INTEL_KBLRVP7 default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp8.bin" if BOARD_INTEL_KBLRVP8 + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp11.bin" if BOARD_INTEL_KBLRVP11 config PRERAM_CBMEM_CONSOLE_SIZE hex @@ -78,5 +81,5 @@ config DIMM_SPD_SIZE int - default 512 if BOARD_INTEL_KBLRVP8 #DDR4 + default 512 if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 #DDR4 endif diff --git a/src/mainboard/intel/kblrvp/Kconfig.name b/src/mainboard/intel/kblrvp/Kconfig.name index b275b17..df65e32 100644 --- a/src/mainboard/intel/kblrvp/Kconfig.name +++ b/src/mainboard/intel/kblrvp/Kconfig.name @@ -4,3 +4,5 @@ bool "Kabylake DDR3L RVP7" config BOARD_INTEL_KBLRVP8 bool "Kabylake DDR4 RVP8" +config BOARD_INTEL_KBLRVP11 + bool "Kabylake DDR4 RVP11" diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index 1e6aa11..453a4da 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2016-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,6 +32,9 @@ static void ioexpander_init(void *unused) { + #if IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP11) + + #else printk(BIOS_DEBUG, "Programming TCA6424A I/O expander\n"); /* I/O Expander 1, Port 0 Data */ @@ -61,6 +64,7 @@ /* Port 0 Configuration */ i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_1_ADDR, IO_EXPANDER_P0CONF, 0x00); + #endif } diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index a29a4af..fe3b59c 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2016-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -59,13 +59,15 @@ mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; - if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) { + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8) || + IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP11)) { mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; } } mupd->FspmTestConfig.DmiVc1 = 1; - if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8) || + IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP11)) mem_cfg->UserBd = BOARD_TYPE_DESKTOP; } diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c index 6006767..1bc2d82 100644 --- a/src/mainboard/intel/kblrvp/smihandler.c +++ b/src/mainboard/intel/kblrvp/smihandler.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2016-2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -52,9 +52,10 @@ if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) return; - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + #if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) if (gpi_status_get(sts, EC_SMI_GPI)) chromeec_smi_process_events(); + #endif } void mainboard_smi_sleep(u8 slp_typ) @@ -67,8 +68,9 @@ int mainboard_smi_apmc(u8 apmc) { - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + #if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + #endif return 0; } diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/devicetree.cb new file mode 100644 index 0000000..eb2ce5d --- /dev/null +++ b/src/mainboard/intel/kblrvp/variants/rvp11/devicetree.cb @@ -0,0 +1,307 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command range is in 0x800-0x8ff + register "gen1_dec" = "0x00fc0801" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "0" + register "Heci3Enabled" = "0" + + register "SaGv" = "3" + register "PmTimerDisabled" = "0" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled + register "SerialIrqConfigSirqEnable" = "0x01" + register "SerialIrqConfigSirqMode" = "0x01" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x1C, \ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x88, \ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C ,\ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C, \ + .voltage_limit = 0x5F0 \ + }" + + # Enable PCIE slot + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1 + # RP6, uses uses CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" + + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2 + # RP7, uses uses CLK SRC 2 + register "PcieRpClkSrcNumber[6]" = "2" + + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 + # RP8, uses uses CLK SRC 3 + register "PcieRpClkSrcNumber[7]" = "3" + + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 + # RP9, uses uses CLK SRC 4 + register "PcieRpClkSrcNumber[8]" = "4" + + register "PcieRpEnable[13]" = "1" + register "PcieRpClkReqSupport[13]" = "1" + register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5 + # RP14, uses uses CLK SRC 5 + register "PcieRpClkSrcNumber[13]" = "5" + + register "PcieRpEnable[16]" = "1" + register "PcieRpClkReqSupport[16]" = "1" + register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7 + # RP17, uses uses CLK SRC 7 + register "PcieRpClkSrcNumber[16]" = "7" + + register EnableLan = "1" + + # USB related + register "SsicPortEnable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel + register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) + register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) + register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor + register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn + register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK + + + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0a" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + register "PmTimerDisabled" = "0" + + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + }" + + # PL2 override 60W + register "tdp_pl2_override" = "60" + + # Power Limit Related + register "PowerLimit4" = "0" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable/Disable VMX feature + register "VmxEnable" = "0" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + #chip drivers/pc80/tpm + # device pnp 0c31.0 on end + #end + #chip ec/google/chromeec + # device pnp 0c09.0 on end + #end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h new file mode 100644 index 0000000..d3224b2 --- /dev/null +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h @@ -0,0 +1,275 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIORVP11_H +#define _GPIORVP11_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ +#define GPE_WLAN_WAKE GPE0_DW0_16 + +/* Input device interrupt configuration */ +#define TOUCHPAD_INT_L GPP_B3_IRQ +#define TOUCHSCREEN_INT_L GPP_E7_IRQ +#define MIC_INT_L GPP_F10_IRQ + +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ +#define EC_SCI_GPI GPE0_DW2_16 + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ + +static const struct pad_config gpio_table[] = { +/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* ESPI ALERT */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF2), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +/* EC_HID_INT */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), +/* ISH_KB_PROX_INT */ PAD_CFG_GPI(GPP_A12, NONE, DEEP), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SLP_S0ix_N */ PAD_CFG_GPO(GPP_A16, 1, DEEP), +/* M.2 WLAN PWR EN */ PAD_CFG_GPO(GPP_A17, 1, DEEP), +/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), +/* GPP_A19 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), +/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), +/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), +/* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP), +/* GPP_A23 */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), + +/* screen lock */ PAD_CFG_GPI(GPP_B0, NONE, DEEP), +/* Tch pnl pwren */ PAD_CFG_GPO(GPP_B1, 1, DEEP), +/* HSJ_MIC_DET */ +/* BT_RF_kill */ PAD_CFG_GPO(GPP_B3, 1, DEEP), +/* SNI_DRV_PCH */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1), +/* M.2 BT UART wake */ PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP), +/* WIFI_CLK_REQ */ +/* KEPLR_CLK_REQ */ +/* SRCCLKREQ3# */ /* GPP_B8 */ +/* SSD_CLK_REQ */ +/* SRCCLKREQ5# */ /* GPP_B10 */ +/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_GPI_ACPI_SMI(GPP_B14, NONE, DEEP, YES), +/* GSPI0_CS# */ /* GPP_B15 */ +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), +/* SSD_PCIE_WAKE */ PAD_CFG_GPO(GPP_B17, 1, DEEP), +/* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 1, DEEP), +/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), +/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), +/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), +/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), +/* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 1, DEEP), + +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPI(GPP_C2, NONE, DEEP), +/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), +/* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* USB_CTL */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* NFC_RST* */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* EN_PP3300_KEPLER */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* PCH_MEM_CFG0 */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), +/* PCH_MEM_CFG1 */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), +/* PCH_MEM_CFG2 */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), +/* PCH_MEM_CFG3 */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* TCH_PNL_PWREN */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* SPI_WP_STATUS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + +/* ITCH_SPI_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), +/* ITCH_SPI_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), +/* ITCH_SPI_MISO_1 */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), +/* ITCH_SPI_MISO_0 */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), +/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), +/* EN_PP3300_DX_EMMC */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +/* EN_PP1800_DX_EMMC */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* TBD */ +/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 1, DEEP), +/* USB_A1_ILIM_SEL */ +/* EN_PP3300_DX_CAM */ +/* EN_PP1800_DX_AUDIO */PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), +/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), +/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* ITCH_SPI_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +/* ITCH_SPI_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + +/* SPI_TPM_IRQ */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF3), +/* SSD_PEDET */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF3), +/* CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), +/* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* SATA_DEVSLP1 */ /* GPP_E5 */ +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF3), +/* TCH_PNL_INTR* */ +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), +/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), +/* I2S2_TXD */ PAD_CFG_GPO(GPP_F2, 0, DEEP), +/* I2S2_RXD */ PAD_CFG_GPO(GPP_F3, 1, DEEP), +/* I2C2_SDA */ PAD_CFG_GPO(GPP_F4, 0, DEEP), +/* I2C2_SCL */ PAD_CFG_GPI_APIC(GPP_F5, NONE, DEEP), +/* I2C3_SDA */ PAD_CFG_GPO(GPP_F6, 0, DEEP), +/* I2C3_SCL */ PAD_CFG_GPO(GPP_F7, 0, DEEP), +/* I2C4_SDA */ PAD_CFG_GPI(GPP_F8, NONE, DEEP), +/* I2C4_SDA */ PAD_CFG_GPI_APIC(GPP_F9, NONE, DEEP), +/* AUDIO_IRQ */ PAD_CFG_GPI(GPP_F10, NONE, DEEP), +/* I2C5_SCL */ PAD_CFG_GPI(GPP_F11, NONE, DEEP), +/* EMMC_CMD */ PAD_CFG_GPI_ACPI_SCI(GPP_F12, NONE, DEEP, YES), +/* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F13, NONE, DEEP), +/* EMMC_DATA1 */ PAD_CFG_GPI(GPP_F14, NONE, DEEP), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_GPO(GPP_F17, 1, DEEP), +/* EMMC_DATA5 */ PAD_CFG_GPO(GPP_F18, 1, DEEP), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_GPO(GPP_F22, 1, DEEP), +/* GPP_F23 */ + +/* SD_CMD */ PAD_CFG_GPI_APIC(GPP_G0, 20K_PD, DEEP), +/* SD_DATA0 */ PAD_CFG_GPO(GPP_G1, 1, DEEP), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES), +/* SD_DATA3 */ PAD_CFG_GPO(GPP_G4, 0, DEEP), +/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 0, DEEP), +/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), +/* SD_WP */ PAD_CFG_GPI_APIC(GPP_G7, NONE, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G8, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G9, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G10, 0, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G11, 1, DEEP), +/* TBD */ PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES), +/* TBD */ PAD_CFG_GPO(GPP_G13, 1, DEEP), +/* TBD */ +/* TBD */ PAD_CFG_GPO(GPP_G15, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G16, 0, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G17, 1, DEEP), +/* TBD */ PAD_CFG_GPI_ACPI_SCI(GPP_G18, NONE, DEEP, YES), +/* TBD */ +/* TBD */ PAD_CFG_GPO(GPP_G20, 1, DEEP), +/* TBD */ PAD_CFG_GPI_APIC(GPP_G21, 20K_PD, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G22, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G23, 1, DEEP), + +/* SD_CMD */ PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), +/* SD_DATA0 */ +/* SD_DATA1 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), +/* SD_DATA2 */ +/* SD_DATA3 */ PAD_CFG_GPO(GPP_H4, 0, DEEP), +/* SD_CD# */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_GPO(GPP_H6, 1, DEEP), +/* SD_WP */ PAD_CFG_GPO(GPP_H7, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H8, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H9, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H10, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H11, 1, DEEP), +/* TBD */ +/* TBD */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), +/* TBD */ PAD_CFG_GPI(GPP_H14, NONE, DEEP), +/* TBD */ PAD_CFG_GPI(GPP_H15, NONE, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H16, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H17, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H18, 1, DEEP), +/* TBD */ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), +/* TBD */ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), +/* TBD */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), +/* TBD */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), +/* TBD */ PAD_CFG_GPO(GPP_H23, 0, DEEP), + +/* SD_CMD */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + +/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7 */ +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +}; + +#endif +#endif diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h new file mode 100644 index 0000000..1312d9b --- /dev/null +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h @@ -0,0 +1,200 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + + 0x8086280B, + 0x00000000, + 0x00000005, + + /* + * Display Audio Verb Table + * Enable the third converter and Pin first (NID 08h) + */ + 0x00878101, + 0x00878101, + 0x00878101, + 0x00878101, + + AZALIA_PIN_CFG(0, 0x05, 0x18560010), + AZALIA_PIN_CFG(0, 0x06, 0x18560020), + AZALIA_PIN_CFG(0, 0x07, 0x18560030), + + /* Disable the third converter and third Pin (NID 08h) */ + 0x00878100, + 0x00878100, + 0x00878100, + 0x00878100, + + /* ALC 298 */ + 0x10EC0298, + 0x00000000, + 0x00000023, + + AZALIA_SUBVENDOR(0, 0x10EC109C), + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x411111F0), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x9017011F), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x03A11040), + AZALIA_PIN_CFG(0, 0x19, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1D, 0x4066A22D), + AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + AZALIA_PIN_CFG(0, 0x21, 0x03211020), + + /* Widget node 0x20 */ + 0x0205004F, + 0x0204B009, + 0x02050050, + 0x02041000, + /* Widget node 0x20 - 1 */ + 0x02050019, + 0x02040017, + 0x02050020, + 0x02040002, + /* Widget node 0x20 - 2 */ + 0x0205008F, + 0x02041008, + 0x02050036, + 0x020462C0, + /* Widget node 0x20 - 3 */ + 0x0205002B, + 0x02040D10, + 0x0205002D, + 0x02044020, + /* Widget node 0x20 - 4 */ + 0x0205000E, + 0x02046F80, + 0x01771F90, + 0x01771F90, + /* Widget node 0x20 - 5 */ + 0x02050079, + 0x02046800, + 0x02050079, + 0x02046800, + + /* TI AMP settings */ + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040000, + 0x02050025, + 0x02040000, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040002, + 0x02050025, + 0x02040011, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x0204000F, + 0x02050025, + 0x02040010, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040025, + 0x02050025, + 0x02040008, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040002, + 0x02050025, + 0x02040000, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040003, + 0x02050025, + 0x02040000, + 0x02050026, + 0x0204B010 +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id86f56df06795601cc9d7830766e54396d218e00 Gerrit-Change-Number: 29809 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/skylake: Add device settings for PL4 power limit
by PraveenX Hodagatta Pranesh (Code Review) 23 Nov '18

23 Nov '18

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29808 Change subject: soc/intel/skylake: Add device settings for PL4 power limit ...................................................................... soc/intel/skylake: Add device settings for PL4 power limit PL4 is a preemptive CPU package peak power limit,it will never be exceeded. Power is preemptively lowered before limit is reached. This change provides option in devicetree and feeds FSP PowerLimit4 UPD for power limit purpose. Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> Change-Id: I64b5a029104a102e5741e8b37c7992f2693180e8 --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/29808/1 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index b1ffcb2..21dddd4 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -97,6 +97,9 @@ /* TCC activation offset */ int tcc_offset; + /* Power Limit Related */ + u32 PowerLimit4; + /* PL2 Override value in Watts */ u32 tdp_pl2_override; /* PL1 Override value in Watts */ diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 8a78348..18c2aef 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -369,6 +369,7 @@ tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; + tconfig->PowerLimit4 = config->PowerLimit4; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree -- To view, visit https://review.coreboot.org/c/coreboot/+/29808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64b5a029104a102e5741e8b37c7992f2693180e8 Gerrit-Change-Number: 29808 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common: Add audio controller device id for SKL-H pch
by PraveenX Hodagatta Pranesh (Code Review) 23 Nov '18

23 Nov '18

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29807 Change subject: soc/intel/common: Add audio controller device id for SKL-H pch ...................................................................... soc/intel/common: Add audio controller device id for SKL-H pch This patch add new HDA controller pci id in common hda driver. BUG:None TEST:Boot to Yocto linux on kabylake rvp11 and verified audio playback functionality. Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> Change-Id: I820115c31bf6b8e1f1afe900b68690d84b51c259 --- M src/include/device/pci_ids.h M src/soc/intel/common/block/hda/hda.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/29807/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index b8354cf..b9c9152 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3046,6 +3046,7 @@ #define PCI_DEVICE_ID_INTEL_GLK_AUDIO 0x3198 #define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8 #define PCI_DEVICE_ID_INTEL_SKL_AUDIO 0x9d70 +#define PCI_DEVICE_ID_INTEL_SKL_H_AUDIO 0xa171 #define PCI_DEVICE_ID_INTEL_KBL_AUDIO 0x9d71 #define PCI_DEVICE_ID_INTEL_CNP_H_AUDIO 0xa348 #define PCI_DEVICE_ID_INTEL_ICL_AUDIO 0x34c8 diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index f1b5e05..5e09ddd 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -73,6 +73,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SKL_AUDIO, + PCI_DEVICE_ID_INTEL_SKL_H_AUDIO, PCI_DEVICE_ID_INTEL_KBL_AUDIO, PCI_DEVICE_ID_INTEL_CNL_AUDIO, PCI_DEVICE_ID_INTEL_CNP_H_AUDIO, -- To view, visit https://review.coreboot.org/c/coreboot/+/29807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I820115c31bf6b8e1f1afe900b68690d84b51c259 Gerrit-Change-Number: 29807 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Kconfig: Unify power-after-failure options
by Tristan Corrick (Code Review) 23 Nov '18

23 Nov '18

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29680 ) Change subject: Kconfig: Unify power-after-failure options ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Gerrit-Change-Number: 29680 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hellsenberg <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 23 Nov 2018 08:46:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: MAINTAINERS: add maintainer for all Siemens mc_xxxx mainboards
by Werner Zeh (Code Review) 23 Nov '18

23 Nov '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29806 Change subject: MAINTAINERS: add maintainer for all Siemens mc_xxxx mainboards ...................................................................... MAINTAINERS: add maintainer for all Siemens mc_xxxx mainboards Change-Id: If8f662d088bf57fd27c5a01a47bc094dcb53a4de Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M MAINTAINERS 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/29806/1 diff --git a/MAINTAINERS b/MAINTAINERS index f972aeb..1da010e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -287,6 +287,13 @@ S: Supported F: src/mainboard/pcengines/ +SIEMENS MC_xxxx MAINBOARDS +M: Werner Zeh <werner.zeh(a)siemens.com> +S: Maintained +F: src/mainboard/siemens/mc_apl1/ +F: src/mainboard/siemens/mc_bdx1/ +F: src/mainboard/siemens/mc_tcu3/ + AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE M: Timothy Pearson <tpearson(a)raptorengineeringinc.com> S: Supported -- To view, visit https://review.coreboot.org/c/coreboot/+/29806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8f662d088bf57fd27c5a01a47bc094dcb53a4de Gerrit-Change-Number: 29806 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation/../../icelake: Add Ice Lake coreboot development docume...
by Subrata Banik (Code Review) 23 Nov '18

23 Nov '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29805 Change subject: Documentation/../../icelake: Add Ice Lake coreboot development documentation ...................................................................... Documentation/../../icelake: Add Ice Lake coreboot development documentation Add documentation for Ice Lake processor family coreboot development. Documented so far: * What is Ice Lake * Development Strategy * Create coreboot Image * Flashing coreboot Change-Id: Ief4df6ca11f95b75ecddeb560f7887bfadced086 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A Documentation/soc/intel/icelake/IceLake_Coreboot_Development.md M Documentation/soc/intel/icelake/index.md 2 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/29805/1 diff --git a/Documentation/soc/intel/icelake/IceLake_Coreboot_Development.md b/Documentation/soc/intel/icelake/IceLake_Coreboot_Development.md new file mode 100644 index 0000000..d60cf79 --- /dev/null +++ b/Documentation/soc/intel/icelake/IceLake_Coreboot_Development.md @@ -0,0 +1,56 @@ +# Intel Ice Lake coreboot development + +## Introduction + +This document captures the coreboot development strategy for Intel SoC named Ice lake. + +The Ice Lake processor family is the next generation Intel® Core processor family. +These processors utilize Intels industry-leading 10 nm+ process technology. + +* Reference: https://www.intel.in/content/www/in/en/design/products-and-solutions/proces… + +## Development Strategy + +Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel common code development model". + +1. Intel develops initial Firmware code for Ice Lake SoC. + * CL: https://review.coreboot.org/#/c/coreboot/+/29162/ + +2. Additionally provides Firmware code support for Intel Reference Platform (RVP), known as Ice lake RVP with same SoC. + * CL: https://review.coreboot.org/#/c/coreboot/+/29164/ + +3. OEMs to design based on reference platform and make use of mainboard sample code. Rigth now Dragonegg is one of Ice Lake based mainboard developed by Google + * CL: https://review.coreboot.org/#/c/coreboot/+/29749/ + +### Summary: +* SoC as Ice Lake. +* Reference platform as icelake_rvp. +* OEM board as Dragonegg. + +## Create coreboot Image + +1. Clone latest coreboot code as below +$ git clone http://review.coreboot.org/p/coreboot + +2. Place blobs (ucode, me.bin and FSP packages) in appropriate locations + +Note: +Consider the fact that ucode an ME binary release process will remain same for Ice Lake program as well. +After PRQ,FSP binary will be available externally as any other program. + +3. Create coreboot .config + +4. Build toolchain + +CPUS=$(nproc--ignore=1) make crossgcc-i386 iasl + +5. Build image +$ make # the image is generated as build/coreboot.rom + +## Flashing coreboot + +Flashing is the same as other Intel boards: + +$ dut-control spi2_vref:pp3300 spi2_buf_en:on spi2_buf_on_flex_en:on warm_reset:on +$ sudo flashrom -n -p ft2232_spi:type=servo-v2 -w <bios_image> +$ dut-control spi2_vref:off spi2_buf_en:off spi2_buf_on_flex_en:off warm_reset:off diff --git a/Documentation/soc/intel/icelake/index.md b/Documentation/soc/intel/icelake/index.md index b4f512c..c295f8a 100644 --- a/Documentation/soc/intel/icelake/index.md +++ b/Documentation/soc/intel/icelake/index.md @@ -2,6 +2,10 @@ This section contains documentation about coreboot on specific Intel "Ice Lake" SOCs. +## Ice Lake coreboot development + +- [Ice Lake coreboot development](IceLake_Coreboot_Development.md) + ## Multiprocessor Init - [Multiprocessor Init](MultiProcessorInit.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/29805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief4df6ca11f95b75ecddeb560f7887bfadced086 Gerrit-Change-Number: 29805 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Add DPTF information
by Sumeet R Pawnikar (Code Review) 23 Nov '18

23 Nov '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29804 Change subject: mb/intel/icelake_rvp: Add DPTF information ...................................................................... mb/intel/icelake_rvp: Add DPTF information Currently, using these placeholder values. These will be updated after thermal tuning. Change-Id: Id206417e2e8029abe1de2a35f58dc4e801f3986b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- A src/mainboard/intel/icelake_rvp/acpi/dptf.asl M src/mainboard/intel/icelake_rvp/dsdt.asl 2 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/29804/1 diff --git a/src/mainboard/intel/icelake_rvp/acpi/dptf.asl b/src/mainboard/intel/icelake_rvp/acpi/dptf.asl new file mode 100644 index 0000000..cbe0792 --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/acpi/dptf.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 99 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index 7951501..2cc4079 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -33,7 +33,11 @@ { #include <soc/intel/icelake/acpi/northbridge.asl> #include <soc/intel/icelake/acpi/southbridge.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" } #if IS_ENABLED(CONFIG_CHROMEOS) -- To view, visit https://review.coreboot.org/c/coreboot/+/29804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id206417e2e8029abe1de2a35f58dc4e801f3986b Gerrit-Change-Number: 29804 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbfstool: Fix GCC error due to a shadowed declaration
by Werner Zeh (Code Review) 23 Nov '18

23 Nov '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29776 ) Change subject: util/cbfstool: Fix GCC error due to a shadowed declaration ...................................................................... util/cbfstool: Fix GCC error due to a shadowed declaration There is already a function with the name buffer_size(). Adding a local variable with the same name will lead to the following error on older GCC versions (e.g. version 4.4.7): declaration of 'buffer_size' shadows a global declaration To fix this rename the local variable to buffer_len. Change-Id: Ifae3a17152f2f9852d29a4ac038f7e5a75a41614 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/29776 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Joel Kitching <kitching(a)google.com> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M util/cbfstool/cbfs_image.c 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved Joel Kitching: Looks good to me, approved diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 3c5d29c..6ccc4f9 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -1299,7 +1299,7 @@ unsigned int decompressed_size = 0; unsigned int compression = cbfs_file_get_compression_info(entry, &decompressed_size); - unsigned int buffer_size; + unsigned int buffer_len; decomp_func_ptr decompress; if (do_processing) { @@ -1308,11 +1308,11 @@ ERROR("looking up decompression routine failed\n"); return -1; } - buffer_size = decompressed_size; + buffer_len = decompressed_size; } else { /* Force nop decompression */ decompress = decompression_function(CBFS_COMPRESS_NONE); - buffer_size = compressed_size; + buffer_len = compressed_size; } LOG("Found file %.30s at 0x%x, type %.12s, compressed %d, size %d\n", @@ -1321,8 +1321,8 @@ decompressed_size); buffer_init(&buffer, strdup("(cbfs_export_entry)"), NULL, 0); - buffer.data = malloc(buffer_size); - buffer.size = buffer_size; + buffer.data = malloc(buffer_len); + buffer.size = buffer_len; if (decompress(CBFS_SUBHEADER(entry), compressed_size, buffer.data, buffer.size, NULL)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/29776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifae3a17152f2f9852d29a4ac038f7e5a75a41614 Gerrit-Change-Number: 29776 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2018