coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S
by Patrick Georgi (Code Review) 22 Nov '18

22 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29687 ) Change subject: drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S ...................................................................... Patch Set 1: remove in src/drivers/intel/fsp1_1/after_raminit.S as well? -- To view, visit https://review.coreboot.org/c/coreboot/+/29687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61 Gerrit-Change-Number: 29687 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Thu, 22 Nov 2018 14:52:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: fix bug of sifive-gpt.py
by Patrick Georgi (Code Review) 22 Nov '18

22 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29767 ) Change subject: riscv: fix bug of sifive-gpt.py ...................................................................... riscv: fix bug of sifive-gpt.py The GPT version must be "00 00 01 00" and the little endian should be represented as 0x10000. Please refer to: https://en.wikipedia.org/wiki/GUID_Partition_Table Change-Id: Ib025197fc96f32823e687a89de0cee51c952b031 Signed-off-by: Xiang Wang <wxjstz(a)126.com> Reviewed-on: https://review.coreboot.org/c/29767 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/riscv/sifive-gpt.py 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jonathan Neuschäfer: Looks good to me, approved diff --git a/util/riscv/sifive-gpt.py b/util/riscv/sifive-gpt.py index 7f522d9..f1e4fa8 100755 --- a/util/riscv/sifive-gpt.py +++ b/util/riscv/sifive-gpt.py @@ -88,7 +88,7 @@ def pack_with_crc(self, crc): header_size = 92 header = struct.pack('<8sIIIIQQQQ16sQIII', - b'EFI PART', 0x100, header_size, crc, 0, + b'EFI PART', 0x10000, header_size, crc, 0, self.current_lba, self.backup_lba, self.first_usable_lba, self.last_usable_lba, self.uniq.get_bytes(), self.part_entries_lba, self.part_entries_number, -- To view, visit https://review.coreboot.org/c/coreboot/+/29767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib025197fc96f32823e687a89de0cee51c952b031 Gerrit-Change-Number: 29767 Gerrit-PatchSet: 4 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: intelblocks/cpu: Fix wrong comment for P_Req field in PERF_CTL MSR
by Werner Zeh (Code Review) 22 Nov '18

22 Nov '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29798 Change subject: intelblocks/cpu: Fix wrong comment for P_Req field in PERF_CTL MSR ...................................................................... intelblocks/cpu: Fix wrong comment for P_Req field in PERF_CTL MSR The mentioned bits 14:8 are wrong as the functions always write bits 15:8. What happens is visible in the written code. There is no need for an extra comment. Change-Id: I59b4d24d01a0a8fa74912f9754e7bbb217ca269d Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 2 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/29798/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index f2142d9..d18b50c 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -34,7 +34,7 @@ #include <stdint.h> /* - * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with + * Set PERF_CTL MSR (0x199) P_Req with * Turbo Ratio which is the Maximum Ratio. */ void cpu_set_max_ratio(void) @@ -86,7 +86,7 @@ * 23:16 - MAX_TURBO_3_CORES * 31:24 - MAX_TURBO_4_CORES * - * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value. + * Set PERF_CTL MSR (0x199) P_Req with that value. */ void cpu_set_p_state_to_turbo_ratio(void) { @@ -106,7 +106,7 @@ * TDP level ratio to be used for specific processor (in units * of 100MHz). * - * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value. + * Set PERF_CTL MSR (0x199) P_Req with that value. */ void cpu_set_p_state_to_nominal_tdp_ratio(void) { @@ -125,7 +125,7 @@ * PLATFORM_INFO MSR (0xCE) Bits 15:8 tells * MAX_NON_TURBO_LIM_RATIO. * - * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value. + * Set PERF_CTL MSR (0x199) P_Req with that value. */ void cpu_set_p_state_to_max_non_turbo_ratio(void) { @@ -142,7 +142,7 @@ } /* - * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with the value + * Set PERF_CTL MSR (0x199) P_Req with the value * for maximum efficiency. This value is reported in PLATFORM_INFO MSR (0xCE) * in Bits 47:40 and is extracted with cpu_get_min_ratio(). */ diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 0d51146..5cea96e 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -20,7 +20,7 @@ #include <stdint.h> /* - * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with + * Set PERF_CTL MSR (0x199) P_Req with * Turbo Ratio which is the Maximum Ratio. */ void cpu_set_max_ratio(void); @@ -52,7 +52,7 @@ * 23:16 - MAX_TURBO_3_CORES * 31:24 - MAX_TURBO_4_CORES * - * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value. + * Set PERF_CTL MSR (0x199) P_Req with that value. */ void cpu_set_p_state_to_turbo_ratio(void); @@ -61,7 +61,7 @@ * TDP level ratio to be used for specific processor (in units * of 100MHz). * - * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value. + * Set PERF_CTL MSR (0x199) P_Req with that value. */ void cpu_set_p_state_to_nominal_tdp_ratio(void); @@ -69,12 +69,12 @@ * PLATFORM_INFO MSR (0xCE) Bits 15:8 tells * MAX_NON_TURBO_LIM_RATIO. * - * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value. + * Set PERF_CTL MSR (0x199) P_Req with that value. */ void cpu_set_p_state_to_max_non_turbo_ratio(void); /* - * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with the value + * Set PERF_CTL MSR (0x199) P_Req with the value * for maximum efficiency. This value is reported in PLATFORM_INFO MSR (0xCE) * in Bits 47:40 and is extracted with cpu_get_min_ratio(). */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59b4d24d01a0a8fa74912f9754e7bbb217ca269d Gerrit-Change-Number: 29798 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbfstool: Fix GCC error due to a shadowed declaration
by Mario Scheithauer (Code Review) 22 Nov '18

22 Nov '18

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29776 ) Change subject: util/cbfstool: Fix GCC error due to a shadowed declaration ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifae3a17152f2f9852d29a4ac038f7e5a75a41614 Gerrit-Change-Number: 29776 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Nov 2018 14:01:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Add EC acpi support code
by Aamir Bohra (Code Review) 22 Nov '18

22 Nov '18

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29797 Change subject: mb/intel/icelake_rvp: Add EC acpi support code ...................................................................... mb/intel/icelake_rvp: Add EC acpi support code This implementation adds below changes: 1. Add chrome ec asl support for iclrvp. 2. EC SCI, SMI, S3/S5 wake events. 3. Wake pin and EC SMI GPE confiiguration. Change-Id: Ie95da92f7125e56fe9ef9d57a1098278c308918e Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/mainboard/intel/icelake_rvp/acpi/mainboard.asl M src/mainboard/intel/icelake_rvp/dsdt.asl A src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h A src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h 6 files changed, 172 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/29797/1 diff --git a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl new file mode 100644 index 0000000..49ae2e6 --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} +#endif diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index eb5c5ab..f1b3f51 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#include "variant/ec.h" +#include "variant/gpio.h" + DefinitionBlock( "dsdt.aml", "DSDT", @@ -28,6 +31,9 @@ // global NVS and variables #include <soc/intel/icelake/acpi/globalnvs.asl> + // CPU + #include <soc/intel/icelake/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) { @@ -41,6 +47,17 @@ #include <vendorcode/google/chromeos/acpi/chromeos.asl> #endif + #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } + #endif + // Chipset specific sleep states #include <soc/intel/icelake/acpi/sleepstates.asl> diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..03096ac --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#include <variant/gpio.h> + + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h index 36318d5..ca303f9 100644 --- a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h @@ -16,6 +16,13 @@ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ +#include <soc/gpe.h> #include <soc/gpio.h> +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h new file mode 100644 index 0000000..af41bf4 --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <baseboard/ec.h> + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h new file mode 100644 index 0000000..af41bf4 --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <baseboard/ec.h> + +#endif /* __MAINBOARD_EC_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie95da92f7125e56fe9ef9d57a1098278c308918e Gerrit-Change-Number: 29797 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5
by David Wu (Code Review) 22 Nov '18

22 Nov '18

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29796 Change subject: mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5 ...................................................................... mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5 Set GPP_B4 to low when entering S5. BUG=b:119594783 BRANCH=master TEST=Verify GPP_B4 is low. Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/fizz/smihandler.c M src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/fizz/variants/karma/Makefile.inc A src/mainboard/google/fizz/variants/karma/smihandler.c 4 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/29796/1 diff --git a/src/mainboard/google/fizz/smihandler.c b/src/mainboard/google/fizz/smihandler.c index 3aa9ddb..2b7367a 100644 --- a/src/mainboard/google/fizz/smihandler.c +++ b/src/mainboard/google/fizz/smihandler.c @@ -17,6 +17,7 @@ #include <ec/google/chromeec/smm.h> #include <soc/smm.h> +#include <baseboard/variants.h> #include <variant/ec.h> void mainboard_smi_espi_handler(void) @@ -24,8 +25,11 @@ chromeec_smi_process_events(); } +void __weak variant_smi_sleep(u8 slp_typ) {} + void mainboard_smi_sleep(u8 slp_typ) { + variant_smi_sleep(slp_typ); chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } diff --git a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h index 50e7ee3..40dfeeb 100644 --- a/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h @@ -29,6 +29,8 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); +void variant_smi_sleep(u8 slp_typ); + struct nhlt; void variant_nhlt_init(struct nhlt *nhlt); void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id, diff --git a/src/mainboard/google/fizz/variants/karma/Makefile.inc b/src/mainboard/google/fizz/variants/karma/Makefile.inc index 0ad298b..7475522 100644 --- a/src/mainboard/google/fizz/variants/karma/Makefile.inc +++ b/src/mainboard/google/fizz/variants/karma/Makefile.inc @@ -2,3 +2,5 @@ ramstage-y += gpio.c ramstage-y += nhlt.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/fizz/variants/karma/smihandler.c b/src/mainboard/google/fizz/variants/karma/smihandler.c new file mode 100644 index 0000000..187fb37 --- /dev/null +++ b/src/mainboard/google/fizz/variants/karma/smihandler.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <gpio.h> + +#define TS_PWROFF GPP_B4 + +void variant_smi_sleep(u8 slp_typ) +{ + if (slp_typ == ACPI_S5) { + /* Set TS Power off */ + gpio_set(TS_PWROFF, 0); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Gerrit-Change-Number: 29796 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Enable touchscreen wakeup
by David Wu (Code Review) 22 Nov '18

22 Nov '18

Hello Zhuohao Lee, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29769 to look at the new patch set (#2). Change subject: mb/google/fizz/variants/karma: Enable touchscreen wakeup ...................................................................... mb/google/fizz/variants/karma: Enable touchscreen wakeup Set GPIO GPP_B4 to high to enable touchscreen wakeup. BUG=b:119594783 BRANCH=master TEST=DUT can wake up with touchscreen. Change-Id: If0c9493dec367c7813047c7994cc83537aaef141 Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/fizz/variants/karma/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29769/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0c9493dec367c7813047c7994cc83537aaef141 Gerrit-Change-Number: 29769 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: google/kahlee/variants/aleena: Set STAPM values.
by Lucas Chen (Code Review) 22 Nov '18

22 Nov '18

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29795 Change subject: google/kahlee/variants/aleena: Set STAPM values. ...................................................................... google/kahlee/variants/aleena: Set STAPM values. According to aleena thermal testing to set STAPM values. skin scalar for 80%. time constant for 2500s. power limit for 7.8w. BUG=b:72979852 TEST=test build for thermal check. Change-Id: I09f1c1052dd317969546ac7d2bbde14cc563c160 Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/aleena/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/29795/1 diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index 784ea6f..fd807c4 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -20,6 +20,9 @@ register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "32 * MiB" + register "stapm_percent" = "80" + register "stapm_time_ms" = "2500000" + register "stapm_power_mw" = "7800" # Enable I2C0 for audio, USB3 hub at 400kHz register "i2c[0]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/29795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09f1c1052dd317969546ac7d2bbde14cc563c160 Gerrit-Change-Number: 29795 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbfstool/rmodule.c: Fix typo and correct header
by Frans Hendriks (Code Review) 22 Nov '18

22 Nov '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29794 Change subject: util/cbfstool/rmodule.c: Fix typo and correct header ...................................................................... util/cbfstool/rmodule.c: Fix typo and correct header Header contains ':' in copyright line. rmdoule is a typo Remove the ';' and correct typo to rmodule. BUG=N/A TEST=N/A Change-Id: I05b1fb80a81682646c9fba3d234de235b6bc9e8c Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M util/cbfstool/rmodule.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29794/1 diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index 07957cb..ff8f1cd 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -1,5 +1,6 @@ /* - ;* Copyright (C) 2014 Google, Inc. + * Copyright (C) 2014 Google, Inc. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -540,7 +541,7 @@ * section and the relocations can fit entirely within occupied memory * region for the program. The other is that the relocations increase * the memory footprint of the program if it was loaded directly into - * the region it would run. The rmdoule header is a fixed cost that + * the region it would run. The rmodule header is a fixed cost that * is considered a part of the program. */ total_size += buffer_size(&rmod_header); -- To view, visit https://review.coreboot.org/c/coreboot/+/29794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05b1fb80a81682646c9fba3d234de235b6bc9e8c Gerrit-Change-Number: 29794 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/icelake: Add support to enable/disable USB charging in s3/S5
by Aamir Bohra (Code Review) 22 Nov '18

22 Nov '18

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29793 Change subject: soc/intel/icelake: Add support to enable/disable USB charging in s3/S5 ...................................................................... soc/intel/icelake: Add support to enable/disable USB charging in s3/S5 Change-Id: I0559b8a546f7a67759377c7f51b2faa2280aa797 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/icelake/acpi/globalnvs.asl 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29793/1 diff --git a/src/soc/intel/icelake/acpi/globalnvs.asl b/src/soc/intel/icelake/acpi/globalnvs.asl index 678ce5a..b8f4d2f 100644 --- a/src/soc/intel/icelake/acpi/globalnvs.asl +++ b/src/soc/intel/icelake/acpi/globalnvs.asl @@ -48,8 +48,34 @@ U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap UIOR, 8, // 0x2f - UART debug controller init on S3 resume + S5U0, 8, // 0x30 - Enable USB in S5 + S3U0, 8, // 0x31 - Enable USB in S3 /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> } + +/* Set flag to enable USB charging in S3 */ +Method (S3UE) +{ + Store (One, \S3U0) +} + +/* Set flag to disable USB charging in S3 */ +Method (S3UD) +{ + Store (Zero, \S3U0) +} + +/* Set flag to enable USB charging in S5 */ +Method (S5UE) +{ + Store (One, \S5U0) +} + +/* Set flag to disable USB charging in S5 */ +Method (S5UD) +{ + Store (Zero, \S5U0) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0559b8a546f7a67759377c7f51b2faa2280aa797 Gerrit-Change-Number: 29793 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2018