coreboot-gerrit November 2018

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Change in ...coreboot[master]: soc/intel/apollolake: use a named choice for power settings
by Patrick Georgi (Code Review) 23 Nov '18

23 Nov '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29814 Change subject: soc/intel/apollolake: use a named choice for power settings ...................................................................... soc/intel/apollolake: use a named choice for power settings This prevents illegal configurations. Change-Id: I88598c5e32fc48d04f7c1e987a0b2549a87da8f2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/soc/intel/apollolake/Kconfig 5 files changed, 34 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29814/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig index 76d62fc..e2922f7 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig @@ -7,6 +7,9 @@ select DRIVERS_I2C_RX6110SA select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + +choice APL_POWER_SETTING + default APL_SKIP_SET_POWER_LIMITS +endchoice endif # BOARD_SIEMENS_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig index 32db935..811a21e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig @@ -7,6 +7,9 @@ select DRIVERS_I2C_RX6110SA select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + +choice APL_POWER_SETTING + default APL_SKIP_SET_POWER_LIMITS +endchoice endif # BOARD_SIEMENS_MC_APL3 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index 925b04f..19dfeab 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -4,6 +4,9 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select DRIVER_INTEL_I210 - select APL_SET_MIN_CLOCK_RATIO + +choice APL_POWER_SETTING + default APL_SET_MIN_CLOCK_RATIO +endchoice endif # BOARD_SIEMENS_MC_APL4 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index 196176c..0f6d1f5 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -7,6 +7,9 @@ select DRIVERS_I2C_RX6110SA select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY - select APL_SKIP_SET_POWER_LIMITS + +choice APL_POWER_SETTING + default APL_SKIP_SET_POWER_LIMITS +endchoice endif # BOARD_SIEMENS_MC_APL5 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4a841be..5c50f6e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -368,24 +368,29 @@ int default 100 +choice APL_POWER_SETTING + prompt "Power configuration" + help + Apollo Lake's power management can be configured in multiple ways: + By default the Running Average Power Limits (RAPL) algorithm can + setup power management reasonably. + Some hardware can also run without these limits, while for other, + the minimum CPU clock might be preferable as a default. + The OS can still override the configuration with a p-state driver. + +config APL_DEFAULT_POWER_LIMITS + bool + prompt "Use default RAPL algorithm" + config APL_SKIP_SET_POWER_LIMITS bool - default n - help - Some Apollo Lake mainboards do not need the Running Average Power - Limits (RAPL) algorithm for a constant power management. - Set this config option to skip the RAPL configuration. + prompt "Skip RAPL configuration" config APL_SET_MIN_CLOCK_RATIO bool - depends on !APL_SKIP_SET_POWER_LIMITS - default n - help - If the power budget of the mainboard is limited, it can be useful to - limit the CPU power dissipation at the cost of performance by setting - the lowest possible CPU clock. Enable this option if you need smallest - possible CPU clock. This setting can be overruled by the OS if it has an - p-state driver which can adjust the clock to its need. + prompt "Set clock ratio to the minimum possible" + +endchoice # M and N divisor values for clock frequency configuration. # These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) -- To view, visit https://review.coreboot.org/c/coreboot/+/29814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88598c5e32fc48d04f7c1e987a0b2549a87da8f2 Gerrit-Change-Number: 29814 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/lint: Allow non-option carrying named choices
by Patrick Georgi (Code Review) 23 Nov '18

23 Nov '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29813 Change subject: util/lint: Allow non-option carrying named choices ...................................................................... util/lint: Allow non-option carrying named choices named choices can be overridden with a default later-on: choice FOO config A config B config C endchoice ... if BOARD_FOO choice FOO default A endchoice endif Reflect that. Change-Id: I6662e19685f6ab0b84c78b30aedc266c0e176039 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/lint/kconfig_lint 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/29813/1 diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index eddd8de..4b0a77a 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -539,6 +539,7 @@ my $inside_config = ""; # set to symbol name of the config section my @inside_menu = (); # stack of menu names my $inside_choice = ""; + my $choice_symbol = ""; my $configs_inside_choice; my %fileinfo; @@ -626,6 +627,7 @@ my $symbol = $1; add_symbol( $symbol, \@inside_menu, $filename, $line_no, \@inside_if ); handle_type( "bool", $symbol, $filename, $line_no ); + $choice_symbol = $symbol; } $inside_config = ""; $inside_choice = "$filename $line_no"; @@ -642,10 +644,12 @@ } $inside_choice = ""; - if ( $configs_inside_choice == 0 ) { - show_error("choice block has no symbols at $filename:$line_no."); + if (( $configs_inside_choice == 0 ) && + ( $choice_symbol eq "" )) { + show_error("unnamed choice block has no symbols at $filename:$line_no."); } $configs_inside_choice = 0; + $choice_symbol=""; } # [optional] -- To view, visit https://review.coreboot.org/c/coreboot/+/29813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6662e19685f6ab0b84c78b30aedc266c0e176039 Gerrit-Change-Number: 29813 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apollolake: Remove cycle in Kconfig symbol dependencies
by Patrick Georgi (Code Review) 23 Nov '18

23 Nov '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29812 Change subject: soc/intel/apollolake: Remove cycle in Kconfig symbol dependencies ...................................................................... soc/intel/apollolake: Remove cycle in Kconfig symbol dependencies Change-Id: Iad60a5c8863283b7d373e1f6aaff48c40b7bb274 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/intel/apollolake/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/29812/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index c9b17b0..4a841be 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -370,7 +370,6 @@ config APL_SKIP_SET_POWER_LIMITS bool - depends on !APL_SET_MIN_CLOCK_RATIO default n help Some Apollo Lake mainboards do not need the Running Average Power -- To view, visit https://review.coreboot.org/c/coreboot/+/29812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad60a5c8863283b7d373e1f6aaff48c40b7bb274 Gerrit-Change-Number: 29812 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/x201/dsdt: Remove duplicated include
by Peter Lemenkov (Code Review) 23 Nov '18

23 Nov '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29811 Change subject: mb/lenovo/x201/dsdt: Remove duplicated include ...................................................................... mb/lenovo/x201/dsdt: Remove duplicated include Change-Id: Ifb08c903e19ef4e93bdc9cbc9844cb1888a8d2fa Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x201/dsdt.asl 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/29811/1 diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 8b2fb78..6ab1dee 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <arch/acpi.h> #define THINKPAD_EC_GPE 17 #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -- To view, visit https://review.coreboot.org/c/coreboot/+/29811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb08c903e19ef4e93bdc9cbc9844cb1888a8d2fa Gerrit-Change-Number: 29811 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/lenovo/*/dsdt: Move mainboard-specific defines out of ec.asl
by Peter Lemenkov (Code Review) 23 Nov '18

23 Nov '18

Hello Christoph Pomaska, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29543 to look at the new patch set (#3). Change subject: mb/lenovo/*/dsdt: Move mainboard-specific defines out of ec.asl ...................................................................... mb/lenovo/*/dsdt: Move mainboard-specific defines out of ec.asl Most Lenovo mainboards define their own specific defines in dsdt.asl. Let's make it consistent across all Lenovo mainboards. Tested - builds fine. Change-Id: I03fbeb09b25e42af2dfbb220c0f726e6abb73673 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t430/acpi/ec.asl M src/mainboard/lenovo/t430/dsdt.asl M src/mainboard/lenovo/x131e/acpi/ec.asl M src/mainboard/lenovo/x131e/dsdt.asl 4 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/29543/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03fbeb09b25e42af2dfbb220c0f726e6abb73673 Gerrit-Change-Number: 29543 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/lenovo/*/dsdt: Rearrange defines
by Peter Lemenkov (Code Review) 23 Nov '18

23 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29544 to look at the new patch set (#4). Change subject: mb/lenovo/*/dsdt: Rearrange defines ...................................................................... mb/lenovo/*/dsdt: Rearrange defines Sort mainboard-specific defines in the same order as in all other Lenovo boards. This is a purely cosmetic change which just makes diff between boards smaller. Change-Id: I4e379bb727b356fc6010e93de492f6d73f97a750 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/l520/dsdt.asl M src/mainboard/lenovo/s230u/dsdt.asl 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/29544/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e379bb727b356fc6010e93de492f6d73f97a750 Gerrit-Change-Number: 29544 Gerrit-PatchSet: 4 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: LinuxBoot: refactor u-root.mk
by Marcello Sylvester Bauer (Code Review) 23 Nov '18

23 Nov '18

Marcello Sylvester Bauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29778 ) Change subject: LinuxBoot: refactor u-root.mk ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/29778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id978ed2ebeff96c5be4f74ae07df9be76e106a1b Gerrit-Change-Number: 29778 Gerrit-PatchSet: 5 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Andrea Barberio <insomniac(a)slackware.it> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Nov 2018 13:54:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/skylake: Drop FSP_CAR options
by Nico Huber (Code Review) 23 Nov '18

23 Nov '18

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29533 ) Change subject: soc/intel/skylake: Drop FSP_CAR options ...................................................................... soc/intel/skylake: Drop FSP_CAR options It's not implemented for Skylake, all combinations that try to enable it either result in Kconfig or linker errors. Move `config SKIP_FSP_CAR` into drivers/intel/fsp1_1 where it's effective. TEST=Built Intel/Kunimitsu (FSP1.1) and Intel/KBLRVP8 (FSP2.0) default configs with and without this patch: binaries stay the same. Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/29533 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/romstage/romstage.c 3 files changed, 10 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 69fa8df..af6ed42 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -94,4 +94,9 @@ bool "Reset the system on S3 wake when ramstage cache invalid." default n +config SKIP_FSP_CAR + def_bool n + help + Selected by platforms that implement their own CAR setup. + endif #PLATFORM_USES_FSP1_1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ae8253a..8e85efa 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -34,6 +34,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select IOAPIC select MRC_SETTINGS_PROTECT @@ -50,6 +51,7 @@ select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -97,6 +99,7 @@ depends on !MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP1_1 select DISPLAY_FSP_ENTRY_POINTS + select SKIP_FSP_CAR config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -269,32 +272,6 @@ help Include DSP firmware settings for DA7219 headset codec. -choice - prompt "Cache-as-ram implementation" - default USE_SKYLAKE_CAR_NEM_ENHANCED - help - This option allows you to select how cache-as-ram (CAR) is set up. - -config USE_SKYLAKE_CAR_NEM_ENHANCED - bool "Enhanced Non-evict mode" - select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED - help - A current limitation of NEM (Non-Evict mode) is that code and data - sizes are derived from the requirement to not write out any modified - cache line. With NEM, if there is no physical memory behind the - cached area, the modified data will be lost and NEM results will be - inconsistent. ENHANCED NEM guarantees that modified data is always - kept in cache while clean data is replaced. - -config USE_SKYLAKE_FSP_CAR - bool "Use FSP CAR" - select FSP_CAR - help - Use FSP APIs to initialize and tear down the Cache-As-Ram. - -endchoice - config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 @@ -309,12 +286,6 @@ default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_KABYLAKE -config SKIP_FSP_CAR - bool "Skip cache as RAM setup in FSP" - default y - help - Skip Cache as RAM setup in FSP. - config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index b194258..e38ae51 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -83,10 +83,8 @@ upd->SaGv = config->SaGv; upd->RMT = config->Rmt; upd->DdrFreqLimit = config->DdrFreqLimit; - if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) { - upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; - upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE; - } + upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; + upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE; } void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/29533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28 Gerrit-Change-Number: 29533 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boon Tiong Teo <boon.tiong.teo(a)intel.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: src/arch/x86/acpi.c: Create log area and extend TPM2 table
by Philipp Deppenwiese (Code Review) 23 Nov '18

23 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29800 ) Change subject: src/arch/x86/acpi.c: Create log area and extend TPM2 table ...................................................................... src/arch/x86/acpi.c: Create log area and extend TPM2 table According to newest TCG ACPI Specification for Family 1.2 and 2.0 Version 1.2, Revision 8, TPM2 ACPI table has two more fields LAML and LASA. Update the table structure definition, create the log area for TPM2 in coreboot tables and fill the missing fields in TPM2 table. TPM2 should be now probed well in SeaBIOS rel-1.12.0 or master. Tested on apu2 with Infineon SLB9665 TT2.0. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/29800 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h M src/commonlib/include/commonlib/cbmem_id.h 3 files changed, 43 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index f54aa19..3b33f1b 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -308,12 +308,47 @@ header->checksum = acpi_checksum((void *)tcpa, header->length); } +static void *get_tpm2_log(u32 *size) +{ + const struct cbmem_entry *ce; + const u32 tpm2_default_log_len = 0x10000; + void *lasa; + ce = cbmem_entry_find(CBMEM_ID_TPM2_TCG_LOG); + if (ce) { + lasa = cbmem_entry_start(ce); + *size = cbmem_entry_size(ce); + printk(BIOS_DEBUG, "TPM2 log found at %p\n", lasa); + return lasa; + } + lasa = cbmem_add(CBMEM_ID_TPM2_TCG_LOG, tpm2_default_log_len); + if (!lasa) { + printk(BIOS_ERR, "TPM2 log creation failed\n"); + return NULL; + } + + printk(BIOS_DEBUG, "TPM2 log created at %p\n", lasa); + memset(lasa, 0, tpm2_default_log_len); + + *size = tpm2_default_log_len; + return lasa; +} + static void acpi_create_tpm2(acpi_tpm2_t *tpm2) { acpi_header_t *header = &(tpm2->header); + u32 tpm2_log_len; + void *lasa; memset((void *)tpm2, 0, sizeof(acpi_tpm2_t)); + /* + * Some payloads like SeaBIOS depend on log area to use TPM2. + * Get the memory size and address of TPM2 log area or initialize it. + */ + lasa = get_tpm2_log(&tpm2_log_len); + if (!lasa) + tpm2_log_len = 0; + /* Fill out header fields. */ memcpy(header->signature, "TPM2", 4); memcpy(header->oem_id, OEM_ID, 6); @@ -331,6 +366,10 @@ tpm2->start_method = 6; memset(tpm2->msp, 0, sizeof(tpm2->msp)); + /* Fill the log area size and start address fields. */ + tpm2->laml = tpm2_log_len; + tpm2->lasa = (uintptr_t) lasa; + /* Calculate checksum. */ header->checksum = acpi_checksum((void *)tpm2, header->length); } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index f6944e4..da125b4 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -199,6 +199,8 @@ u64 control_area; u32 start_method; u8 msp[12]; + u32 laml; + u64 lasa; } __packed acpi_tpm2_t; typedef struct acpi_mcfg_mmconfig { diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 042ea6e..2e0eeb6 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -65,6 +65,7 @@ #define CBMEM_ID_TCPA_LOG 0x54435041 #define CBMEM_ID_TCPA_TCG_LOG 0x54445041 #define CBMEM_ID_TIMESTAMP 0x54494d45 +#define CBMEM_ID_TPM2_TCG_LOG 0x54504d32 #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 #define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 @@ -121,6 +122,7 @@ { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \ { CBMEM_ID_TCPA_TCG_LOG, "TCPA TCGLOG" }, \ { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \ + { CBMEM_ID_TPM2_TCG_LOG, "TPM2 TCGLOG" }, \ { CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \ { CBMEM_ID_VBOOT_SEL_REG, "VBOOT SEL " }, \ { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/29800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3 Gerrit-Change-Number: 29800 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: src/arch/x86/acpi.c: Create log area and extend TPM2 table
by Philipp Deppenwiese (Code Review) 23 Nov '18

23 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29800 ) Change subject: src/arch/x86/acpi.c: Create log area and extend TPM2 table ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3 Gerrit-Change-Number: 29800 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Nov 2018 12:56:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2018