coreboot-gerrit November 2018

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Change in ...coreboot[master]: Documentation/../../dragonegg: Add dragonegg coreboot development doc...
by Patrick Rudolph (Code Review) 26 Nov '18

26 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29829 ) Change subject: Documentation/../../dragonegg: Add dragonegg coreboot development documentation ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29829/1/Documentation/mainboard/google/drag… File Documentation/mainboard/google/dragonegg.md: https://review.coreboot.org/#/c/29829/1/Documentation/mainboard/google/drag… PS1, Line 1: # Google Dragonegg (Chromebook) must be referenced from Documentation/mainboard/index.md -- To view, visit https://review.coreboot.org/c/coreboot/+/29829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15e317557a0893d9f80cc9e87c6b90c85b93dcf Gerrit-Change-Number: 29829 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 07:45:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation/../../icelake_rvp: Add RVP coreboot development documen...
by Arthur Heymans (Code Review) 26 Nov '18

26 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29828 ) Change subject: Documentation/../../icelake_rvp: Add RVP coreboot development documentation ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Is this a WIP stub? It does not contain that much useful information. https://review.coreboot.org/#/c/29828/1/Documentation/mainboard/intel/icela… File Documentation/mainboard/intel/icelake_rvp.md: https://review.coreboot.org/#/c/29828/1/Documentation/mainboard/intel/icela… PS1, Line 3: This page describes how to run coreboot on the Intel icelake_rvp board. I don't think this is accurate... Please add what Kconfig options you need to configure (the defaults most certainly won't boot) -- To view, visit https://review.coreboot.org/c/coreboot/+/29828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If063cbd3436d9ee107945f425a31ba0009039a1d Gerrit-Change-Number: 29828 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 07:40:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation/../../icelake_rvp: Add RVP coreboot development documen...
by Subrata Banik (Code Review) 26 Nov '18

26 Nov '18

Subrata Banik has removed Patrick Georgi from this change. ( https://review.coreboot.org/c/coreboot/+/29828 ) Change subject: Documentation/../../icelake_rvp: Add RVP coreboot development documentation ...................................................................... Removed reviewer Patrick Georgi. -- To view, visit https://review.coreboot.org/c/coreboot/+/29828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If063cbd3436d9ee107945f425a31ba0009039a1d Gerrit-Change-Number: 29828 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in ...coreboot[master]: Documentation/../../dragonegg: Add dragonegg coreboot development doc...
by Subrata Banik (Code Review) 26 Nov '18

26 Nov '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29829 Change subject: Documentation/../../dragonegg: Add dragonegg coreboot development documentation ...................................................................... Documentation/../../dragonegg: Add dragonegg coreboot development documentation Change-Id: Ia15e317557a0893d9f80cc9e87c6b90c85b93dcf Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A Documentation/mainboard/google/dragonegg.md 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/29829/1 diff --git a/Documentation/mainboard/google/dragonegg.md b/Documentation/mainboard/google/dragonegg.md new file mode 100644 index 0000000..ea283d7 --- /dev/null +++ b/Documentation/mainboard/google/dragonegg.md @@ -0,0 +1,24 @@ +# Google Dragonegg (Chromebook) + +This page describes how to run coreboot on the google dragonegg board. + +Dragonegg is based on Intel Ice Lake platform, please refer to below link to get more details +* Ice Lake coreboot development(iceLake_coreboot_development.md) + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Size | 32 MiB | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ +``` -- To view, visit https://review.coreboot.org/c/coreboot/+/29829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15e317557a0893d9f80cc9e87c6b90c85b93dcf Gerrit-Change-Number: 29829 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation/../../icelake_rvp: Add RVP coreboot development documen...
by Subrata Banik (Code Review) 26 Nov '18

26 Nov '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29828 Change subject: Documentation/../../icelake_rvp: Add RVP coreboot development documentation ...................................................................... Documentation/../../icelake_rvp: Add RVP coreboot development documentation Change-Id: If063cbd3436d9ee107945f425a31ba0009039a1d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A Documentation/mainboard/intel/icelake_rvp.md 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/29828/1 diff --git a/Documentation/mainboard/intel/icelake_rvp.md b/Documentation/mainboard/intel/icelake_rvp.md new file mode 100644 index 0000000..e6c0809 --- /dev/null +++ b/Documentation/mainboard/intel/icelake_rvp.md @@ -0,0 +1,24 @@ +# Intel Ice Lake RVP (Reference Validation Platform) + +This page describes how to run coreboot on the Intel icelake_rvp board. + +Ice Lake RVP is based on Intel Ice Lake platform, please refer to below link to get more details +* Ice Lake coreboot development(iceLake_coreboot_development.md) + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Size | 32 MiB | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ +``` -- To view, visit https://review.coreboot.org/c/coreboot/+/29828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If063cbd3436d9ee107945f425a31ba0009039a1d Gerrit-Change-Number: 29828 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/vboot: Add VB2_LIB to romstage sources without dependencies
by Werner Zeh (Code Review) 26 Nov '18

26 Nov '18

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29827 to look at the new patch set (#2). Change subject: security/vboot: Add VB2_LIB to romstage sources without dependencies ...................................................................... security/vboot: Add VB2_LIB to romstage sources without dependencies The coming feature "measured boot" relies on VB2_LIB in romstage. In the case where there is no separate verstage, compile the library just for romstage as it will then be shared across verstage and romstage code. If there is a separate verstage, compile the library separately for verstage and romstage. Change-Id: I8126c21b8fbe8dd65d95af49cbe2ad776b8ef605 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/security/vboot/Makefile.inc 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/29827/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8126c21b8fbe8dd65d95af49cbe2ad776b8ef605 Gerrit-Change-Number: 29827 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security/vboot: Add VB2_LIB to romstage sources without dependencies
by Werner Zeh (Code Review) 26 Nov '18

26 Nov '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29827 Change subject: security/vboot: Add VB2_LIB to romstage sources without dependencies ...................................................................... security/vboot: Add VB2_LIB to romstage sources without dependencies The coming feature "measured boot" relies on VB2_LIB in romstage. After the compilation of VB2_LIB has been restructured it is safe to add the library to romstage without dependencies. Change-Id: I8126c21b8fbe8dd65d95af49cbe2ad776b8ef605 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/security/vboot/Makefile.inc 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/29827/1 diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index da5d5b1..1edb452 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -112,15 +112,12 @@ $(eval $(call vboot-for-stage,verstage)) $(eval $(call vboot-for-stage,bootblock)) +$(eval $(call vboot-for-stage,romstage)) $(eval $(call vboot-for-stage,ramstage)) $(eval $(call vboot-for-stage,postcar)) ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y) -ifeq ($(CONFIG_VBOOT_HAS_REC_HASH_SPACE),y) -$(eval $(call vboot-for-stage,romstage)) -endif - cbfs-files-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += $(CONFIG_CBFS_PREFIX)/verstage $(CONFIG_CBFS_PREFIX)/verstage-file := $(objcbfs)/verstage.elf $(CONFIG_CBFS_PREFIX)/verstage-type := stage -- To view, visit https://review.coreboot.org/c/coreboot/+/29827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8126c21b8fbe8dd65d95af49cbe2ad776b8ef605 Gerrit-Change-Number: 29827 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/crossgcc: Document how to build the toolchain for another location
by Patrick Georgi (Code Review) 24 Nov '18

24 Nov '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29826 Change subject: util/crossgcc: Document how to build the toolchain for another location ...................................................................... util/crossgcc: Document how to build the toolchain for another location One common issue with the toolchain is that it takes a very long time to build while it's somewhat volatile inside the coreboot tree. Installing the toolchain elsewhere helps keep it safe but since there is no reliable default location outside the tree, keep the default as is. Change-Id: Ic414cddfd3c7097412f3f2c3c7ec7b7191fa32de Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/crossgcc/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29826/1 diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index f7da7de..f4aa364 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -28,6 +28,7 @@ @echo ' crosstools-ARCH - Build cross-compiler with GDB for specific architecture' @echo ' ARCH can be "$(subst $(spc),"$(comma) ",$(TOOLCHAIN_ARCHES))"' @echo ' Use "make [target] CPUS=#" to build toolchain using multiple cores' + @echo ' Use "make [target] DEST=some/path" to install toolchain there' @echo # For the toolchain builds, use CPUS=x to use multiple processors to build -- To view, visit https://review.coreboot.org/c/coreboot/+/29826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic414cddfd3c7097412f3f2c3c7ec7b7191fa32de Gerrit-Change-Number: 29826 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/Kconfig: Unhide SMBIOS_ENCLOSURE_TYPE prompt
by HAOUAS Elyes (Code Review) 24 Nov '18

24 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29825 Change subject: src/Kconfig: Unhide SMBIOS_ENCLOSURE_TYPE prompt ...................................................................... src/Kconfig: Unhide SMBIOS_ENCLOSURE_TYPE prompt This makes possible to enter system enclosure type other than 0x03 or 0x09. Clarify Mainboard's fields to store for SMBIOS structures. Change-Id: Ifea2376e5abd44232c80daa73e480e695de7d87c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/Kconfig 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/29825/1 diff --git a/src/Kconfig b/src/Kconfig index 62a7a92..0f30ea2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -623,7 +623,7 @@ default n config MAINBOARD_SERIAL_NUMBER - string "SMBIOS Serial Number" + string "SMBIOS: Mainboard Serial Number" depends on GENERATE_SMBIOS_TABLES depends on !SMBIOS_PROVIDED_BY_MOBO default "123456789" @@ -631,7 +631,7 @@ The Serial Number to store in SMBIOS structures. config MAINBOARD_VERSION - string "SMBIOS Version Number" + string "SMBIOS: Mainboard Version Number" depends on GENERATE_SMBIOS_TABLES depends on !SMBIOS_PROVIDED_BY_MOBO default "1.0" @@ -639,7 +639,7 @@ The Version Number to store in SMBIOS structures. config MAINBOARD_SMBIOS_MANUFACTURER - string "SMBIOS Manufacturer" + string "SMBIOS: Mainboard Manufacturer" depends on GENERATE_SMBIOS_TABLES depends on !SMBIOS_PROVIDED_BY_MOBO default MAINBOARD_VENDOR @@ -647,7 +647,7 @@ Override the default Manufacturer stored in SMBIOS structures. config MAINBOARD_SMBIOS_PRODUCT_NAME - string "SMBIOS Product name" + string "SMBIOS: Mainboard Product name" depends on GENERATE_SMBIOS_TABLES depends on !SMBIOS_PROVIDED_BY_MOBO default MAINBOARD_PART_NUMBER @@ -655,7 +655,7 @@ Override the default Product name stored in SMBIOS structures. config SMBIOS_ENCLOSURE_TYPE - hex + hex "SMBIOS: System Enclosure or Chassis Type" depends on GENERATE_SMBIOS_TABLES default 0x09 if SYSTEM_TYPE_LAPTOP default 0x03 -- To view, visit https://review.coreboot.org/c/coreboot/+/29825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea2376e5abd44232c80daa73e480e695de7d87c Gerrit-Change-Number: 29825 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Add and use defines for registers of device 0:01.0
by HAOUAS Elyes (Code Review) 24 Nov '18

24 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29824 Change subject: nb/intel/i945: Add and use defines for registers of device 0:01.0 ...................................................................... nb/intel/i945: Add and use defines for registers of device 0:01.0 Some registers are not documented in "Mobile Intel 945 Express Chipset Family" datasheet but they are in "Intel 945G/945GZ/ 945GC/945P/945PL Express Chipset Family" datasheet. Change-Id: I81f68a5b16e195626d4d271f8c7036032611bea3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/i945.h 2 files changed, 59 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29824/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 39d660b..5d70250 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -566,9 +566,9 @@ reg16 |= DEVEN_D1F0; pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x208); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGCC); reg32 &= ~(1 << 8); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), PEGCC, reg32); /* We have no success with querying the usual PCIe registers * for link setup success on the i945. Hence we assign a temporary @@ -576,25 +576,25 @@ */ /* First we reset the secondary bus */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); reg16 |= (1 << 6); /* SRESET */ - pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); /* Read back and clear reset bit. */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); reg16 &= ~(1 << 6); /* SRESET */ - pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS); printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); if (!(reg16 & 0x48)) goto disable_pciexpress_x16_link; reg16 |= (1 << 4) | (1 << 0); - pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), SLOTSTS, reg16); - pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x00); - pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x00); - pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x0a); - pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x0a); + pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x00); + pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x00); + pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x0a); + pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x0a); reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); reg32 &= ~(1 << 8); @@ -603,21 +603,21 @@ MCHBAR16(UPMC1) &= ~((1 << 5) | (1 << 0)); /* Initialize PEG_CAP */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xa2); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PEG_CAP); reg16 |= (1 << 8); - pci_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), PEG_CAP, reg16); /* Setup SLOTCAP */ /* TODO: These values are mainboard dependent and should * be set from devicetree.cb. */ /* NOTE: SLOTCAP becomes RO after the first write! */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xb4); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), SLOTCAP); reg32 &= 0x0007ffff; reg32 &= 0xfffe007f; - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), SLOTCAP, reg32); /* Wait for training to succeed */ printk(BIOS_DEBUG, "PCIe link training ..."); @@ -640,12 +640,12 @@ reg32 |= 1; pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); reg16 |= (1 << 6); - pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); reg16 &= ~(1 << 6); - pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16); + pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; @@ -664,22 +664,22 @@ } } - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xb2); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), LSTS); reg16 >>= 4; reg16 &= 0x3f; /* reg16 == 1 -> x1; reg16 == 16 -> x16 */ printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x204); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGTC); reg32 &= 0xfffffc00; /* clear [9:0] */ if (reg16 == 1) reg32 |= 0x32b; // TODO - /* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ + /* pci_write_config32(PCI_DEV(0, 0x01, 0), PEGTC, reg32); */ else if (reg16 == 16) reg32 |= 0x0f4; // TODO - /* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ + /* pci_write_config32(PCI_DEV(0, 0x01, 0), PEGTC, reg32); */ reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32); @@ -693,36 +693,36 @@ pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32); /* Set VGA enable bit in PCIe bridge */ - reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), 0x3e); + reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), BCTRL1); reg16 |= (1 << 3); - pci_write_config16(PCI_DEV(0, 0x1, 0), 0x3e, reg16); + pci_write_config16(PCI_DEV(0, 0x1, 0), BCTRL1, reg16); } /* Enable GPEs */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xec); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEG_LC); reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xec, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), PEG_LC, reg32); /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x114); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), VC0RCTL); reg32 &= 0xffffff01; - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), VC0RCTL, reg32); /* Extended VC count */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x104); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PVCCAP1); reg32 &= ~(7 << 0); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), PVCCAP1, reg32); /* Active State Power Management ASPM */ /* TODO */ /* Clear error bits */ - pci_write_config16(PCI_DEV(0, 0x01, 0), 0x06, 0xffff); - pci_write_config16(PCI_DEV(0, 0x01, 0), 0x1e, 0xffff); - pci_write_config16(PCI_DEV(0, 0x01, 0), 0xaa, 0xffff); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1c4, 0xffffffff); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1d0, 0xffffffff); + pci_write_config16(PCI_DEV(0, 0x01, 0), PCISTS1, 0xffff); + pci_write_config16(PCI_DEV(0, 0x01, 0), SSTS1, 0xffff); + pci_write_config16(PCI_DEV(0, 0x01, 0), DSTS, 0xffff); + pci_write_config32(PCI_DEV(0, 0x01, 0), UESTS, 0xffffffff); + pci_write_config32(PCI_DEV(0, 0x01, 0), CESTS, 0xffffffff); pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff); pci_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff); @@ -739,8 +739,8 @@ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328); pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); - reg8 = pci_read_config8(PCI_DEV(0, 0x01, 0), 0xb4); - pci_write_config8(PCI_DEV(0, 0x01, 0), 0xb4, reg8); + reg8 = pci_read_config8(PCI_DEV(0, 0x01, 0), SLOTCAP); + pci_write_config8(PCI_DEV(0, 0x01, 0), SLOTCAP, reg8); /* Additional PCIe graphics setup */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); @@ -874,10 +874,10 @@ /* PCI Express x16 Port Root Topology */ if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x158, DEFAULT_EPBAR); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x150); + pci_write_config32(PCI_DEV(0, 0x01, 0), LE1A, DEFAULT_EPBAR); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), LE1D); reg32 |= (1 << 0); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), LE1D, reg32); } } diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index cc5f087..b934a4b 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -83,7 +83,25 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */ +#define PCISTS1 0x06 /* 16bit */ +#define SBUSN1 0x19 /* 8bit */ +#define SUBUSN1 0x1a /* 8bit */ +#define SSTS1 0x1e /* 16bit */ #define BCTRL1 0x3e /* 16bit */ +#define PEG_CAP 0xa2 /* 16bit */ +#define DSTS 0xaa /* 16bit */ +#define LSTS 0xb2 /* 16bit */ +#define SLOTCAP 0xb4 /* 32bit */ +#define SLOTSTS 0xba /* 16bit */ +#define PEG_LC 0xec /* 32bit */ +#define PVCCAP 0x104 /* 32bit */ +#define VC0RCTL 0x114 /* 32bit */ +#define LE1D 0x150 /* 32bit */ +#define LE1A 0x158 /* 64bit */ +#define UESTS 0x1c4 /* 32bit */ +#define CESTS 0x1d0 /* 32bit */ +#define PEGTC 0x204 /* 32bit */ +#define PEGCC 0x208 /* 32bit */ #define PEGSTS 0x214 /* 32bit */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81f68a5b16e195626d4d271f8c7036032611bea3 Gerrit-Change-Number: 29824 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit November 2018