coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: security/vboot: Fix measured boot issues
by Philipp Deppenwiese (Code Review) 26 Nov '18

26 Nov '18

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29840 to look at the new patch set (#8). Change subject: security/vboot: Fix measured boot issues ...................................................................... security/vboot: Fix measured boot issues * Remove legacy and never published google purin. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add decompressor target for SPI/I2C TIS drivers. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/drivers/i2c/tpm/Makefile.inc M src/drivers/spi/tpm/Makefile.inc D src/mainboard/google/purin/Kconfig D src/mainboard/google/purin/Kconfig.name D src/mainboard/google/purin/Makefile.inc D src/mainboard/google/purin/board_info.txt D src/mainboard/google/purin/boardid.c D src/mainboard/google/purin/bootblock.c D src/mainboard/google/purin/chromeos.c D src/mainboard/google/purin/chromeos.fmd D src/mainboard/google/purin/devicetree.cb D src/mainboard/google/purin/mainboard.c D src/mainboard/google/purin/memlayout.ld D src/mainboard/google/purin/reset.c M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld 16 files changed, 17 insertions(+), 308 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29840/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/29840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Gerrit-Change-Number: 29840 Gerrit-PatchSet: 8 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security/vboot: Fix measured boot issues
by Philipp Deppenwiese (Code Review) 26 Nov '18

26 Nov '18

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29840 to look at the new patch set (#7). Change subject: security/vboot: Fix measured boot issues ...................................................................... security/vboot: Fix measured boot issues * Remove legacy and never published google purin. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/drivers/i2c/tpm/Makefile.inc M src/drivers/spi/tpm/Makefile.inc D src/mainboard/google/purin/Kconfig D src/mainboard/google/purin/Kconfig.name D src/mainboard/google/purin/Makefile.inc D src/mainboard/google/purin/board_info.txt D src/mainboard/google/purin/boardid.c D src/mainboard/google/purin/bootblock.c D src/mainboard/google/purin/chromeos.c D src/mainboard/google/purin/chromeos.fmd D src/mainboard/google/purin/devicetree.cb D src/mainboard/google/purin/mainboard.c D src/mainboard/google/purin/memlayout.ld D src/mainboard/google/purin/reset.c M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld 16 files changed, 17 insertions(+), 308 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29840/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/29840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Gerrit-Change-Number: 29840 Gerrit-PatchSet: 7 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/fsp_broadwell_de: Add early microcode updates
by Philipp Deppenwiese (Code Review) 26 Nov '18

26 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29819 ) Change subject: soc/fsp_broadwell_de: Add early microcode updates ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/29819/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29819/2//COMMIT_MSG@7 PS2, Line 7: soc/fsp_broadwell_de: Add early microcode updates > Allow me some time to catch up with the latest code base so I could help review your changes. […] Required for Intel TXT support. See updated commit message -- To view, visit https://review.coreboot.org/c/coreboot/+/29819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie31acaf0fc41c51b9edf65b981d43d7732661770 Gerrit-Change-Number: 29819 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 14:45:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Huang Jin <huang.jin(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Fix measured boot issues
by Philipp Deppenwiese (Code Review) 26 Nov '18

26 Nov '18

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29840 to look at the new patch set (#6). Change subject: security/vboot: Fix measured boot issues ...................................................................... security/vboot: Fix measured boot issues * Remove legacy and never published google purin. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add decompressor target for SPI/I2C TIS drivers. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/drivers/i2c/tpm/Makefile.inc M src/drivers/spi/tpm/Makefile.inc D src/mainboard/google/purin/Kconfig D src/mainboard/google/purin/Kconfig.name D src/mainboard/google/purin/Makefile.inc D src/mainboard/google/purin/board_info.txt D src/mainboard/google/purin/boardid.c D src/mainboard/google/purin/bootblock.c D src/mainboard/google/purin/chromeos.c D src/mainboard/google/purin/chromeos.fmd D src/mainboard/google/purin/devicetree.cb D src/mainboard/google/purin/mainboard.c D src/mainboard/google/purin/memlayout.ld D src/mainboard/google/purin/reset.c M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld 16 files changed, 10 insertions(+), 301 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29840/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/29840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Gerrit-Change-Number: 29840 Gerrit-PatchSet: 6 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security/vboot: Fix measured boot issues
by Philipp Deppenwiese (Code Review) 26 Nov '18

26 Nov '18

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29840 to look at the new patch set (#5). Change subject: security/vboot: Fix measured boot issues ...................................................................... security/vboot: Fix measured boot issues * Remove legacy and never published google purin. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add decompressor target for SPI/I2C TIS drivers. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/drivers/i2c/tpm/Makefile.inc M src/drivers/spi/tpm/Makefile.inc D src/mainboard/google/purin/Kconfig D src/mainboard/google/purin/Kconfig.name D src/mainboard/google/purin/Makefile.inc D src/mainboard/google/purin/board_info.txt D src/mainboard/google/purin/boardid.c D src/mainboard/google/purin/bootblock.c D src/mainboard/google/purin/chromeos.c D src/mainboard/google/purin/chromeos.fmd D src/mainboard/google/purin/devicetree.cb D src/mainboard/google/purin/mainboard.c D src/mainboard/google/purin/memlayout.ld D src/mainboard/google/purin/reset.c M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld 16 files changed, 10 insertions(+), 301 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29840/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/29840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Gerrit-Change-Number: 29840 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: security/vboot: Fix measured boot issues
by Philipp Deppenwiese (Code Review) 26 Nov '18

26 Nov '18

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29840 to look at the new patch set (#4). Change subject: security/vboot: Fix measured boot issues ...................................................................... security/vboot: Fix measured boot issues * Remove legacy and never published google purin. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/drivers/i2c/tpm/Makefile.inc M src/drivers/spi/tpm/Makefile.inc D src/mainboard/google/purin/Kconfig D src/mainboard/google/purin/Kconfig.name D src/mainboard/google/purin/Makefile.inc D src/mainboard/google/purin/board_info.txt D src/mainboard/google/purin/boardid.c D src/mainboard/google/purin/bootblock.c D src/mainboard/google/purin/chromeos.c D src/mainboard/google/purin/chromeos.fmd D src/mainboard/google/purin/devicetree.cb D src/mainboard/google/purin/mainboard.c D src/mainboard/google/purin/memlayout.ld D src/mainboard/google/purin/reset.c M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld 16 files changed, 10 insertions(+), 301 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29840/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Gerrit-Change-Number: 29840 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: security/vboot: Fix measured boot issues
by Philipp Deppenwiese (Code Review) 26 Nov '18

26 Nov '18

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29840 to look at the new patch set (#3). Change subject: security/vboot: Fix measured boot issues ...................................................................... security/vboot: Fix measured boot issues * Remove legacy and never published google purin. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- D src/mainboard/google/purin/Kconfig D src/mainboard/google/purin/Kconfig.name D src/mainboard/google/purin/Makefile.inc D src/mainboard/google/purin/board_info.txt D src/mainboard/google/purin/boardid.c D src/mainboard/google/purin/bootblock.c D src/mainboard/google/purin/chromeos.c D src/mainboard/google/purin/chromeos.fmd D src/mainboard/google/purin/devicetree.cb D src/mainboard/google/purin/mainboard.c D src/mainboard/google/purin/memlayout.ld D src/mainboard/google/purin/reset.c M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld 14 files changed, 6 insertions(+), 302 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29840/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Gerrit-Change-Number: 29840 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: security/vboot: Fix measured boot issues
by Philipp Deppenwiese (Code Review) 26 Nov '18

26 Nov '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29840 Change subject: security/vboot: Fix measured boot issues ...................................................................... security/vboot: Fix measured boot issues * Remove legacy and never published google purin. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- D src/mainboard/google/purin/Kconfig D src/mainboard/google/purin/Kconfig.name D src/mainboard/google/purin/Makefile.inc D src/mainboard/google/purin/board_info.txt D src/mainboard/google/purin/boardid.c D src/mainboard/google/purin/bootblock.c D src/mainboard/google/purin/chromeos.c D src/mainboard/google/purin/chromeos.fmd D src/mainboard/google/purin/devicetree.cb D src/mainboard/google/purin/mainboard.c D src/mainboard/google/purin/memlayout.ld D src/mainboard/google/purin/reset.c 12 files changed, 0 insertions(+), 296 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29840/1 diff --git a/src/mainboard/google/purin/Kconfig b/src/mainboard/google/purin/Kconfig deleted file mode 100644 index 4666453..0000000 --- a/src/mainboard/google/purin/Kconfig +++ /dev/null @@ -1,53 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2015 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_GOOGLE_PURIN - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select BOARD_ROMSIZE_KB_2048 - select COMMON_CBFS_SPI_WRAPPER - select MAINBOARD_HAS_CHROMEOS - select SOC_BROADCOM_CYGNUS - select SPI_FLASH - select SPI_FLASH_SPANSION - select SPI_FLASH_STMICRO # required for the reference board BCM958305K - select MAINBOARD_HAS_I2C_TPM_GENERIC - select MAINBOARD_HAS_TPM1 - -config VBOOT - select VBOOT_VBNV_FLASH - -config MAINBOARD_DIR - string - default google/purin - -config MAINBOARD_PART_NUMBER - string - default "Purin" - -config MAINBOARD_VENDOR - string - default "Google" - -config DRAM_SIZE_MB - int - default 256 - -config GBB_HWID - string - depends on CHROMEOS - default "Purin TEST 1" -endif # BOARD_GOOGLE_PURIN diff --git a/src/mainboard/google/purin/Kconfig.name b/src/mainboard/google/purin/Kconfig.name deleted file mode 100644 index db960087..0000000 --- a/src/mainboard/google/purin/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_PURIN - bool "Purin" diff --git a/src/mainboard/google/purin/Makefile.inc b/src/mainboard/google/purin/Makefile.inc deleted file mode 100644 index 5f13a8b..0000000 --- a/src/mainboard/google/purin/Makefile.inc +++ /dev/null @@ -1,36 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2015 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -bootblock-y += bootblock.c -bootblock-y += boardid.c -bootblock-y += chromeos.c -bootblock-y += reset.c - -verstage-y += boardid.c -verstage-y += chromeos.c -verstage-y += reset.c - -romstage-y += boardid.c -romstage-y += chromeos.c -romstage-y += reset.c - -ramstage-y += boardid.c -ramstage-y += chromeos.c -ramstage-y += mainboard.c -ramstage-y += reset.c - -bootblock-y += memlayout.ld -verstage-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/purin/board_info.txt b/src/mainboard/google/purin/board_info.txt deleted file mode 100644 index 878db18..0000000 --- a/src/mainboard/google/purin/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: Google -Board name: Purin Broadcom Cygnus reference board -Category: eval -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/google/purin/boardid.c b/src/mainboard/google/purin/boardid.c deleted file mode 100644 index 901d837..0000000 --- a/src/mainboard/google/purin/boardid.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boardid.h> - -uint32_t board_id(void) -{ - return -1; -} diff --git a/src/mainboard/google/purin/bootblock.c b/src/mainboard/google/purin/bootblock.c deleted file mode 100644 index 18c1f5f..0000000 --- a/src/mainboard/google/purin/bootblock.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 20145Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootblock_common.h> - -void bootblock_mainboard_init(void) -{ -} diff --git a/src/mainboard/google/purin/chromeos.c b/src/mainboard/google/purin/chromeos.c deleted file mode 100644 index 5e7cdfe..0000000 --- a/src/mainboard/google/purin/chromeos.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boot/coreboot_tables.h> -#include <vendorcode/google/chromeos/chromeos.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ -} - -int get_recovery_mode_switch(void) -{ - return 0; -} - -int get_write_protect_state(void) -{ - return 0; -} diff --git a/src/mainboard/google/purin/chromeos.fmd b/src/mainboard/google/purin/chromeos.fmd deleted file mode 100644 index 3f4ca84..0000000 --- a/src/mainboard/google/purin/chromeos.fmd +++ /dev/null @@ -1,32 +0,0 @@ -FLASH@0x0 0x200000 { - WP_RO@0x0 0x100000 { - RO_SECTION@0x0 0xf0000 { - BOOTBLOCK@0 128K - COREBOOT(CBFS)@0x20000 0x60000 - FMAP@0x80000 0x1000 - GBB@0x81000 0x6ef00 - RO_FRID@0xeff00 0x100 - } - RO_VPD@0xf0000 0x10000 - } - RW_SECTION_A@0x100000 0x58000 { - VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x55f00 - RW_FWID_A@0x57f00 0x100 - } - RW_SHARED@0x158000 0x4000 { - SHARED_DATA@0x0 0x4000 - } - RW_ELOG@0x15c000 0x4000 - RW_GPT@0x160000 0x20000 { - RW_GPT_PRIMARY@0x0 0x10000 - RW_GPT_SECONDARY@0x10000 0x10000 - } - RW_SECTION_B@0x180000 0x58000 { - VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x55f00 - RW_FWID_B@0x57f00 0x100 - } - RW_VPD@0x1d8000 0x8000 - RW_NVRAM@0x1e0000 0x10000 -} diff --git a/src/mainboard/google/purin/devicetree.cb b/src/mainboard/google/purin/devicetree.cb deleted file mode 100644 index 6ef5c3b..0000000 --- a/src/mainboard/google/purin/devicetree.cb +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2015 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# TODO fill with Versatile Express board data in QEMU. -chip soc/broadcom/cygnus - device cpu_cluster 0 on end -end diff --git a/src/mainboard/google/purin/mainboard.c b/src/mainboard/google/purin/mainboard.c deleted file mode 100644 index bc7b545..0000000 --- a/src/mainboard/google/purin/mainboard.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <boot/coreboot_tables.h> -#include <symbols.h> - -static void mainboard_init(struct device *dev) -{ -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = &mainboard_init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; - -void lb_board(struct lb_header *header) -{ - struct lb_range *dma; - - dma = (struct lb_range *)lb_new_record(header); - dma->tag = LB_TAB_DMA; - dma->size = sizeof(*dma); - dma->range_start = (uintptr_t)_dma_coherent; - dma->range_size = _dma_coherent_size; -} diff --git a/src/mainboard/google/purin/memlayout.ld b/src/mainboard/google/purin/memlayout.ld deleted file mode 100644 index 2c33306..0000000 --- a/src/mainboard/google/purin/memlayout.ld +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/memlayout.ld> diff --git a/src/mainboard/google/purin/reset.c b/src/mainboard/google/purin/reset.c deleted file mode 100644 index 51a2187..0000000 --- a/src/mainboard/google/purin/reset.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <reset.h> - -void do_board_reset(void) -{ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/29840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Gerrit-Change-Number: 29840 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/intel/icelake_rvp: Enable HDA audio support
by Aamir Bohra (Code Review) 26 Nov '18

26 Nov '18

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29838 Change subject: mb/intel/icelake_rvp: Enable HDA audio support ...................................................................... mb/intel/icelake_rvp: Enable HDA audio support This patch enables HDA audio support on icelake rvp. Add ALC700 codec verb table and selects SOC_INTEL_COMMON_BLOCK_HDA_VERB config to detect and initialize codec configuration as specified in verb table. BUG=none TEST=verify codec is listed and audio playback is working Change-Id: Ibdf707f9002a09870ebe879c9db462084ecb01ea Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/Kconfig M src/mainboard/intel/icelake_rvp/Makefile.inc A src/mainboard/intel/icelake_rvp/hda_verb.c A src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/hda_verb.h A src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h 5 files changed, 1,418 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/29838/1 diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig index ecab319..0741bf8 100644 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ b/src/mainboard/intel/icelake_rvp/Kconfig @@ -11,6 +11,7 @@ select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select DRIVERS_USB_ACPI + select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_ICELAKE config MAINBOARD_DIR diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc index f63b4bf..7e74f09 100644 --- a/src/mainboard/intel/icelake_rvp/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += board_id.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c ramstage-y += mainboard.c ramstage-y += board_id.c diff --git a/src/mainboard/intel/icelake_rvp/hda_verb.c b/src/mainboard/intel/icelake_rvp/hda_verb.c new file mode 100644 index 0000000..c87392d --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/hda_verb.c @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "variant/hda_verb.h" diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/hda_verb.h b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/hda_verb.h new file mode 100644 index 0000000..d821a26 --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/hda_verb.h @@ -0,0 +1,700 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* ALC 700 */ + 0x10EC0700, + 0xFFFFFFFF, + 0x00000023, + + AZALIA_SUBVENDOR(0, 0x10EC10F2), + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x411111F0), + AZALIA_PIN_CFG(0, 0x15, 0x411111F0), + AZALIA_PIN_CFG(0, 0x16, 0x411111F0), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + AZALIA_PIN_CFG(0, 0x19, 0x04A11030), + AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1D, 0x40622005), + AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1F, 0x411111F0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + AZALIA_PIN_CFG(0, 0x29, 0x411111F0), + + /* Widget node 0x20 */ + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + /* Widget node 0x20 - 1 */ + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + + //Widget node 0X20 for ALC1305 20160603 update + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204800F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02044848, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050000, + 0x02043330, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050000, + 0x02043333, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x020402EC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02044909, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x020440B0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040047, + 0x02050028, + 0x02040C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040048, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040049, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004A, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040001, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024 +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h new file mode 100644 index 0000000..d821a26 --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h @@ -0,0 +1,700 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* ALC 700 */ + 0x10EC0700, + 0xFFFFFFFF, + 0x00000023, + + AZALIA_SUBVENDOR(0, 0x10EC10F2), + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x411111F0), + AZALIA_PIN_CFG(0, 0x15, 0x411111F0), + AZALIA_PIN_CFG(0, 0x16, 0x411111F0), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + AZALIA_PIN_CFG(0, 0x19, 0x04A11030), + AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1B, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1D, 0x40622005), + AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1F, 0x411111F0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + AZALIA_PIN_CFG(0, 0x29, 0x411111F0), + + /* Widget node 0x20 */ + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + /* Widget node 0x20 - 1 */ + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + + //Widget node 0X20 for ALC1305 20160603 update + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204800F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02044848, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050000, + 0x02043330, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050000, + 0x02043333, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x020402EC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02044909, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x020440B0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040047, + 0x02050028, + 0x02040C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040048, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040049, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004A, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040001, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024 +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdf707f9002a09870ebe879c9db462084ecb01ea Gerrit-Change-Number: 29838 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mediatek: Share GPIO external interrupts (EINT) code among similar SoCs
by Tristan Hsieh (Code Review) 26 Nov '18

26 Nov '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29837 Change subject: mediatek: Share GPIO external interrupts (EINT) code among similar SoCs ...................................................................... mediatek: Share GPIO external interrupts (EINT) code among similar SoCs Refactor GPIO EINT code which can be reused among similar SoCs. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot; emerge-kukui coreboot Change-Id: Ib01b43cf1aa4082d7d968fe1ef82f75e8cf05b8b Signed-off-by: Chuanjia Liu <Chuanjia.Liu(a)mediatek.com> --- M src/soc/mediatek/common/gpio.c M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/mt8173/gpio.c M src/soc/mediatek/mt8173/include/soc/gpio.h M src/soc/mediatek/mt8183/include/soc/addressmap.h M src/soc/mediatek/mt8183/include/soc/gpio.h 6 files changed, 116 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/29837/1 diff --git a/src/soc/mediatek/common/gpio.c b/src/soc/mediatek/common/gpio.c index 590f8ea..371ff26 100644 --- a/src/soc/mediatek/common/gpio.c +++ b/src/soc/mediatek/common/gpio.c @@ -126,3 +126,64 @@ gpio_set_dir(gpio, GPIO_DIRECTION_OUT); gpio_set_mode(gpio, GPIO_MODE); } + +enum { + MAX_EINT_REG_BITS = 32, +}; + +static void pos_bit_calc_for_eint(gpio_t gpio, u32 *pos, u32 *bit) +{ + *pos = gpio.id / MAX_EINT_REG_BITS; + *bit = gpio.id % MAX_EINT_REG_BITS; +} + +int gpio_eint_poll(gpio_t gpio) +{ + u32 pos; + u32 bit; + u32 status; + + pos_bit_calc_for_eint(gpio, &pos, &bit); + + status = (read32(&mtk_eint->sta.regs[pos]) >> bit) & 0x1; + + if (status) + write32(&mtk_eint->ack.regs[pos], 1 << bit); + + return status; +} + +void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type) +{ + u32 pos; + u32 bit, mask; + + pos_bit_calc_for_eint(gpio, &pos, &bit); + mask = 1 << bit; + + /* Make it an input first. */ + gpio_input_pullup(gpio); + + write32(&mtk_eint->d0en[pos], mask); + + switch (type) { + case IRQ_TYPE_EDGE_FALLING: + write32(&mtk_eint->sens_clr.regs[pos], mask); + write32(&mtk_eint->pol_clr.regs[pos], mask); + break; + case IRQ_TYPE_EDGE_RISING: + write32(&mtk_eint->sens_clr.regs[pos], mask); + write32(&mtk_eint->pol_set.regs[pos], mask); + break; + case IRQ_TYPE_LEVEL_LOW: + write32(&mtk_eint->sens_set.regs[pos], mask); + write32(&mtk_eint->pol_clr.regs[pos], mask); + break; + case IRQ_TYPE_LEVEL_HIGH: + write32(&mtk_eint->sens_set.regs[pos], mask); + write32(&mtk_eint->pol_set.regs[pos], mask); + break; + } + + write32(&mtk_eint->mask_clr.regs[pos], mask); +} diff --git a/src/soc/mediatek/common/include/soc/gpio_common.h b/src/soc/mediatek/common/include/soc/gpio_common.h index 22acd92..b9b9714 100644 --- a/src/soc/mediatek/common/include/soc/gpio_common.h +++ b/src/soc/mediatek/common/include/soc/gpio_common.h @@ -16,6 +16,9 @@ #ifndef SOC_MEDIATEK_COMMON_GPIO_H #define SOC_MEDIATEK_COMMON_GPIO_H +#include <stddef.h> +#include <stdint.h> + enum pull_enable { GPIO_PULL_DISABLE = 0, GPIO_PULL_ENABLE = 1, @@ -26,4 +29,42 @@ GPIO_PULL_UP = 1, }; +enum gpio_irq_type { + IRQ_TYPE_EDGE_RISING, + IRQ_TYPE_EDGE_FALLING, + IRQ_TYPE_LEVEL_HIGH, + IRQ_TYPE_LEVEL_LOW, +}; + +struct eint_section { + uint32_t regs[7]; + uint32_t align1[9]; +}; + +struct eint_regs { + struct eint_section sta; + struct eint_section ack; + struct eint_section mask; + struct eint_section mask_set; + struct eint_section mask_clr; + struct eint_section sens; + struct eint_section sens_set; + struct eint_section sens_clr; + struct eint_section soft; + struct eint_section soft_set; + struct eint_section soft_clr; + struct eint_section rsv00; + struct eint_section pol; + struct eint_section pol_set; + struct eint_section pol_clr; + struct eint_section rsv01; + uint32_t d0en[7]; + uint32_t rsv02; + uint32_t d1en[7]; +}; + +check_member(eint_regs, d1en, 0x420); + +static struct eint_regs *const mtk_eint = (void *)(EINT_BASE); + #endif diff --git a/src/soc/mediatek/mt8173/gpio.c b/src/soc/mediatek/mt8173/gpio.c index 518df85..259ac53 100644 --- a/src/soc/mediatek/mt8173/gpio.c +++ b/src/soc/mediatek/mt8173/gpio.c @@ -19,7 +19,6 @@ enum { MAX_GPIO_NUMBER = 134, - MAX_EINT_REG_BITS = 32, }; static void pos_bit_calc(gpio_t gpio, u32 *pos, u32 *bit) @@ -28,12 +27,6 @@ *bit = gpio.id % MAX_GPIO_REG_BITS; } -static void pos_bit_calc_for_eint(gpio_t gpio, u32 *pos, u32 *bit) -{ - *pos = gpio.id / MAX_EINT_REG_BITS; - *bit = gpio.id % MAX_EINT_REG_BITS; -} - void gpio_set_pull(gpio_t gpio, enum pull_enable enable, enum pull_select select) { @@ -63,54 +56,3 @@ } write16(en_reg, 1L << bit); } - -int gpio_eint_poll(gpio_t gpio) -{ - u32 pos; - u32 bit; - u32 status; - - pos_bit_calc_for_eint(gpio, &pos, &bit); - - status = (read32(&mt8173_eint->sta.regs[pos]) >> bit) & 0x1; - - if (status) - write32(&mt8173_eint->ack.regs[pos], 1 << bit); - - return status; -} - -void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type) -{ - u32 pos; - u32 bit, mask; - - pos_bit_calc_for_eint(gpio, &pos, &bit); - mask = 1 << bit; - - /* Make it an input first. */ - gpio_input_pullup(gpio); - - write32(&mt8173_eint->d0en[pos], mask); - - switch (type) { - case IRQ_TYPE_EDGE_FALLING: - write32(&mt8173_eint->sens_clr.regs[pos], mask); - write32(&mt8173_eint->pol_clr.regs[pos], mask); - break; - case IRQ_TYPE_EDGE_RISING: - write32(&mt8173_eint->sens_clr.regs[pos], mask); - write32(&mt8173_eint->pol_set.regs[pos], mask); - break; - case IRQ_TYPE_LEVEL_LOW: - write32(&mt8173_eint->sens_set.regs[pos], mask); - write32(&mt8173_eint->pol_clr.regs[pos], mask); - break; - case IRQ_TYPE_LEVEL_HIGH: - write32(&mt8173_eint->sens_set.regs[pos], mask); - write32(&mt8173_eint->pol_set.regs[pos], mask); - break; - } - - write32(&mt8173_eint->mask_clr.regs[pos], mask); -} diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h index a78c8b4..e2bd12f 100644 --- a/src/soc/mediatek/mt8173/include/soc/gpio.h +++ b/src/soc/mediatek/mt8173/include/soc/gpio.h @@ -369,44 +369,6 @@ void gpio_set_mode(gpio_t gpio, int mode); void gpio_init(enum external_power); -enum gpio_irq_type { - IRQ_TYPE_EDGE_RISING, - IRQ_TYPE_EDGE_FALLING, - IRQ_TYPE_LEVEL_HIGH, - IRQ_TYPE_LEVEL_LOW, -}; - -struct eint_section { - uint32_t regs[7]; - uint32_t align1[9]; -}; - -struct eint_regs { - struct eint_section sta; - struct eint_section ack; - struct eint_section mask; - struct eint_section mask_set; - struct eint_section mask_clr; - struct eint_section sens; - struct eint_section sens_set; - struct eint_section sens_clr; - struct eint_section soft; - struct eint_section soft_set; - struct eint_section soft_clr; - struct eint_section rsv00; - struct eint_section pol; - struct eint_section pol_set; - struct eint_section pol_clr; - struct eint_section rsv01; - uint32_t d0en[7]; - uint32_t rsv02; - uint32_t d1en[7]; -}; - -check_member(eint_regs, d1en, 0x420); - -static struct eint_regs *const mt8173_eint = (void *)(EINT_BASE); - /* * Firmware never enables interrupts on this platform. This function * reads current EINT status and clears the pending interrupt. diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index cee9bd8..23a6804 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -28,6 +28,7 @@ SPM_BASE = IO_PHYS + 0x00006000, RGU_BASE = IO_PHYS + 0x00007000, GPT_BASE = IO_PHYS + 0x00008000, + EINT_BASE = IO_PHYS + 0x0000B000, APMIXED_BASE = IO_PHYS + 0x0000C000, EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, diff --git a/src/soc/mediatek/mt8183/include/soc/gpio.h b/src/soc/mediatek/mt8183/include/soc/gpio.h index 1faab44..12a8c10 100644 --- a/src/soc/mediatek/mt8183/include/soc/gpio.h +++ b/src/soc/mediatek/mt8183/include/soc/gpio.h @@ -632,4 +632,17 @@ enum pull_select select); void gpio_set_mode(gpio_t gpio, int mode); +/* + * Firmware never enables interrupts on this platform. This function + * reads current EINT status and clears the pending interrupt. + * + * Returns 1 if the interrupt was pending, else 0. + */ +int gpio_eint_poll(gpio_t gpio); + +/* + * Configure a GPIO to handle external interrupts (EINT) of given irq type. + */ +void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib01b43cf1aa4082d7d968fe1ef82f75e8cf05b8b Gerrit-Change-Number: 29837 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2018