coreboot-gerrit November 2018

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Change in ...coreboot[master]: soc/intel/cannonlake: Delete unused macros in lpc.h
by Subrata Banik (Code Review) 26 Nov '18

26 Nov '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29836 Change subject: soc/intel/cannonlake: Delete unused macros in lpc.h ...................................................................... soc/intel/cannonlake: Delete unused macros in lpc.h TEST=Able to build and boot successfully. Change-Id: If013d8e59046152e9f1a026f48bd9cd9b43ab6af Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/include/soc/lpc.h 1 file changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29836/1 diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h index ea72675..260e03c 100644 --- a/src/soc/intel/cannonlake/include/soc/lpc.h +++ b/src/soc/intel/cannonlake/include/soc/lpc.h @@ -33,16 +33,6 @@ #define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ #define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ #define LPC_EN 0x82 /* LPC IF Enables Register */ -#define MC2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define SE_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC1_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* Floppy Drive Enable */ -#define LPT_LPC_EN (1 << 2) /* Parallel Port Enable */ -#define COMB_LPC_EN (1 << 1) /* Com Port B Enable */ -#define COMA_LPC_EN (1 << 0) /* Com Port A Enable */ #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If013d8e59046152e9f1a026f48bd9cd9b43ab6af Gerrit-Change-Number: 29836 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/icelake: Fix IO decode setup
by Subrata Banik (Code Review) 26 Nov '18

26 Nov '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29835 Change subject: soc/intel/icelake: Fix IO decode setup ...................................................................... soc/intel/icelake: Fix IO decode setup Make pch_early_iorange_init() function similar to soc/intel/cannonlake/bootblock/pch.c while fixing below issue: * COM1 not being enabled properly. TEST=Able to get serial output from an 8250IO UART device at the standard 0x3f8 base address. Change-Id: I5ab02f46d27e667be3d9328d94b634ef04038d2f Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/include/soc/lpc.h 2 files changed, 29 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29835/1 diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index c4f97b6..af24c10 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -44,6 +44,9 @@ #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) + #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC @@ -115,24 +118,38 @@ } } +static int pch_check_decode_enable(void) +{ + uint32_t dmi_control; + + /* + * This cycle decoding is only allowed to set when + * DMICTL.SRLOCK is 0. + */ + dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + if (dmi_control & PCR_DMI_DMICTL_SRLOCK) + return -1; + return 0; +} + void pch_early_iorange_init(void) { - uint16_t dec_rng, dec_en = 0; + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | + LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; /* IO Decode Range */ - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) && - IS_ENABLED(CONFIG_UART_DEBUG)) { - dec_rng = COMA_RANGE | (COMB_RANGE << 4); - dec_en = COMA_LPC_EN | COMB_LPC_EN; - pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, dec_rng); - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, dec_rng); - } + if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN | - LPC_IOE_KBC_60_64; - pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en); - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en); + if (pch_check_decode_enable() == 0) { + io_enables = lpc_enable_fixed_io_ranges(io_enables); + /* + * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same + * value program in LPC PCI offset 82h. + */ + pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + } /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/icelake/include/soc/lpc.h b/src/soc/intel/icelake/include/soc/lpc.h index dfcfa35..ebfcaa8 100644 --- a/src/soc/intel/icelake/include/soc/lpc.h +++ b/src/soc/intel/icelake/include/soc/lpc.h @@ -32,16 +32,6 @@ #define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ #define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ #define LPC_EN 0x82 /* LPC IF Enables Register */ -#define MC2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define SE_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC1_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* Floppy Drive Enable */ -#define LPT_LPC_EN (1 << 2) /* Parallel Port Enable */ -#define COMB_LPC_EN (1 << 1) /* Com Port B Enable */ -#define COMA_LPC_EN (1 << 0) /* Com Port A Enable */ #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ab02f46d27e667be3d9328d94b634ef04038d2f Gerrit-Change-Number: 29835 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/{commonlib, drivers/intel/fslp1_1/include}: Fix typo
by HAOUAS Elyes (Code Review) 26 Nov '18

26 Nov '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29831 ) Change subject: src/{commonlib,drivers/intel/fslp1_1/include}: Fix typo ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee6b8a8afc4d885d2d4ab9ee5d596e32e5e6d3f1 Gerrit-Change-Number: 29831 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 10:22:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell/northcluster.c: Reserve local APIC resources
by Frans Hendriks (Code Review) 26 Nov '18

26 Nov '18

Hello Patrick Rudolph, Hannah Williams, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29375 to look at the new patch set (#2). Change subject: soc/intel/braswell/northcluster.c: Reserve local APIC resources ...................................................................... soc/intel/braswell/northcluster.c: Reserve local APIC resources The resources of the local APIC are not reserved. Use mmio_resource() to add local APIC resources. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ieb9de45098d507d59f1974eddb7a94cb18ef7903 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/northcluster.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/29375/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb9de45098d507d59f1974eddb7a94cb18ef7903 Gerrit-Change-Number: 29375 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security/vboot: Add VB2_LIB to romstage sources without dependencies
by Werner Zeh (Code Review) 26 Nov '18

26 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29827 ) Change subject: security/vboot: Add VB2_LIB to romstage sources without dependencies ...................................................................... Patch Set 2: > Patch Set 2: > > I guess the main downside is that this creates another build of libvboot, no matter if it's used later-on or not. Reminds me that I wanted to look into deduplicating them ;-) Yes, we still have this issue open. But at least it helps getting Philipps measured-boot patch more stable for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/29827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8126c21b8fbe8dd65d95af49cbe2ad776b8ef605 Gerrit-Change-Number: 29827 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 09:56:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add VB2_LIB to romstage sources without dependencies
by Patrick Georgi (Code Review) 26 Nov '18

26 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29827 ) Change subject: security/vboot: Add VB2_LIB to romstage sources without dependencies ...................................................................... Patch Set 2: I guess the main downside is that this creates another build of libvboot, no matter if it's used later-on or not. Reminds me that I wanted to look into deduplicating them ;-) -- To view, visit https://review.coreboot.org/c/coreboot/+/29827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8126c21b8fbe8dd65d95af49cbe2ad776b8ef605 Gerrit-Change-Number: 29827 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 09:53:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/common: Fix style issue in spi.c
by Patrick Georgi (Code Review) 26 Nov '18

26 Nov '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29834 Change subject: sb/intel/common: Fix style issue in spi.c ...................................................................... sb/intel/common: Fix style issue in spi.c Change-Id: Ife8f7f164b26bea65a0dcde0cab339a1bb599e38 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/southbridge/intel/common/spi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/29834/1 diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 96b580e..0ab3606 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -344,7 +344,7 @@ cntlr->fpr_max = 5; if (cntlr->hsfs & HSFS_FDV) { - writel_ (4, &ich9_spi->fdoc); + writel_(4, &ich9_spi->fdoc); cntlr->flmap0 = readl_(&ich9_spi->fdod); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/29834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife8f7f164b26bea65a0dcde0cab339a1bb599e38 Gerrit-Change-Number: 29834 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/braswell/northcluster.c: Reserve local APIC resources
by Arthur Heymans (Code Review) 26 Nov '18

26 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29375 ) Change subject: src/soc/intel/braswell/northcluster.c: Reserve local APIC resources ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29375/1/src/soc/intel/braswell/northcluster… File src/soc/intel/braswell/northcluster.c: https://review.coreboot.org/#/c/29375/1/src/soc/intel/braswell/northcluster… PS1, Line 157: (0x00100000/1024) also use RES_IN_KIB ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb9de45098d507d59f1974eddb7a94cb18ef7903 Gerrit-Change-Number: 29375 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 26 Nov 2018 09:34:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/apl/acpi: Do not report 8259 PICs
by Nico Huber (Code Review) 26 Nov '18

26 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29833 Change subject: soc/intel/apl/acpi: Do not report 8259 PICs ...................................................................... soc/intel/apl/acpi: Do not report 8259 PICs The IRQ tables don't support this path, so we shouldn't report presence of the legacy PICs. As the _PIC method is optional and we ignore the passed parameter anyway, drop it. Change-Id: I51301a600e16f74fde00fdcb4595e1f47a52e207 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/acpi/platform.asl 2 files changed, 1 insertion(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/29833/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4a841be..6571892 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_NO_PCAT_8259 select ARCH_BOOTBLOCK_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 diff --git a/src/soc/intel/apollolake/acpi/platform.asl b/src/soc/intel/apollolake/acpi/platform.asl index ec1844a..f3202a0 100644 --- a/src/soc/intel/apollolake/acpi/platform.asl +++ b/src/soc/intel/apollolake/acpi/platform.asl @@ -18,19 +18,3 @@ /* Enable ACPI _SWS methods */ #include <soc/intel/common/acpi/acpi_wake_source.asl> #include <soc/intel/common/acpi/platform.asl> - -Name(\PICM, Zero) // IOAPIC/8259 - -/* - * The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method (_PIC, 1) -{ - /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) -} -- To view, visit https://review.coreboot.org/c/coreboot/+/29833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51301a600e16f74fde00fdcb4595e1f47a52e207 Gerrit-Change-Number: 29833 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: x86/acpi: Add Kconfig to toggle 8259 reporting
by Nico Huber (Code Review) 26 Nov '18

26 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29832 Change subject: x86/acpi: Add Kconfig to toggle 8259 reporting ...................................................................... x86/acpi: Add Kconfig to toggle 8259 reporting Change-Id: If3c9783ebc41c103c915788139d91644b805f397 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/arch/x86/Kconfig M src/arch/x86/acpi.c 2 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/29832/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 7c8371e..2a16caa 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -277,6 +277,14 @@ Note that it is the responsibility of the payload to reset the normal boot bit to 1 after each successsful boot. +config ACPI_NO_PCAT_8259 + bool + help + Selected by platforms that don't expose a PC/AT 8259 PIC pair. + +config ACPI_HAVE_PCAT_8259 + def_bool y if !ACPI_NO_PCAT_8259 + config ACPI_CPU_STRING string default "\\_PR.CP%02d" diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 3b33f1b..848b509 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -220,7 +220,8 @@ header->revision = get_acpi_table_revision(MADT); madt->lapic_addr = LOCAL_APIC_ADDR; - madt->flags = 0x1; /* PCAT_COMPAT */ + if (IS_ENABLED(CONFIG_ACPI_HAVE_PCAT_8259)) + madt->flags |= 1; current = acpi_fill_madt(current); -- To view, visit https://review.coreboot.org/c/coreboot/+/29832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3c9783ebc41c103c915788139d91644b805f397 Gerrit-Change-Number: 29832 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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coreboot-gerrit November 2018