Hello Richard Spiegel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29580
to look at the new patch set (#5).
Change subject: nb/amd/amdmct/{mct,mct_ddr3}: Replace "magic" numbers with macros
......................................................................
nb/amd/amdmct/{mct,mct_ddr3}: Replace "magic" numbers with macros
MTRR addresses are publicly available at cpu/x86/mtrr.h, so use
macros instead of "magic" numbers.
Change-Id: I224136ed4a19199bae0223a1aae366b3dd4ef9cf
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/northbridge/amd/amdmct/mct/mctmtr_d.c
M src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
2 files changed, 22 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29580/5
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Gerrit-Change-Id: I224136ed4a19199bae0223a1aae366b3dd4ef9cf
Gerrit-Change-Number: 29580
Gerrit-PatchSet: 5
Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr>
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Hello Werner Zeh, Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29840
to look at the new patch set (#12).
Change subject: security/vboot: Fix measured boot issues
......................................................................
security/vboot: Fix measured boot issues
* Remove legacy and never published google purin.
* Increase Tegra210 and Rockchip3228 SRAM for
romstage/verstage.
Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
---
D src/mainboard/google/purin/Kconfig
D src/mainboard/google/purin/Kconfig.name
D src/mainboard/google/purin/Makefile.inc
D src/mainboard/google/purin/board_info.txt
D src/mainboard/google/purin/boardid.c
D src/mainboard/google/purin/bootblock.c
D src/mainboard/google/purin/chromeos.c
D src/mainboard/google/purin/chromeos.fmd
D src/mainboard/google/purin/devicetree.cb
D src/mainboard/google/purin/mainboard.c
D src/mainboard/google/purin/memlayout.ld
D src/mainboard/google/purin/reset.c
M src/soc/nvidia/tegra210/include/soc/memlayout.ld
M src/soc/rockchip/rk3288/include/soc/memlayout.ld
14 files changed, 12 insertions(+), 308 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29840/12
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Hello Werner Zeh, Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29840
to look at the new patch set (#11).
Change subject: security/vboot: Fix measured boot issues
......................................................................
security/vboot: Fix measured boot issues
* Remove legacy and never published google purin.
* Increase Tegra210 and Rockchip3228 SRAM for
romstage/verstage.
* Add decompressor target for SPI/I2C TIS drivers.
* Add decompressor target for security/tpm.
Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
---
D src/mainboard/google/purin/Kconfig
D src/mainboard/google/purin/Kconfig.name
D src/mainboard/google/purin/Makefile.inc
D src/mainboard/google/purin/board_info.txt
D src/mainboard/google/purin/boardid.c
D src/mainboard/google/purin/bootblock.c
D src/mainboard/google/purin/chromeos.c
D src/mainboard/google/purin/chromeos.fmd
D src/mainboard/google/purin/devicetree.cb
D src/mainboard/google/purin/mainboard.c
D src/mainboard/google/purin/memlayout.ld
D src/mainboard/google/purin/reset.c
M src/soc/nvidia/tegra210/include/soc/memlayout.ld
M src/soc/rockchip/rk3288/include/soc/memlayout.ld
14 files changed, 12 insertions(+), 308 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29840/11
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29828 )
Change subject: Documentation/../../icelake_rvp: Add RVP coreboot development documentation
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/29828/2/Documentation/mainboard/intel/icela…
File Documentation/mainboard/intel/icelake_rvp.md:
https://review.coreboot.org/#/c/29828/2/Documentation/mainboard/intel/icela…
PS2, Line 17:
> https://review.coreboot. […]
I'm fine with that, but it's an extra step compared to these 3. To be honest, I disagree with the others that we need to explain this every. single. time.
Line 12 should be sufficient, as it explains the process: pick the board in Kconfig (by whatever means necessary), build, done. Maybe add "Following the instructions for Ice Lake, " before it so that the blobs thing is mentioned.
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29805 )
Change subject: Documentation/../../icelake: Add Ice Lake coreboot development documentation
......................................................................
Patch Set 5:
> Patch Set 3:
>
> > Please give more a detailed overview of the supported icelake
> > features and their requirements. Also please recommend to use
> > 3rdparty/fsp via kconfig instead of copying binaries into the tree.
>
> Philipp,
>
> Kindly consider the fact that ICL SOC development is still ongoing on and many such feature will be not in public as soc is not out in market for everyone's consumption. i have also mentioned a Intel public link for ICL, you may find more feature details if you have partner access. Kindly consider this case as we are up streaming ICL code almost same time SOC development is going on.
>
> Apart from that once product is out, i hope your FSP binary problem will also resolve as it will available in separate git like other program. And i know already a process been set to make use of that. Due to the fact that ICL FSP binaries are still not available externally for all so, we have to make use of copy stuff.
Got it. Then do a follow-up CL later on
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Gerrit-Comment-Date: Mon, 26 Nov 2018 16:16:56 +0000
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Hello Richard Spiegel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29580
to look at the new patch set (#4).
Change subject: nb/amd/amdmct/{mct,mct_ddr3}: Replace "magic" numbers with macros
......................................................................
nb/amd/amdmct/{mct,mct_ddr3}: Replace "magic" numbers with macros
MTRR addresses are publicly available at cpu/x86/mtrr.h, so use
macro instead of "magic" numbers.
Change-Id: I224136ed4a19199bae0223a1aae366b3dd4ef9cf
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/northbridge/amd/amdmct/mct/mctmtr_d.c
M src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
2 files changed, 22 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29580/4
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Gerrit-MessageType: newpatchset
Hello Richard Spiegel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29580
to look at the new patch set (#3).
Change subject: nb/amd/amdmct/{mct,mct_ddr3}: Replace "magic" numbers with macros.
......................................................................
nb/amd/amdmct/{mct,mct_ddr3}: Replace "magic" numbers with macros.
MTRR addresses are publicly available at cpu/x86/mtrr.h, so use
macro instead of "magic" numbers.
Change-Id: I224136ed4a19199bae0223a1aae366b3dd4ef9cf
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/northbridge/amd/amdmct/mct/mctmtr_d.c
M src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
2 files changed, 22 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29580/3
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29828 )
Change subject: Documentation/../../icelake_rvp: Add RVP coreboot development documentation
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/29828/2/Documentation/mainboard/intel/icela…
File Documentation/mainboard/intel/icelake_rvp.md:
https://review.coreboot.org/#/c/29828/2/Documentation/mainboard/intel/icela…
PS2, Line 17:
> "Note: Until the FSP binaries for this platform are released, you need to add them manually before b […]
https://review.coreboot.org/#/c/coreboot/+/29805/5/Documentation/soc/intel/…
line no:40?
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