coreboot-gerrit November 2018

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Change in ...coreboot[master]: mb/google/poppy/variants/nami: Enable g2touch touchscreen device
by Furquan Shaikh (Code Review) 27 Nov '18

27 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29768 ) Change subject: mb/google/poppy/variants/nami: Enable g2touch touchscreen device ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26e16b7e118121b3dd9a88c76d04898b97753df0 Gerrit-Change-Number: 29768 Gerrit-PatchSet: 2 Gerrit-Owner: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Nov 2018 02:34:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/poppy/variants/nami: Enable g2touch touchscreen device
by Crystal Lin (Code Review) 27 Nov '18

27 Nov '18

Hello Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29768 to look at the new patch set (#2). Change subject: mb/google/poppy/variants/nami: Enable g2touch touchscreen device ...................................................................... mb/google/poppy/variants/nami: Enable g2touch touchscreen device This change adds ACPI properties for GTCH7503 device. BUG=b:119169362 BRANCH=firmware-nami-10775.B TEST=Verify touchscreen works with this change Change-Id: I26e16b7e118121b3dd9a88c76d04898b97753df0 Signed-off-by: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29768/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26e16b7e118121b3dd9a88c76d04898b97753df0 Gerrit-Change-Number: 29768 Gerrit-PatchSet: 2 Gerrit-Owner: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cheza: Add board reset via Chrome EC
by Julius Werner (Code Review) 27 Nov '18

27 Nov '18

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29849 to look at the new patch set (#2). Change subject: cheza: Add board reset via Chrome EC ...................................................................... cheza: Add board reset via Chrome EC This patch implements board reset on the Cheza board. The real board reset used by the operating system uses the PMIC, but unfortunately the PMIC needs to be configured right for that to work. The PMIC configuration currently happens in the Qualcomm blob (QcLib) that is run from romstage, but vboot needs to be able to reboot during verstage already. Porting all the PMIC initialization code to run in the bootblock seems excessive (and at odds with the goal of doing as little as possible before verification), so we'll just do a little hack and ask the EC to perform a cold reset instead. For vboot purposes, this should work just as well. BUG=b:118501305 TEST=Hacked vboot code to call vboot_reboot(), confirmed that board reset and came back up as expected. Change-Id: I3858d95f481884a87c243d4fa3d6369c1e8a5a2c Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/cheza/Kconfig M src/mainboard/google/cheza/Makefile.inc A src/mainboard/google/cheza/reset.c 3 files changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29849/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3858d95f481884a87c243d4fa3d6369c1e8a5a2c Gerrit-Change-Number: 29849 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: vendorcode/cavium: Supply bdk_pop and bdk_dpop definitions
by Martin Roth (Code Review) 27 Nov '18

27 Nov '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29851 Change subject: vendorcode/cavium: Supply bdk_pop and bdk_dpop definitions ...................................................................... vendorcode/cavium: Supply bdk_pop and bdk_dpop definitions This is an issue found by the new builder image and needs to be fixed before we can upgrade to the new toolchain version: In function `bdk_dram_get_size_mbytes': src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-size.c:198: undefined reference to `bdk_pop' In function `bdk_get_num_cores': /src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-utils.h:164: undefined reference to `bdk_dpop' In function `init_octeon3_ddr3_interface': src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c:7550: undefined reference to `bdk_pop' Change-Id: Ibf71e4556014795bfedceccfe3837dc9deb29ad2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-size.c M src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c M src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-utils.h 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29851/1 diff --git a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-size.c b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-size.c index 8cd4594..eecb348 100644 --- a/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-size.c +++ b/src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-size.c @@ -37,6 +37,7 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include <bdk.h> +#include <bdk-coreboot.h> #include <libbdk-hal/bdk-utils.h> diff --git a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c index 0fcc180..3a6d5ab 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c @@ -37,6 +37,7 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include <bdk.h> +#include <bdk-coreboot.h> #include "libbdk-arch/bdk-csrs-l2c_tad.h" #include "libbdk-arch/bdk-csrs-mio_fus.h" #include "dram-internal.h" diff --git a/src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-utils.h b/src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-utils.h index c836586..a51ab6b 100644 --- a/src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-utils.h +++ b/src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-utils.h @@ -39,6 +39,7 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include "libbdk-arch/bdk-csrs-rst.h" +#include <bdk-coreboot.h> #include <string.h> /** -- To view, visit https://review.coreboot.org/c/coreboot/+/29851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf71e4556014795bfedceccfe3837dc9deb29ad2 Gerrit-Change-Number: 29851 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: romcc: Increase buffer size to fit max string size
by Martin Roth (Code Review) 27 Nov '18

27 Nov '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29850 Change subject: romcc: Increase buffer size to fit max string size ...................................................................... romcc: Increase buffer size to fit max string size On the updated builder image, the build is failing because the system compiler has been updated to GCC 8.2.0. It complains about the possibility of overflow when putting one 30 character buffer plus 2 characters into another 30 character buffer. To fix this, increase the recipient buffer size by 2. romcc.c:3645:2: note: 'sprintf' output between 3 and 32 bytes into a destination of size 30 [-Werror=format-overflow=] sprintf(buf, "\"%s\"", scratch); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ romcc.c:3649:2: note: 'sprintf' output between 3 and 32 bytes into a destination of size 30 [-Werror=format-overflow=] sprintf(buf, "\"%s\"", scratch); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Change-Id: I7879a7202cc3ff52301b10118fc49fcc601f133e Signed-off-by: Martin Roth <martinroth(a)google.com> --- M util/romcc/romcc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/29850/1 diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 307fcf8..4cb2aad 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -3629,7 +3629,7 @@ static void register_builtin_macros(struct compile_state *state) { - char buf[30]; + char buf[32]; char scratch[30]; time_t now; struct tm *tm; -- To view, visit https://review.coreboot.org/c/coreboot/+/29850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7879a7202cc3ff52301b10118fc49fcc601f133e Gerrit-Change-Number: 29850 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cheza: Add board reset via Chrome EC
by build bot (Jenkins) (Code Review) 27 Nov '18

27 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29849 ) Change subject: cheza: Add board reset via Chrome EC ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29849/1/src/mainboard/google/cheza/reset.c File src/mainboard/google/cheza/reset.c: https://review.coreboot.org/#/c/29849/1/src/mainboard/google/cheza/reset.c@… PS1, Line 21: void do_board_reset(void) { open brace '{' following function definitions go on the next line -- To view, visit https://review.coreboot.org/c/coreboot/+/29849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3858d95f481884a87c243d4fa3d6369c1e8a5a2c Gerrit-Change-Number: 29849 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Nov 2018 01:29:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cheza: Add board reset via Chrome EC
by Julius Werner (Code Review) 27 Nov '18

27 Nov '18

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29849 Change subject: cheza: Add board reset via Chrome EC ...................................................................... cheza: Add board reset via Chrome EC This patch implements board reset on the Cheza board. The real board reset used by the operating system uses the PMIC, but unfortunately the PMIC needs to be configured right for that to work. The PMIC configuration currently happens in the Qualcomm blob (QcLib) that is run from romstage, but vboot needs to be able to reboot during verstage already. Porting all the PMIC initialization code to run in the bootblock seems excessive (and at odds with the goal of doing as little as possible before verification), so we'll just do a little hack and ask the EC to perform a cold reset instead. For vboot purposes, this should work just as well. BUG=b:118501305 TEST=Hacked vboot code to call vboot_reboot(), confirmed that board reset and came back up as expected. Change-Id: I3858d95f481884a87c243d4fa3d6369c1e8a5a2c Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/cheza/Kconfig M src/mainboard/google/cheza/Makefile.inc A src/mainboard/google/cheza/reset.c 3 files changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29849/1 diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig index 828a1f7..392c9b1 100644 --- a/src/mainboard/google/cheza/Kconfig +++ b/src/mainboard/google/cheza/Kconfig @@ -16,7 +16,6 @@ select SPI_FLASH select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS - select MISSING_BOARD_RESET select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_SPI_TPM_CR50 diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/cheza/Makefile.inc index 1d339c3..7655e24 100644 --- a/src/mainboard/google/cheza/Makefile.inc +++ b/src/mainboard/google/cheza/Makefile.inc @@ -18,18 +18,22 @@ bootblock-y += chromeos.c bootblock-y += bootblock.c bootblock-y += qupv3_config.c +bootblock-y += reset.c verstage-y += boardid.c verstage-y += memlayout.ld verstage-y += chromeos.c +verstage-y += reset.c romstage-y += boardid.c romstage-y += memlayout.ld romstage-y += chromeos.c romstage-y += romstage.c +romstage-y += reset.c ramstage-y += boardid.c ramstage-y += memlayout.ld ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += qupv3_config.c +ramstage-y += reset.c diff --git a/src/mainboard/google/cheza/reset.c b/src/mainboard/google/cheza/reset.c new file mode 100644 index 0000000..0a835b5 --- /dev/null +++ b/src/mainboard/google/cheza/reset.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/google/chromeec/ec.h> +#include <reset.h> + +/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage), + but this works well enough for our purposes. */ +void do_board_reset(void) { + google_chromeec_reboot(0, EC_REBOOT_COLD, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3858d95f481884a87c243d4fa3d6369c1e8a5a2c Gerrit-Change-Number: 29849 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Remove duplicated round up function
by HAOUAS Elyes (Code Review) 26 Nov '18

26 Nov '18

Hello Patrick Rudolph, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29847 to look at the new patch set (#2). Change subject: src: Remove duplicated round up function ...................................................................... src: Remove duplicated round up function Fixes 7116ac8037 (src: Make use of 'CEIL_DIV(a, b)' macro across tree). Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/include/commonlib/helpers.h M src/cpu/allwinner/a10/clock.c M src/cpu/x86/tsc/delay_tsc.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/nvidia/tegra124/clock.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/clock.c M src/soc/samsung/exynos5420/cpu.c 10 files changed, 25 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29847/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Gerrit-Change-Number: 29847 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src: Remove duplicated round up function
by HAOUAS Elyes (Code Review) 26 Nov '18

26 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29847 Change subject: src: Remove duplicated round up function ...................................................................... src: Remove duplicated round up function Fixes 7116ac8037 (src: Make use of 'CEIL_DIV(a, b)' macro across tree). Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/include/commonlib/helpers.h M src/cpu/allwinner/a10/clock.c M src/cpu/x86/tsc/delay_tsc.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/nvidia/tegra124/clock.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/clock.c M src/soc/samsung/exynos5420/cpu.c 10 files changed, 25 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29847/1 diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index f2acedc..03f4306 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -36,7 +36,6 @@ #define MAX(a, b) ((a) > (b) ? (a) : (b)) #endif #define ABS(a) (((a) < 0) ? (-(a)) : (a)) -#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b)) #define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0) #define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) /* diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c index ae50e06..7ea5424 100644 --- a/src/cpu/allwinner/a10/clock.c +++ b/src/cpu/allwinner/a10/clock.c @@ -247,8 +247,8 @@ * will always be in spec, as long as AHB is in spec, although the max * AHB0 clock we can get is 125 MHz */ - axi = CEIL_DIV(actual_mhz, 450); /* Max 450 MHz */ - ahb = CEIL_DIV(actual_mhz/axi, 250); /* Max 250 MHz */ + axi = DIV_ROUND_UP(actual_mhz, 450); /* Max 450 MHz */ + ahb = DIV_ROUND_UP(actual_mhz/axi, 250); /* Max 250 MHz */ apb0 = 2; /* Max 150 MHz */ ahb_exp = log2_ceil(ahb); diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 04f709f..a589cdb 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -83,7 +83,7 @@ if (end.lo <= CALIBRATE_DIVISOR) goto bad_ctc; - return CEIL_DIV(end.lo, CALIBRATE_DIVISOR); + return DIV_ROUND_UP(end.lo, CALIBRATE_DIVISOR); } /* diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index d067dc2..ddf705f 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -361,8 +361,7 @@ } } -#define ROUNDUP_DIV(val, by) CEIL_DIV(val, by) -#define ROUNDUP_DIV_THIS(val, by) val = ROUNDUP_DIV(val, by) +#define ROUNDUP_DIV_THIS(val, by) (val = DIV_ROUND_UP(val, by)) static fsb_clock_t read_fsb_clock(void) { switch (MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) { diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index d0dfb75..54ef278 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -602,7 +602,7 @@ break; } } - min_cas_latency = CEIL_DIV(cas_latency_time, cycletime); + min_cas_latency = DIV_ROUND_UP(cas_latency_time, cycletime); cas_latency = 0; while (supported_cas_latencies) { cas_latency = find_highest_bit_set(supported_cas_latencies) + 3; @@ -3231,7 +3231,7 @@ static inline int div_roundup(int a, int b) { - return CEIL_DIV(a, b); + return DIV_ROUND_UP(a, b); } static unsigned lcm(unsigned a, unsigned b) diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index 1d05fa7..7acab31 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -572,7 +572,7 @@ printram("Selected DRAM frequency: %u MHz\n", val32); /* Find CAS and CWL latencies */ - val = CEIL_DIV(ctrl->tAA, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); printram("Minimum CAS latency : %uT\n", val); /* Find lowest supported CAS latency that satisfies the minimum value */ while (!((ctrl->cas_supported >> (val - 4)) & 1) @@ -591,30 +591,30 @@ pci_write_config8(MCU, 0xc0, reg8); /* Find tRCD */ - val = CEIL_DIV(ctrl->tRCD, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); printram("Selected tRCD : %uT\n", val); reg8 = ((val - 4) & 0x7) << 4; /* Find tRP */ - val = CEIL_DIV(ctrl->tRP, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); printram("Selected tRP : %uT\n", val); reg8 |= ((val - 4) & 0x7); pci_write_config8(MCU, 0xc1, reg8); /* Find tRAS */ - val = CEIL_DIV(ctrl->tRAS, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); printram("Selected tRAS : %uT\n", val); reg8 = ((val - 15) & 0x7) << 4; /* Find tWR */ - ctrl->WR = CEIL_DIV(ctrl->tWR, ctrl->tCK); + ctrl->WR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); printram("Selected tWR : %uT\n", ctrl->WR); reg8 |= ((ctrl->WR - 4) & 0x7); pci_write_config8(MCU, 0xc2, reg8); /* Find tFAW */ - tFAW = CEIL_DIV(ctrl->tFAW, ctrl->tCK); + tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); printram("Selected tFAW : %uT\n", tFAW); /* Find tRRD */ - tRRD = CEIL_DIV(ctrl->tRRD, ctrl->tCK); + tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); printram("Selected tRRD : %uT\n", tRRD); val = tFAW - 4 * tRRD; /* number of cycles above 4*tRRD */ reg8 = ((val - 0) & 0x7) << 4; @@ -622,11 +622,11 @@ pci_write_config8(MCU, 0xc3, reg8); /* Find tRTP */ - val = CEIL_DIV(ctrl->tRTP, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); printram("Selected tRTP : %uT\n", val); reg8 = ((val & 0x3) << 4); /* Find tWTR */ - val = CEIL_DIV(ctrl->tWTR, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); printram("Selected tWTR : %uT\n", val); reg8 |= ((val - 2) & 0x7); pci_mod_config8(MCU, 0xc4, 0x3f, reg8); @@ -639,7 +639,7 @@ * Since we previously set RxC4[7] */ reg8 = pci_read_config8(MCU, 0xc5); - val = CEIL_DIV(ctrl->tRFC, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); printram("Minimum tRFC : %uT\n", val); if (val < 30) { val = 0; @@ -652,7 +652,7 @@ pci_write_config8(MCU, 0xc5, reg8); /* Where does this go??? */ - val = CEIL_DIV(ctrl->tRC, ctrl->tCK); + val = DIV_ROUND_UP(ctrl->tRC, ctrl->tCK); printram("Required tRC : %uT\n", val); } diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 9173e62..b9a4cd1 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -247,17 +247,17 @@ 1 << 8); /* (rst) phy_divm */ write32(&clk_rst->utmip_pll_cfg1, - CEIL_DIV(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ + DIV_ROUND_UP(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ 0 << 16 | /* PLLU pwrdn */ 0 << 14 | /* pll_enable pwrdn */ 0 << 12 | /* pll_active pwrdn */ - CEIL_DIV(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */ + DIV_ROUND_UP(khz, 102) << 0); /* phy_stbl_cnt / 256 (2.5ms) */ /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ write32(&clk_rst->utmip_pll_cfg2, 0 << 24 | /* SAMP_D/XDEV pwrdn */ - CEIL_DIV(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ - CEIL_DIV(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ + DIV_ROUND_UP(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ + DIV_ROUND_UP(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ 0 << 4 | /* SAMP_C/USB3 pwrdn */ 0 << 2 | /* SAMP_B/XHOST pwrdn */ 0 << 0); /* SAMP_A/USBD pwrdn */ diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index aed1114..4fdb8f8 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -112,7 +112,7 @@ u32 lcdbase = get_fb_base_kb() * KiB; ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); - mmio_resource(dev, 1, lcdbase / KiB, CEIL_DIV(fb_size, KiB)); + mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB)); exynos_displayport_init(dev, lcdbase, fb_size); diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 04125d9..0da3522 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -345,7 +345,7 @@ } printk(BIOS_DEBUG, "%s(%d): sdclkin: %ld\n", __func__, device_index, sdclkin); - cclkin = CEIL_DIV(sdclkin, freq); + cclkin = DIV_ROUND_UP(sdclkin, freq); set_mmc_clk(device_index, cclkin); return 0; } diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index ecda54b..fa4cd06 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -114,7 +114,7 @@ dcache_clean_invalidate_by_mva((void *)lower, upper - lower); mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); - mmio_resource(dev, 1, lcdbase/KiB, CEIL_DIV(fb_size, KiB)); + mmio_resource(dev, 1, lcdbase/KiB, DIV_ROUND_UP(fb_size, KiB)); } static void tps65090_thru_ec_fet_disable(int index) @@ -134,7 +134,7 @@ u32 lcdbase = get_fb_base_kb() * KiB; ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); - mmio_resource(dev, 1, lcdbase / KiB, CEIL_DIV(fb_size, KiB)); + mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB)); /* * Disable LCD FETs before we do anything with the display. -- To view, visit https://review.coreboot.org/c/coreboot/+/29847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Gerrit-Change-Number: 29847 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by Philipp Deppenwiese (Code Review) 26 Nov '18

26 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 23: (6 comments) https://review.coreboot.org/#/c/29563/20/src/commonlib/include/commonlib/tc… File src/commonlib/include/commonlib/tcpa_log_serialized.h: https://review.coreboot.org/#/c/29563/20/src/commonlib/include/commonlib/tc… PS20, Line 21: #define MAX_TCPA_LOG_ENTRIES 50 > This is specific to coreboot proper's implementation and shouldn't necessarily be in here. Done https://review.coreboot.org/#/c/29563/20/src/commonlib/include/commonlib/tc… PS20, Line 26: struct tcpa_entry { > I don't see why this needs to be in the header since it's really dependent on the format string you […] Done https://review.coreboot.org/#/c/29563/20/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/20/src/include/memlayout.h@168 PS20, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ > Macros with multiple statements should be enclosed in a do - while loop Done https://review.coreboot.org/#/c/29563/20/src/include/memlayout.h@168 PS20, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ > macros should not use a trailing semicolon Done https://review.coreboot.org/#/c/29563/20/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/20/src/security/tpm/tspi/log.c@79 PS20, Line 79: memset(log_string, 0, sizeof(log_string)); > This needs to subtract j for proper length calculation. Done https://review.coreboot.org/#/c/29563/20/src/security/tpm/tspi/log.c@116 PS20, Line 116: EST_MAX_LENGT > MIN(digest_length, TCPA_DIGEST_MAX_LENGTH) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 23 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 21:45:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2018