coreboot-gerrit November 2018

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Change in ...coreboot[master]: security/vboot: Fix measured boot issues
by Julius Werner (Code Review) 26 Nov '18

26 Nov '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29840 ) Change subject: security/vboot: Fix measured boot issues ...................................................................... Patch Set 13: (3 comments) https://review.coreboot.org/#/c/29840/13//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29840/13//COMMIT_MSG@9 PS13, Line 9: * Remove legacy and never published google purin. Hmm... the reason we haven't done this before is that Purin is the only board that builds for MIPS architecture. It may have bitrotted a bit by now anyway, but at least it's still getting compiled. If we remove this, we may as well remove all of MIPS support because nothing will prevent it from rotting away. Is fixing Purin that hard? I don't even care whether the memory map makes sense for the board, actually, I'd just like to keep something for compile testing if possible. Just make it as big as it needs to be. (Long-term it would be great if we could get a MIPS QEMU target instead, but of course nobody has time for that.) If you do think we need to remove this, please also remove the Cygnus SoC with it. https://review.coreboot.org/#/c/29840/13//COMMIT_MSG@13 PS13, Line 13: AMD stoneyridge. Can you please make separate commits for each of these? Changes should be grouped in commits based on what they do, not why you need them. https://review.coreboot.org/#/c/29840/13/src/soc/rockchip/rk3288/include/so… File src/soc/rockchip/rk3288/include/soc/memlayout.ld: https://review.coreboot.org/#/c/29840/13/src/soc/rockchip/rk3288/include/so… PS13, Line 36: OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K) Are these changes needed even if you don't compile CONFIG_VBOOT_MEASURED_BOOT into those systems? Because I don't think your feature should increase code size when it's not enabled. If it does, maybe we can track down how and fix that. -- To view, visit https://review.coreboot.org/c/coreboot/+/29840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Gerrit-Change-Number: 29840 Gerrit-PatchSet: 13 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 21:31:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 26 Nov '18

26 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 23: (2 comments) https://review.coreboot.org/#/c/29563/23/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/23/src/include/memlayout.h@168 PS23, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/23/src/include/memlayout.h@168 PS23, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 23 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 21:30:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 26 Nov '18

26 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 22: (3 comments) https://review.coreboot.org/#/c/29563/22/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/22/src/include/memlayout.h@168 PS22, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/22/src/include/memlayout.h@168 PS22, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29563/22/src/security/tpm/tspi/log.c File src/security/tpm/tspi/log.c: https://review.coreboot.org/#/c/29563/22/src/security/tpm/tspi/log.c@124 PS22, Line 124: } void function return statements are not generally useful -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 22 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 21:28:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: payloads/libpayload/libcbfs: Remove duplicated '; ' at end of line
by HAOUAS Elyes (Code Review) 26 Nov '18

26 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29846 Change subject: payloads/libpayload/libcbfs: Remove duplicated ';' at end of line ...................................................................... payloads/libpayload/libcbfs: Remove duplicated ';' at end of line Change-Id: Id3750e839fc277e22387b78e938cc59bb3902697 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M payloads/libpayload/libcbfs/cbfs.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/29846/1 diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index f087eaa..577fb20 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -193,7 +193,7 @@ void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, struct cbfs_media *media, size_t offset, size_t count) { - void *address = buffer->buffer + buffer->allocated;; + void *address = buffer->buffer + buffer->allocated; DEBUG("simple_buffer_map(offset=%zu, count=%zu): " "allocated=%zu, size=%zu, last_allocate=%zu\n", offset, count, buffer->allocated, buffer->size, -- To view, visit https://review.coreboot.org/c/coreboot/+/29846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3750e839fc277e22387b78e938cc59bb3902697 Gerrit-Change-Number: 29846 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/{mainboard, southbridge}: Remove commented include lines
by HAOUAS Elyes (Code Review) 26 Nov '18

26 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29845 Change subject: src/{mainboard,southbridge}: Remove commented include lines ...................................................................... src/{mainboard,southbridge}: Remove commented include lines Change-Id: Ie06ae528ade3e06ae880b488628692ce43c30f5a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/bap/ode_e20XX/buildOpts.c M src/mainboard/gizmosphere/gizmo2/buildOpts.c M src/southbridge/amd/cimx/sb800/smbus.h M src/southbridge/amd/cimx/sb900/smbus.h M src/southbridge/amd/sb800/smbus.h 5 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29845/1 diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index 2f6143e..6c405cc 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -228,8 +228,6 @@ #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList -//#include "KeralaInstall.h" - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index 2f6143e..6c405cc 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -228,8 +228,6 @@ #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList -//#include "KeralaInstall.h" - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/southbridge/amd/cimx/sb800/smbus.h b/src/southbridge/amd/cimx/sb800/smbus.h index eb5bddf..82db12a 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.h +++ b/src/southbridge/amd/cimx/sb800/smbus.h @@ -16,8 +16,6 @@ #ifndef _SB800_SMBUS_H_ #define _SB800_SMBUS_H_ -//#include <stdint.h> - #define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS #define SMBHSTSTAT 0x0 diff --git a/src/southbridge/amd/cimx/sb900/smbus.h b/src/southbridge/amd/cimx/sb900/smbus.h index feaa397..9fc698e 100644 --- a/src/southbridge/amd/cimx/sb900/smbus.h +++ b/src/southbridge/amd/cimx/sb900/smbus.h @@ -16,8 +16,6 @@ #ifndef _SB900_SMBUS_H_ #define _SB900_SMBUS_H_ -//#include <stdint.h> - #define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS #define SMBHSTSTAT 0x0 diff --git a/src/southbridge/amd/sb800/smbus.h b/src/southbridge/amd/sb800/smbus.h index 5ac4ea6..0a7ca0e 100644 --- a/src/southbridge/amd/sb800/smbus.h +++ b/src/southbridge/amd/sb800/smbus.h @@ -16,8 +16,6 @@ #ifndef SB800_SMBUS_H #define SB800_SMBUS_H -//#include <stdint.h> - #define SMBHSTSTAT 0x0 #define SMBSLVSTAT 0x1 #define SMBHSTCTRL 0x2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie06ae528ade3e06ae880b488628692ce43c30f5a Gerrit-Change-Number: 29845 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/amd/sb800: Remove unused smbus_delay() function
by HAOUAS Elyes (Code Review) 26 Nov '18

26 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29843 Change subject: sb/amd/sb800: Remove unused smbus_delay() function ...................................................................... sb/amd/sb800: Remove unused smbus_delay() function Change-Id: I08ed67dd7159f8a407d61c9b5fc69ff6aef10057 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/sb800/smbus.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/29843/1 diff --git a/src/southbridge/amd/sb800/smbus.c b/src/southbridge/amd/sb800/smbus.c index aa4133b..0803b12 100644 --- a/src/southbridge/amd/sb800/smbus.c +++ b/src/southbridge/amd/sb800/smbus.c @@ -18,11 +18,6 @@ #include "smbus.h" -static inline void smbus_delay(void) -{ - outb(inb(0x80), 0x80); -} - static int smbus_wait_until_ready(u32 smbus_io_base) { u32 loops; -- To view, visit https://review.coreboot.org/c/coreboot/+/29843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08ed67dd7159f8a407d61c9b5fc69ff6aef10057 Gerrit-Change-Number: 29843 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 26 Nov '18

26 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 21: (2 comments) https://review.coreboot.org/#/c/29563/21/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/21/src/include/memlayout.h@168 PS21, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/21/src/include/memlayout.h@168 PS21, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 21 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 20:13:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/mb/pcengines/apu2/mainboard.c: Fix retrieving serial number
by Michał Żygowski (Code Review) 26 Nov '18

26 Nov '18

Hello Piotr Król, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29842 to look at the new patch set (#2). Change subject: src/mb/pcengines/apu2/mainboard.c: Fix retrieving serial number ...................................................................... src/mb/pcengines/apu2/mainboard.c: Fix retrieving serial number Handle situation when first NIC is not BDF 1:0.0. The PCI enumeration is different when a external PCIe device is connected to mPCIe2 slot which is routed to first PCIe bridge. The first NIC is then assigned BDF 2:0.0, because it is connected to the second PCIe bridge. Add a check for vendor ID and device ID of the NIC, before reading MAC address and calculating serial number. Change-Id: I9f89a6f3cd0c23a2d2924e587338f69c260b12f8 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/pcengines/apu2/mainboard.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/29842/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f89a6f3cd0c23a2d2924e587338f69c260b12f8 Gerrit-Change-Number: 29842 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/mb/pcengines/apu2/mainboard.c: Fix retrieving serial number
by Michał Żygowski (Code Review) 26 Nov '18

26 Nov '18

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29842 Change subject: src/mb/pcengines/apu2/mainboard.c: Fix retrieving serial number ...................................................................... src/mb/pcengines/apu2/mainboard.c: Fix retrieving serial number Handle situation when first NIC is not BDF 1:0.0. The PCI enumeration is different when a external PCIe device is connected to mPCIe2 slot which is routed to first PCIe bridge. The first NIC is then assigned BDF 2:0.0, because it is connected to the second PCIe bridge. Add a check for vendor ID and device ID of the NIC, before reading MAC address and calculating serial number. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I9f89a6f3cd0c23a2d2924e587338f69c260b12f8 --- M src/mainboard/pcengines/apu2/mainboard.c 1 file changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/29842/1 diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 35385c2..f54c4a0 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> +# #include <southbridge/amd/pi/hudson/hudson.h> #include <southbridge/amd/pi/hudson/pci_devs.h> #include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> @@ -197,11 +198,38 @@ struct device *nic_dev; uintptr_t bar10; u32 mac_addr = 0; + u16 vendor_id, device_id; int i; nic_dev = dev_find_slot(1, PCI_DEVFN(0, 0)); - if ((serial[0] != 0) || !nic_dev) - return serial; + /* + * Check if we really have found first NIC. In case we have PCIe module + * connected to mPCIe2 slot, BDF 1:0.0 may not be a NIC, because mPCIe2 + * slot is routed to the very first PCIe bridge and the first NIC is + * connected to the second PCIe bridge. + */ + if (!serial || !nic_dev) + return -1; + vendor_id = pci_read_config16(nic_dev, 0x0); + device_id = pci_read_config16(nic_dev, 0x2); + + /* + * apu boards have Intel NICs. If vendor ID does not match, it means + * that something is connected to mPCIe2 slot. Look on BDF 2:0.0. + */ + if (vendor_id != PCI_VENDOR_ID_INTEL) { + nic_dev = dev_find_slot(2, PCI_DEVFN(0, 0)); + if (!nic_dev) + return -1; + vendor_id = pci_read_config16(nic_dev, 0x0); + device_id = pci_read_config16(nic_dev, 0x2); + if (vendor_id != PCI_VENDOR_ID_INTEL) + return -1; + } + + /* Handle both hardware options: i210 and i211 NICs */ + if ((device_id != 0x1537) && (device_id != 0x157b)) + return -1; /* Read in the last 3 bytes of NIC's MAC address. */ bar10 = pci_read_config32(nic_dev, 0x10); -- To view, visit https://review.coreboot.org/c/coreboot/+/29842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f89a6f3cd0c23a2d2924e587338f69c260b12f8 Gerrit-Change-Number: 29842 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/vboot: Fix measured boot issues
by Philipp Deppenwiese (Code Review) 26 Nov '18

26 Nov '18

Hello Werner Zeh, Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29840 to look at the new patch set (#13). Change subject: security/vboot: Fix measured boot issues ...................................................................... security/vboot: Fix measured boot issues * Remove legacy and never published google purin. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add missing files for Intel apollolake and AMD stoneyridge. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- D src/mainboard/google/purin/Kconfig D src/mainboard/google/purin/Kconfig.name D src/mainboard/google/purin/Makefile.inc D src/mainboard/google/purin/board_info.txt D src/mainboard/google/purin/boardid.c D src/mainboard/google/purin/bootblock.c D src/mainboard/google/purin/chromeos.c D src/mainboard/google/purin/chromeos.fmd D src/mainboard/google/purin/devicetree.cb D src/mainboard/google/purin/mainboard.c D src/mainboard/google/purin/memlayout.ld D src/mainboard/google/purin/reset.c M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld 16 files changed, 14 insertions(+), 308 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29840/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/29840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Gerrit-Change-Number: 29840 Gerrit-PatchSet: 13 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2018