coreboot-gerrit November 2018

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Change in ...coreboot[master]: Documentation/../../dragonegg: Add dragonegg coreboot development doc...
by Patrick Georgi (Code Review) 26 Nov '18

26 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29829 ) Change subject: Documentation/../../dragonegg: Add dragonegg coreboot development documentation ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15e317557a0893d9f80cc9e87c6b90c85b93dcf Gerrit-Change-Number: 29829 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 15:43:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation/../../dragonegg: Add dragonegg coreboot development doc...
by Patrick Georgi (Code Review) 26 Nov '18

26 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29829 ) Change subject: Documentation/../../dragonegg: Add dragonegg coreboot development documentation ...................................................................... Patch Set 3: same thing about a comment on FSP availability. Not sure if it needs reiterating here, since it's also on the Ice Lake page, but if it's in the RVP instructions, it also belongs here. -- To view, visit https://review.coreboot.org/c/coreboot/+/29829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15e317557a0893d9f80cc9e87c6b90c85b93dcf Gerrit-Change-Number: 29829 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 15:43:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation/../../icelake_rvp: Add RVP coreboot development documen...
by Patrick Georgi (Code Review) 26 Nov '18

26 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29828 ) Change subject: Documentation/../../icelake_rvp: Add RVP coreboot development documentation ...................................................................... Patch Set 2: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/29828/2/Documentation/mainboard/intel/icela… File Documentation/mainboard/intel/icelake_rvp.md: https://review.coreboot.org/#/c/29828/2/Documentation/mainboard/intel/icela… PS2, Line 17: "Note: Until the FSP binaries for this platform are released, you need to add them manually before building."? -- To view, visit https://review.coreboot.org/c/coreboot/+/29828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If063cbd3436d9ee107945f425a31ba0009039a1d Gerrit-Change-Number: 29828 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 15:41:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/amd/amdmct/{mct, mct_ddr3}: Replace MTRR addresses with macros
by Richard Spiegel (Code Review) 26 Nov '18

26 Nov '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29580 ) Change subject: nb/amd/amdmct/{mct,mct_ddr3}: Replace MTRR addresses with macros ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29580/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29580/2//COMMIT_MSG@9 PS2, Line 9: Replace numbers by macro Replace "magic" numbers with macros. Also, normally the description should be longer then the title... add something else, maybe that the MTRR addresses are now publicly available? -- To view, visit https://review.coreboot.org/c/coreboot/+/29580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I224136ed4a19199bae0223a1aae366b3dd4ef9cf Gerrit-Change-Number: 29580 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 15:39:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/common: Fix style issue in spi.c
by Patrick Georgi (Code Review) 26 Nov '18

26 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29841 ) Change subject: sb/intel/common: Fix style issue in spi.c ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9e0e0c643f9b47cfe8bdfffbe247f477ace685 Gerrit-Change-Number: 29841 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 15:30:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Fix measured boot issues
by Philipp Deppenwiese (Code Review) 26 Nov '18

26 Nov '18

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29840 to look at the new patch set (#10). Change subject: security/vboot: Fix measured boot issues ...................................................................... security/vboot: Fix measured boot issues * Remove legacy and never published google purin. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add decompressor target for SPI/I2C TIS drivers. * Add decompressor target for security/tpm. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/drivers/i2c/tpm/Makefile.inc M src/drivers/spi/tpm/Makefile.inc D src/mainboard/google/purin/Kconfig D src/mainboard/google/purin/Kconfig.name D src/mainboard/google/purin/Makefile.inc D src/mainboard/google/purin/board_info.txt D src/mainboard/google/purin/boardid.c D src/mainboard/google/purin/bootblock.c D src/mainboard/google/purin/chromeos.c D src/mainboard/google/purin/chromeos.fmd D src/mainboard/google/purin/devicetree.cb D src/mainboard/google/purin/mainboard.c D src/mainboard/google/purin/memlayout.ld D src/mainboard/google/purin/reset.c M src/security/tpm/Makefile.inc M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld 17 files changed, 23 insertions(+), 308 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29840/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/29840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Gerrit-Change-Number: 29840 Gerrit-PatchSet: 10 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: sb/intel/common: Fix style issue in spi.c
by HAOUAS Elyes (Code Review) 26 Nov '18

26 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29841 to look at the new patch set (#2). Change subject: sb/intel/common: Fix style issue in spi.c ...................................................................... sb/intel/common: Fix style issue in spi.c Change-Id: I6b9e0e0c643f9b47cfe8bdfffbe247f477ace685 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/common/spi.c 1 file changed, 54 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/29841/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9e0e0c643f9b47cfe8bdfffbe247f477ace685 Gerrit-Change-Number: 29841 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security/vboot: Fix measured boot issues
by Philipp Deppenwiese (Code Review) 26 Nov '18

26 Nov '18

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29840 to look at the new patch set (#9). Change subject: security/vboot: Fix measured boot issues ...................................................................... security/vboot: Fix measured boot issues * Remove legacy and never published google purin. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add decompressor target for SPI/I2C TIS drivers. * Add decompressor target for security/tpm. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/drivers/i2c/tpm/Makefile.inc M src/drivers/spi/tpm/Makefile.inc D src/mainboard/google/purin/Kconfig D src/mainboard/google/purin/Kconfig.name D src/mainboard/google/purin/Makefile.inc D src/mainboard/google/purin/board_info.txt D src/mainboard/google/purin/boardid.c D src/mainboard/google/purin/bootblock.c D src/mainboard/google/purin/chromeos.c D src/mainboard/google/purin/chromeos.fmd D src/mainboard/google/purin/devicetree.cb D src/mainboard/google/purin/mainboard.c D src/mainboard/google/purin/memlayout.ld D src/mainboard/google/purin/reset.c M src/security/tpm/Makefile.inc M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/rockchip/rk3288/include/soc/memlayout.ld 17 files changed, 23 insertions(+), 308 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29840/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/29840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Gerrit-Change-Number: 29840 Gerrit-PatchSet: 9 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: sb/intel/common: Fix style issue in spi.c
by HAOUAS Elyes (Code Review) 26 Nov '18

26 Nov '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29841 ) Change subject: sb/intel/common: Fix style issue in spi.c ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29841/1/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c: https://review.coreboot.org/#/c/29841/1/src/southbridge/intel/common/spi.c@… PS1, Line 445: else { I think , 'esle' is not needed as we have a 'return' just before. -- To view, visit https://review.coreboot.org/c/coreboot/+/29841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9e0e0c643f9b47cfe8bdfffbe247f477ace685 Gerrit-Change-Number: 29841 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 26 Nov 2018 15:00:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/common: Fix style issue in spi.c
by HAOUAS Elyes (Code Review) 26 Nov '18

26 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29841 Change subject: sb/intel/common: Fix style issue in spi.c ...................................................................... sb/intel/common: Fix style issue in spi.c Change-Id: I6b9e0e0c643f9b47cfe8bdfffbe247f477ace685 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/common/spi.c 1 file changed, 18 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/29841/1 diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 0592379..ec84611 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -196,6 +196,7 @@ static u8 readb_(const void *addr) { u8 v = read8(addr); + printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -204,6 +205,7 @@ static u16 readw_(const void *addr) { u16 v = read16(addr); + printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -212,6 +214,7 @@ static u32 readl_(const void *addr) { u32 v = read32(addr); + printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -347,7 +350,7 @@ if (cntlr->hsfs & HSFS_FDV) { writel_(4, &ich9_spi->fdoc); cntlr->flmap0 = readl_(&ich9_spi->fdod); - writel_ (0x1000, &ich9_spi->fdoc); + writel_(0x1000, &ich9_spi->fdoc); cntlr->flcomp = readl_(&ich9_spi->fdod); } } @@ -526,7 +529,7 @@ return -1; } -static int spi_is_multichip (void) +static int spi_is_multichip(void) { ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); if (!(cntlr->hsfs & HSFS_FDV)) @@ -689,6 +692,7 @@ { ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF; + writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr); } @@ -773,8 +777,7 @@ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ writew_(hsfc, &cntlr->ich9_spi->hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, len)) - { + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) { printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); ret = -1; goto out; @@ -811,7 +814,7 @@ uint8_t block_len; if (addr + len > flash->size) { - printk (BIOS_ERR, + printk(BIOS_ERR, "Attempt to read %x-%x which is out of chip\n", (unsigned) addr, (unsigned) addr+(unsigned) len); @@ -882,7 +885,7 @@ uint32_t start = addr; if (addr + len > flash->size) { - printk (BIOS_ERR, + printk(BIOS_ERR, "Attempt to write 0x%x-0x%x which is out of chip\n", (unsigned)addr, (unsigned) (addr+len)); return -1; @@ -908,9 +911,8 @@ hsfc |= HSFC_FGO; /* start */ writew_(hsfc, &cntlr->ich9_spi->hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) - { - printk (BIOS_ERR, "SF: write failure at %x\n", + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) { + printk(BIOS_ERR, "SF: write failure at %x\n", addr); return -1; } @@ -944,9 +946,8 @@ memcpy(&flash->spi, spi, sizeof(*spi)); flash->name = "Opaque HW-sequencing"; - ich_hwseq_set_addr (0); - switch ((cntlr->hsfs >> 3) & 3) - { + ich_hwseq_set_addr(0); + switch ((cntlr->hsfs >> 3) & 3) { case 0: flash->sector_size = 256; break; @@ -967,7 +968,7 @@ if ((cntlr->hsfs & HSFS_FDV) && ((cntlr->flmap0 >> 8) & 3)) flash->size += 1 << (19 + ((cntlr->flcomp >> 3) & 7)); - printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); + printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); return 0; } @@ -978,19 +979,20 @@ return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); } -#define SPI_FPR_SHIFT 12 +#define SPI_FPR_SHIFT 12 #define ICH7_SPI_FPR_MASK 0xfff #define ICH9_SPI_FPR_MASK 0x1fff -#define SPI_FPR_BASE_SHIFT 0 +#define SPI_FPR_BASE_SHIFT 0 #define ICH7_SPI_FPR_LIMIT_SHIFT 12 #define ICH9_SPI_FPR_LIMIT_SHIFT 16 #define ICH9_SPI_FPR_RPE (1 << 15) /* Read Protect */ -#define SPI_FPR_WPE (1 << 31) /* Write Protect */ +#define SPI_FPR_WPE (1 << 31) /* Write Protect */ static u32 spi_fpr(u32 base, u32 limit) { u32 ret; u32 mask, limit_shift; + if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) { mask = ICH7_SPI_FPR_MASK; limit_shift = ICH7_SPI_FPR_LIMIT_SHIFT; -- To view, visit https://review.coreboot.org/c/coreboot/+/29841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9e0e0c643f9b47cfe8bdfffbe247f477ace685 Gerrit-Change-Number: 29841 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit November 2018