coreboot-gerrit November 2018

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Change in ...coreboot[master]: smmstore: update smm store filename to use an underscore
by Joel Kitching (Code Review) 27 Nov '18

27 Nov '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29854 Change subject: smmstore: update smm store filename to use an underscore ...................................................................... smmstore: update smm store filename to use an underscore Rename "smm store" to "smm_store". BUG=b:120060878 TEST=None Signed-off-by: Joel Kitching <kitching(a)google.com> Change-Id: If70772e17cc1668a28b376eeccfde0424e637b1a --- M src/drivers/smmstore/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29854/1 diff --git a/src/drivers/smmstore/Kconfig b/src/drivers/smmstore/Kconfig index 4bb48f7..d7063df 100644 --- a/src/drivers/smmstore/Kconfig +++ b/src/drivers/smmstore/Kconfig @@ -27,6 +27,6 @@ config SMMSTORE_FILENAME string "SMM store file name" - default "smm store" + default "smm_store" endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If70772e17cc1668a28b376eeccfde0424e637b1a Gerrit-Change-Number: 29854 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation/../../dragonegg: Add dragonegg coreboot development doc...
by Patrick Georgi (Code Review) 27 Nov '18

27 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29829 ) Change subject: Documentation/../../dragonegg: Add dragonegg coreboot development documentation ...................................................................... Documentation/../../dragonegg: Add dragonegg coreboot development documentation Change-Id: Ia15e317557a0893d9f80cc9e87c6b90c85b93dcf Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/29829 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- A Documentation/mainboard/google/dragonegg.md M Documentation/mainboard/index.md 2 files changed, 44 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/Documentation/mainboard/google/dragonegg.md b/Documentation/mainboard/google/dragonegg.md new file mode 100644 index 0000000..df4fe16 --- /dev/null +++ b/Documentation/mainboard/google/dragonegg.md @@ -0,0 +1,40 @@ +# Google Dragonegg (Chromebook) + +This page describes how to run coreboot on the google dragonegg board. + +Dragonegg is based on Intel Ice Lake platform, please refer to below link to get more details +```eval_rst +:doc:`../../soc/intel/iceLake_coreboot_development.md` +``` + +## Building coreboot + +* Follow build instructions mentioned in Ice Lake document +```eval_rst +:doc:`../../soc/intel/iceLake_coreboot_development.md` +``` + +* The default options for this board should result in a fully working image: +```bash + # echo "CONFIG_VENDOR_GOOGLE=y" > .config + # echo "CONFIG_BOARD_GOOGLE_DRAGONEGG=y" >> .config + # make olddefconfig && make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Size | 32 MiB | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ +``` diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 0b47168..128f0c1 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -33,6 +33,10 @@ - [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md) +## Google + +- [Dragonegg](google/dragonegg.md) + ## Open Cellular - [Elgon](opencellular/elgon.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/29829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15e317557a0893d9f80cc9e87c6b90c85b93dcf Gerrit-Change-Number: 29829 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Documentation/../../dragonegg: Add dragonegg coreboot development doc...
by Patrick Georgi (Code Review) 27 Nov '18

27 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29829 ) Change subject: Documentation/../../dragonegg: Add dragonegg coreboot development documentation ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15e317557a0893d9f80cc9e87c6b90c85b93dcf Gerrit-Change-Number: 29829 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Nov 2018 08:57:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation/../../icelake_rvp: Add RVP coreboot development documen...
by Patrick Georgi (Code Review) 27 Nov '18

27 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29828 ) Change subject: Documentation/../../icelake_rvp: Add RVP coreboot development documentation ...................................................................... Documentation/../../icelake_rvp: Add RVP coreboot development documentation Change-Id: If063cbd3436d9ee107945f425a31ba0009039a1d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/29828 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/intel/icelake_rvp.md 2 files changed, 41 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 15c2ede..0b47168 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -23,6 +23,7 @@ ## Intel - [DG43GT](intel/dg43gt.md) +- [IceLake RVP](intel/icelake_rvp.md) ## Foxconn diff --git a/Documentation/mainboard/intel/icelake_rvp.md b/Documentation/mainboard/intel/icelake_rvp.md new file mode 100644 index 0000000..09f2185 --- /dev/null +++ b/Documentation/mainboard/intel/icelake_rvp.md @@ -0,0 +1,40 @@ +# Intel Ice Lake RVP (Reference Validation Platform) + +This page describes how to run coreboot on the Intel icelake_rvp board. + +Ice Lake RVP is based on Intel Ice Lake platform, please refer to below link to get more details +```eval_rst +:doc:`../../soc/intel/iceLake_coreboot_development.md` +``` + +## Building coreboot + +* Follow build instructions mentioned in Ice Lake document +```eval_rst +:doc:`../../soc/intel/iceLake_coreboot_development.md` +``` + +* The default options for this board should result in a fully working image: +```bash + # echo "CONFIG_VENDOR_INTEL=y" > .config + # echo "CONFIG_BOARD_INTEL_ICELAKE_RVPU=y" >> .config + # make olddefconfig && make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Size | 32 MiB | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ +``` -- To view, visit https://review.coreboot.org/c/coreboot/+/29828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If063cbd3436d9ee107945f425a31ba0009039a1d Gerrit-Change-Number: 29828 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Documentation/../../icelake_rvp: Add RVP coreboot development documen...
by Patrick Georgi (Code Review) 27 Nov '18

27 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29828 ) Change subject: Documentation/../../icelake_rvp: Add RVP coreboot development documentation ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If063cbd3436d9ee107945f425a31ba0009039a1d Gerrit-Change-Number: 29828 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Nov 2018 08:56:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/poppy/variants/nami: Enable g2touch touchscreen device
by Patrick Georgi (Code Review) 27 Nov '18

27 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29768 ) Change subject: mb/google/poppy/variants/nami: Enable g2touch touchscreen device ...................................................................... mb/google/poppy/variants/nami: Enable g2touch touchscreen device This change adds ACPI properties for GTCH7503 device. BUG=b:119169362 BRANCH=firmware-nami-10775.B TEST=Verify touchscreen works with this change Change-Id: I26e16b7e118121b3dd9a88c76d04898b97753df0 Signed-off-by: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29768 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 49e35b2..edf7ed6 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -346,6 +346,20 @@ register "hid_desc_reg_offset" = "0x20" device i2c 20 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # I2C #0 device pci 15.1 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/29768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26e16b7e118121b3dd9a88c76d04898b97753df0 Gerrit-Change-Number: 29768 Gerrit-PatchSet: 3 Gerrit-Owner: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: nb/amd/amdmct/{mct, mct_ddr3}: Replace "magic" numbers with macros
by Patrick Georgi (Code Review) 27 Nov '18

27 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29580 ) Change subject: nb/amd/amdmct/{mct,mct_ddr3}: Replace "magic" numbers with macros ...................................................................... nb/amd/amdmct/{mct,mct_ddr3}: Replace "magic" numbers with macros MTRR addresses are publicly available at cpu/x86/mtrr.h, so use macros instead of "magic" numbers. Change-Id: I224136ed4a19199bae0223a1aae366b3dd4ef9cf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/29580 Reviewed-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/amd/amdmct/mct/mctmtr_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c 2 files changed, 22 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Richard Spiegel: Looks good to me, approved diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c index 1e47ab4..883ab65 100644 --- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ - #include "mct_d.h" #include <cpu/amd/mtrr.h> +#include <cpu/x86/mtrr.h> static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr); static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType); @@ -67,11 +67,11 @@ /* NOTE : For coreboot, we don't need to set mtrr enables here because they are still enable from cache_as_ram.inc */ - addr = 0x250; + addr = MTRR_FIX_64K_00000; lo = 0x1E1E1E1E; hi = lo; _WRMSR(addr, lo, hi); /* 0 - 512K = WB Mem */ - addr = 0x258; + addr = MTRR_FIX_16K_80000; _WRMSR(addr, lo, hi); /* 512K - 640K = WB Mem */ /*====================================================================== @@ -81,7 +81,7 @@ 0x200, 0x201 for [1M, CONFIG_TOP_MEM) 0x202, 0x203 for ROM Caching */ - addr = 0x204; /* MTRR phys base 2*/ + addr = MTRR_PHYS_BASE(2); /* MTRR phys base 2*/ /* use TOP_MEM as limit*/ /* Limit = TOP_MEM|TOM2*/ /* Base = 0*/ @@ -112,14 +112,14 @@ addr += 3; /* TOM2 */ _WRMSR(addr, lo, hi); } - addr = 0xC0010010; /* SYS_CFG */ + addr = SYSCFG_MSR; /* SYS_CFG */ _RDMSR(addr, &lo, &hi); if (Bottom40bIO) { - lo |= (1<<21); /* MtrrTom2En = 1 */ - lo |= (1<<22); /* Tom2ForceMemTypeWB */ + lo |= SYSCFG_MSR_TOM2En; /* MtrrTom2En = 1 */ + lo |= SYSCFG_MSR_TOM2WB; /* Tom2ForceMemTypeWB */ } else { - lo &= ~(1<<21); /* MtrrTom2En = 0 */ - lo &= ~(1<<22); /* Tom2ForceMemTypeWB */ + lo &= ~SYSCFG_MSR_TOM2En; /* MtrrTom2En = 0 */ + lo &= ~SYSCFG_MSR_TOM2WB; /* Tom2ForceMemTypeWB */ } _WRMSR(addr, lo, hi); } @@ -235,10 +235,10 @@ /*====================================================================== * Clear variable MTRR values *======================================================================*/ - addr = 0x200; + addr = MTRR_PHYS_BASE(0); lo = 0; hi = lo; - while (addr < 0x20C) { + while (addr < MTRR_PHYS_BASE(6)) { _WRMSR(addr, lo, hi); /* prog. MTRR with current region Mask */ addr++; /* next MTRR pair addr */ } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c index 2bf8562..4836757 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c @@ -20,6 +20,7 @@ #include "mct_d.h" #include "mct_d_gcc.h" #include <cpu/amd/mtrr.h> +#include <cpu/x86/mtrr.h> static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr); static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType); @@ -71,11 +72,11 @@ /* NOTE : For coreboot, we don't need to set mtrr enables here because they are still enable from cache_as_ram.inc */ - addr = 0x250; + addr = MTRR_FIX_64K_00000; lo = 0x1E1E1E1E; hi = lo; _WRMSR(addr, lo, hi); /* 0 - 512K = WB Mem */ - addr = 0x258; + addr = MTRR_FIX_16K_80000; _WRMSR(addr, lo, hi); /* 512K - 640K = WB Mem */ /*====================================================================== @@ -85,7 +86,7 @@ 0x200, 0x201 for [1M, CONFIG_TOP_MEM) 0x202, 0x203 for ROM Caching */ - addr = 0x204; /* MTRR phys base 2*/ + addr = MTRR_PHYS_BASE(2); /* MTRR phys base 2*/ /* use TOP_MEM as limit*/ /* Limit = TOP_MEM|TOM2*/ /* Base = 0*/ @@ -114,14 +115,14 @@ addr += 3; /* TOM2 */ _WRMSR(addr, lo, hi); } - addr = 0xC0010010; /* SYS_CFG */ + addr = SYSCFG_MSR; /* SYS_CFG */ _RDMSR(addr, &lo, &hi); if (Bottom40bIO) { - lo |= (1<<21); /* MtrrTom2En = 1 */ - lo |= (1<<22); /* Tom2ForceMemTypeWB */ + lo |= SYSCFG_MSR_TOM2En; /* MtrrTom2En = 1 */ + lo |= SYSCFG_MSR_TOM2WB; /* Tom2ForceMemTypeWB */ } else { - lo &= ~(1<<21); /* MtrrTom2En = 0 */ - lo &= ~(1<<22); /* Tom2ForceMemTypeWB */ + lo &= ~SYSCFG_MSR_TOM2En; /* MtrrTom2En = 0 */ + lo &= ~SYSCFG_MSR_TOM2WB; /* Tom2ForceMemTypeWB */ } _WRMSR(addr, lo, hi); } @@ -236,10 +237,10 @@ /*====================================================================== * Clear variable MTRR values *======================================================================*/ - addr = 0x200; + addr = MTRR_PHYS_BASE(0); lo = 0; hi = lo; - while (addr < 0x20C) { + while (addr < MTRR_PHYS_BASE(6)) { _WRMSR(addr, lo, hi); /* prog. MTRR with current region Mask */ addr++; /* next MTRR pair addr */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/29580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I224136ed4a19199bae0223a1aae366b3dd4ef9cf Gerrit-Change-Number: 29580 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: src/{commonlib, drivers/intel/fslp1_1/include}: Fix typo
by Patrick Georgi (Code Review) 27 Nov '18

27 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29831 ) Change subject: src/{commonlib,drivers/intel/fslp1_1/include}: Fix typo ...................................................................... src/{commonlib,drivers/intel/fslp1_1/include}: Fix typo Correct typo of 'compilation' BUG=N/A TEST=N/A Change-Id: Iee6b8a8afc4d885d2d4ab9ee5d596e32e5e6d3f1 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/29831 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/commonlib/fsp_relocate.c M src/drivers/intel/fsp1_1/include/fsp/api.h M src/drivers/intel/fsp1_1/include/fsp/soc_binding.h M src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h 4 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index fe58a29..32e6b6d 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -19,7 +19,7 @@ /* * Intel's code does not have a handle on changing global packing state. * Therefore, one needs to protect against packing policies that are set - * globally for a compliation unit just by including a header file. + * globally for a compilation unit just by including a header file. */ #pragma pack(push) diff --git a/src/drivers/intel/fsp1_1/include/fsp/api.h b/src/drivers/intel/fsp1_1/include/fsp/api.h index 773b3c3..103b406 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/api.h +++ b/src/drivers/intel/fsp1_1/include/fsp/api.h @@ -22,7 +22,7 @@ /* * Intel's code does not have a handle on changing global packing state. * Therefore, one needs to protect against packing policies that are set - * globally for a compliation unit just by including a header file. + * globally for a compilation unit just by including a header file. */ #pragma pack(push) diff --git a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h index affb43f..ab1270d 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp1_1/include/fsp/soc_binding.h @@ -22,7 +22,7 @@ /* * Intel's code does not have a handle on changing global packing state. * Therefore, one needs to protect against packing policies that are set - * globally for a compliation unit just by including a header file. + * globally for a compilation unit just by including a header file. */ #pragma pack(push) diff --git a/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h index ad5bd36..2352d0a 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h +++ b/src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h @@ -19,7 +19,7 @@ /* * Intel's code does not have a handle on changing global packing state. * Therefore, one needs to protect against packing policies that are set - * globally for a compliation unit just by including a header file. + * globally for a compilation unit just by including a header file. */ #pragma pack(push) -- To view, visit https://review.coreboot.org/c/coreboot/+/29831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee6b8a8afc4d885d2d4ab9ee5d596e32e5e6d3f1 Gerrit-Change-Number: 29831 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: {mb, nb, soc/fsp_baytrail}: Get rid of dump_mem()
by HAOUAS Elyes (Code Review) 27 Nov '18

27 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29853 Change subject: {mb,nb,soc/fsp_baytrail}: Get rid of dump_mem() ...................................................................... {mb,nb,soc/fsp_baytrail}: Get rid of dump_mem() Use hexdump() instead of dump_mem(). Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/northbridge/amd/amdfam10/debug.c M src/northbridge/amd/amdfam10/debug.h M src/northbridge/intel/e7505/debug.c M src/northbridge/intel/e7505/debug.h M src/northbridge/intel/fsp_rangeley/northbridge.h M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/nehalem/nehalem.h M src/northbridge/intel/sandybridge/sandybridge.h M src/soc/intel/fsp_baytrail/include/soc/baytrail.h 20 files changed, 0 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29853/1 diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 39ff7a0..180fa5d 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -102,8 +102,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 96d80cc..4860787 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -102,8 +102,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 8eb9226..f8e2e32 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -103,8 +103,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index bb43dd5..9eec8c0 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -106,8 +106,6 @@ console_init(); printk(BIOS_DEBUG, "\n"); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 098baac..9255b01 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -98,8 +98,6 @@ it8718f_disable_reboot(GPIO_DEV); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 05d2e04..cd7ff1e 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -98,8 +98,6 @@ it8718f_disable_reboot(GPIO_DEV); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index fc1b32f..46da224 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -100,8 +100,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index f75c5a4..f738341 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -105,8 +105,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 3eeaeda..62f5f8d 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -112,8 +112,6 @@ console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index 067c299..55a00e1 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -299,19 +299,6 @@ } } -void dump_mem(u32 start, u32 end) -{ - u32 i; - printk(BIOS_DEBUG, "dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%08x:", i); - } - printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); - } - printk(BIOS_DEBUG, "\n"); -} - #if IS_ENABLED(CONFIG_DIMM_DDR2) void print_tx(const char *strval, u32 val) { diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h index a4ecfe9..a23303e 100644 --- a/src/northbridge/amd/amdfam10/debug.h +++ b/src/northbridge/amd/amdfam10/debug.h @@ -38,7 +38,6 @@ #endif void dump_io_resources(u32 port); -void dump_mem(u32 start, u32 end); void print_tx(const char *strval, u32 val); void print_t(const char *strval); diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index f3a27e2..c21e321 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -183,15 +183,3 @@ port++; } } - -void dump_mem(unsigned start, unsigned end) -{ - unsigned i; - printk(BIOS_DEBUG, "dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf)==0) - printk(BIOS_DEBUG, "\n%08x:", i); - printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); - } - printk(BIOS_DEBUG, "\n"); -} diff --git a/src/northbridge/intel/e7505/debug.h b/src/northbridge/intel/e7505/debug.h index 238c500..98ca848 100644 --- a/src/northbridge/intel/e7505/debug.h +++ b/src/northbridge/intel/e7505/debug.h @@ -22,6 +22,5 @@ void dump_spd_registers(const struct mem_controller *ctrl); void dump_smbus_registers(void); void dump_io_resources(unsigned port); -void dump_mem(unsigned start, unsigned end); #endif diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index f68d175..11089a5 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -69,7 +69,6 @@ void dump_pci_device(unsigned dev); void dump_pci_devices(void); void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #ifndef __SIMPLE_DEVICE__ diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 33818ee..574a7f8 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -222,7 +222,6 @@ void dump_pci_device(unsigned dev); void dump_pci_devices(void); void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index ef4f17b..c52f2a6 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -96,15 +96,3 @@ printk(BIOS_DEBUG, "\n"); } } - -void dump_mem(unsigned int start, unsigned int end) -{ - unsigned int i; - printk(BIOS_DEBUG, "dump_mem:"); - for (i = start; i < end; i++) { - if ((i & 0xf) == 0) - printk(BIOS_DEBUG, "\n%08x:", i); - printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); - } - printk(BIOS_DEBUG, "\n"); -} diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 65a40e7..757eb52 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -379,7 +379,6 @@ void dump_pci_device(unsigned int dev); void dump_pci_devices(void); void dump_spd_registers(void); -void dump_mem(unsigned int start, unsigned int end); u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc); diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 5756c90..b0e8490 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -277,7 +277,6 @@ void dump_pci_device(unsigned dev); void dump_pci_devices(void); void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index faa9cd90..9e3da4b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -219,7 +219,6 @@ void dump_pci_device(unsigned dev); void dump_pci_devices(void); void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); #endif /* !__SMM__ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h index 82fd0a1..68bdd12 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h @@ -63,7 +63,6 @@ void dump_pci_device(unsigned dev); void dump_pci_devices(void); void dump_spd_registers(void); -void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* __PRE_RAM__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f Gerrit-Change-Number: 29853 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/braswell/include/soc/irq.h: Change PIRQ_PIC_IRQDISABLE ...
by Patrick Rudolph (Code Review) 27 Nov '18

27 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29393 ) Change subject: src/soc/intel/braswell/include/soc/irq.h: Change PIRQ_PIC_IRQDISABLE value ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514 Gerrit-Change-Number: 29393 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Nov 2018 08:34:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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