coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

1 participants
1699 discussions

Change in ...coreboot[master]: cpu/intel/fit: Make FIT microcode updates selectable
by Arthur Heymans (Code Review) 27 Nov '18

27 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29863 ) Change subject: cpu/intel/fit: Make FIT microcode updates selectable ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29863/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29863/2//COMMIT_MSG@7 PS2, Line 7: Make FIT microcode updates selectable What is the rationale behind this? -- To view, visit https://review.coreboot.org/c/coreboot/+/29863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7da926943aef89e49e98d0b990ab46f5f8200e6e Gerrit-Change-Number: 29863 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 27 Nov 2018 14:45:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: nb/intel/gm45: Correctly cache TSEG
by Nico Huber (Code Review) 27 Nov '18

27 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29866 ) Change subject: nb/intel/gm45: Correctly cache TSEG ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Gerrit-Change-Number: 29866 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Nov 2018 14:05:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: nb/intel/gm45: Correctly cache TSEG
by Arthur Heymans (Code Review) 27 Nov '18

27 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29866 to look at the new patch set (#4). Change subject: nb/intel/gm45: Correctly cache TSEG ...................................................................... nb/intel/gm45: Correctly cache TSEG Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/ram_calc.c 3 files changed, 14 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29866/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Gerrit-Change-Number: 29866 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: cpu/intel/fit: Make FIT microcode updates selectable
by Philipp Deppenwiese (Code Review) 27 Nov '18

27 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29863 to look at the new patch set (#2). Change subject: cpu/intel/fit: Make FIT microcode updates selectable ...................................................................... cpu/intel/fit: Make FIT microcode updates selectable * Add a kconfig option for de-/selecting microcode updates via Firmware Interface Table. * Default didn't change and stays "yes". Change-Id: I7da926943aef89e49e98d0b990ab46f5f8200e6e Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M Makefile.inc M src/cpu/intel/fit/Kconfig 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29863/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7da926943aef89e49e98d0b990ab46f5f8200e6e Gerrit-Change-Number: 29863 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: nb/intel/gm45: Correctly cache TSEG
by Nico Huber (Code Review) 27 Nov '18

27 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29866 ) Change subject: nb/intel/gm45: Correctly cache TSEG ...................................................................... Patch Set 3: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/29866/3/src/northbridge/intel/gm45/ram_calc… File src/northbridge/intel/gm45/ram_calc.c: https://review.coreboot.org/#/c/29866/3/src/northbridge/intel/gm45/ram_calc… PS3, Line 87: uintptr_t smm_region_start(void) Could be static now. Could also rename this to `northbridge_get_tseg_base`. And remove the declaration in `gm45.h`. -- To view, visit https://review.coreboot.org/c/coreboot/+/29866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Gerrit-Change-Number: 29866 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Nov 2018 13:38:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: nb/intel/gm45: Correctly cache TSEG
by Arthur Heymans (Code Review) 27 Nov '18

27 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29866 to look at the new patch set (#3). Change subject: nb/intel/gm45: Correctly cache TSEG ...................................................................... nb/intel/gm45: Correctly cache TSEG Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/ram_calc.c 2 files changed, 17 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29866/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Gerrit-Change-Number: 29866 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: nb/intel/gm45: Correctly cache TSEG
by Arthur Heymans (Code Review) 27 Nov '18

27 Nov '18

Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29866 to look at the new patch set (#2). Change subject: nb/intel/gm45: Correctly cache TSEG ...................................................................... nb/intel/gm45: Correctly cache TSEG Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/ram_calc.c 2 files changed, 16 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29866/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Gerrit-Change-Number: 29866 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: nb/intel/gm45: Correctly cache TSEG
by Arthur Heymans (Code Review) 27 Nov '18

27 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29866 Change subject: nb/intel/gm45: Correctly cache TSEG ...................................................................... nb/intel/gm45: Correctly cache TSEG Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/ram_calc.c 2 files changed, 16 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29866/1 diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 0fd7fe5..a001a67 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -221,22 +221,6 @@ return NULL; } -u32 northbridge_get_tseg_base(void) -{ - return (u32)smm_region_start(); -} - -u32 northbridge_get_tseg_size(void) -{ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC); - return decode_tseg_size(esmramc) << 10; -} - void northbridge_write_smram(u8 smram) { struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 5af3e16..da1963e 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -106,6 +106,17 @@ return tor; } +u32 northbridge_get_tseg_base(void) +{ + return (u32)smm_region_start(); +} + +u32 northbridge_get_tseg_size(void) +{ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); + return decode_tseg_size(esmramc) << 10; +} + /* Depending of UMA and TSEG configuration, TSEG might start at any * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. @@ -135,12 +146,12 @@ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache a 8 MiB region below the top of ram and 8 MiB above top of + /* Cache 8 MiB region below the top of ram and 2 MiB above top of * ram to cover both cbmem as the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); + */ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), + northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); run_postcar_phase(&pcf); -- To view, visit https://review.coreboot.org/c/coreboot/+/29866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Gerrit-Change-Number: 29866 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: cpu/intel/microcode: Enable verbose output
by Philipp Deppenwiese (Code Review) 27 Nov '18

27 Nov '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29864 Change subject: cpu/intel/microcode: Enable verbose output ...................................................................... cpu/intel/microcode: Enable verbose output * Check if microcode is really updated. * Enable more verbose output. Change-Id: I534aa790c8d37b5f1603e1715635446835513a65 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/cpu/intel/microcode/microcode.c 1 file changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/29864/1 diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index d217cfd..96b9e4e 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -89,8 +89,12 @@ current_rev = read_microcode_rev(); /* No use loading the same revision. */ - if (current_rev == m->rev) + if (current_rev == m->rev) { +#if !defined(__ROMCC__) + printk(BIOS_INFO, "microcode: Update skipped, already up-to-date\n"); +#endif return; + } #if ENV_RAMSTAGE /*SoC specific check to update microcode*/ @@ -104,12 +108,20 @@ msr.hi = 0; wrmsr(IA32_BIOS_UPDT_TRIG, msr); + current_rev = read_microcode_rev(); + if (current_rev == m->rev) { #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "microcode: updated to revision " + printk(BIOS_INFO, "microcode: updated to revision " "0x%x date=%04x-%02x-%02x\n", read_microcode_rev(), m->date & 0xffff, (m->date >> 24) & 0xff, (m->date >> 16) & 0xff); #endif + return; + } + +#if !defined(__ROMCC__) + printk(BIOS_INFO, "microcode: Update failed\n"); +#endif } uint32_t get_current_microcode_rev(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/29864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534aa790c8d37b5f1603e1715635446835513a65 Gerrit-Change-Number: 29864 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: soc/{amd, intel}: Remove duplicated '&' on ptr's function
by David Guckian (Code Review) 27 Nov '18

27 Nov '18

David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29862 ) Change subject: soc/{amd,intel}: Remove duplicated '&' on ptr's function ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a59fd2f370d2b0d830ca83be9a9bc1abe2750f5 Gerrit-Change-Number: 29862 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Nov 2018 12:39:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2018