coreboot-gerrit November 2018

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Change in ...coreboot[master]: sb/intel: Fix pointer casts
by Patrick Rudolph (Code Review) 28 Nov '18

28 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29875 Change subject: sb/intel: Fix pointer casts ...................................................................... sb/intel: Fix pointer casts Fix some compiler warnings due to pointer to integer conversions with different size. Required for 64bit ramstage. Change-Id: Ibfb3cacf25adfb4a242d38e4ea290fdc3929a684 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/sata.c 4 files changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/29875/1 diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 3c25556..3ce4f40 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -150,7 +150,7 @@ "outb %%al, %%dx\n\t" : /* ignore result */ : "a" (APM_CNT_GNVS_UPDATE), - "b" ((u32)gnvs), + "b" ((uintptr_t)gnvs), "d" (APM_CNT) ); } diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 607604b..b4cee46 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -278,7 +278,7 @@ // NOTE this will break as soon as the Azalia get's a bar above // 4G. Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); codec_mask = codec_detect(base); if (codec_mask) { diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index a69b879..474c484 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -553,7 +553,7 @@ /* Add it to SSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); acpigen_pop_len(); } } diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index dcdeeb4..e35babc 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -30,9 +30,14 @@ { int i; u32 reg32; + struct resource *res; /* Initialize AHCI memory-mapped space */ - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + res = find_resource(dev, PCI_BASE_ADDRESS_5); + if (!res) + return; + + u8 *abar = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* Set AHCI access mode. -- To view, visit https://review.coreboot.org/c/coreboot/+/29875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfb3cacf25adfb4a242d38e4ea290fdc3929a684 Gerrit-Change-Number: 29875 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbfstool: Support AMD64 rmodules
by Patrick Rudolph (Code Review) 28 Nov '18

28 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29874 Change subject: util/cbfstool: Support AMD64 rmodules ...................................................................... util/cbfstool: Support AMD64 rmodules Add support for 64bit rmodule, as required for relocatable ramstage on x86_64. Change-Id: I7fbb3b4c0f76ce82c090b5f16f67a728b6bf94a5 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M util/cbfstool/elf.h M util/cbfstool/elfheaders.c M util/cbfstool/rmodule.c 3 files changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29874/1 diff --git a/util/cbfstool/elf.h b/util/cbfstool/elf.h index a0bb35d..43fd7f3 100644 --- a/util/cbfstool/elf.h +++ b/util/cbfstool/elf.h @@ -1148,6 +1148,43 @@ /* Keep this the last entry. */ #define R_386_NUM 38 +/* AMD64 specific definitions. */ +#define R_AMD64_NONE 0 /* relocation types */ +#define R_AMD64_64 1 +#define R_AMD64_PC32 2 +#define R_AMD64_GOT32 3 +#define R_AMD64_PLT32 4 +#define R_AMD64_COPY 5 +#define R_AMD64_GLOB_DAT 6 +#define R_AMD64_JUMP_SLOT 7 +#define R_AMD64_RELATIVE 8 +#define R_AMD64_GOTPCREL 9 +#define R_AMD64_32 10 +#define R_AMD64_32S 11 +#define R_AMD64_16 12 +#define R_AMD64_PC16 13 +#define R_AMD64_8 14 +#define R_AMD64_PC8 15 +#define R_AMD64_DTPMOD64 16 +#define R_AMD64_DTPOFF64 17 +#define R_AMD64_TPOFF64 18 +#define R_AMD64_TLSGD 19 +#define R_AMD64_TLSLD 20 +#define R_AMD64_DTPOFF32 21 +#define R_AMD64_GOTTPOFF 22 +#define R_AMD64_TPOFF32 23 +#define R_AMD64_PC64 24 +#define R_AMD64_GOTOFF64 25 +#define R_AMD64_GOTPC32 26 +#define R_AMD64_GOT64 27 /* reserved for future expansion */ +#define R_AMD64_GOTPCREL64 28 /* reserved for future expansion */ +#define R_AMD64_GOTPC64 29 /* reserved for future expansion */ +#define R_AMD64_GOTPLT64 30 /* reserved for future expansion */ +#define R_AMD64_PLTOFF64 31 /* reserved for future expansion */ +#define R_AMD64_SIZE32 32 +#define R_AMD64_SIZE64 33 +#define R_AMD64_NUM 34 + /* SUN SPARC specific definitions. */ /* Legal values for ST_TYPE subfield of st_info (symbol type). */ diff --git a/util/cbfstool/elfheaders.c b/util/cbfstool/elfheaders.c index 9d02c30..8da54d0 100644 --- a/util/cbfstool/elfheaders.c +++ b/util/cbfstool/elfheaders.c @@ -1072,6 +1072,9 @@ case EM_386: type = R_386_32; break; + case EM_X86_64: + type = R_AMD64_64; + break; case EM_ARM: type = R_ARM_ABS32; break; diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index 07957cb..6808826 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -43,6 +43,33 @@ return (type == R_386_32); } +static int valid_reloc_amd64(Elf64_Rela *rel) +{ + int type; + + type = ELF64_R_TYPE(rel->r_info); + + /* Only these 5 relocations are expected to be found. */ + return (type == R_AMD64_64 || + type == R_AMD64_PC64 || + type == R_AMD64_32S || + type == R_AMD64_32 || + type == R_AMD64_PC32); +} + +static int should_emit_amd64(Elf64_Rela *rel) +{ + int type; + + type = ELF64_R_TYPE(rel->r_info); + + /* Only emit absolute relocations */ + return (type == R_AMD64_64 || + type == R_AMD64_PC64 || + type == R_AMD64_32S || + type == R_AMD64_32); +} + static int valid_reloc_arm(Elf64_Rela *rel) { int type; @@ -100,6 +127,11 @@ .should_emit = should_emit_386, }, { + .arch = EM_X86_64, + .valid_type = valid_reloc_amd64, + .should_emit = should_emit_amd64, + }, + { .arch = EM_ARM, .valid_type = valid_reloc_arm, .should_emit = should_emit_arm, -- To view, visit https://review.coreboot.org/c/coreboot/+/29874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fbb3b4c0f76ce82c090b5f16f67a728b6bf94a5 Gerrit-Change-Number: 29874 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
by Ren Kuo (Code Review) 28 Nov '18

28 Nov '18

Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29872 ) Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29872/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nami/gpio.c: https://review.coreboot.org/#/c/29872/2/src/mainboard/google/poppy/variants… PS2, Line 413: PAD_CFG_GPI_APIC > Did you try PAD_CFG_GPI_APIC_INVERT? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Gerrit-Change-Number: 29872 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 28 Nov 2018 05:08:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: google/grunt: Update hynix-H5ANAG6NAMR-UH.spd.hex SPD file Module Par...
by Lucas Chen (Code Review) 28 Nov '18

28 Nov '18

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29873 Change subject: google/grunt: Update hynix-H5ANAG6NAMR-UH.spd.hex SPD file Module Part Number ...................................................................... google/grunt: Update hynix-H5ANAG6NAMR-UH.spd.hex SPD file Module Part Number Correct Ram_ID=0b0001 SPD Module Part Number to "H5ANAG6NAMR-UH" from "HMAA51S6AMR6N-UH". BUG=b:120000816 BRANCH=master TEST=mosys memory spd print all Change-Id: I59d920498ff6b73e9e7b2887771ad6bc6c6c0b66 Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NAMR-UH.spd.hex 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29873/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NAMR-UH.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NAMR-UH.spd.hex index bd184ad..0071c88 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NAMR-UH.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/hynix-H5ANAG6NAMR-UH.spd.hex @@ -19,8 +19,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 AD 01 00 00 00 00 00 00 48 4D 41 41 35 31 53 -36 41 4D 52 36 4E 2D 55 48 20 20 20 20 00 80 AD +80 AD 01 00 00 00 00 00 00 48 35 41 4E 41 47 36 +4E 41 4D 52 2D 55 48 20 20 20 20 20 20 00 80 AD FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/29873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59d920498ff6b73e9e7b2887771ad6bc6c6c0b66 Gerrit-Change-Number: 29873 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
by Furquan Shaikh (Code Review) 28 Nov '18

28 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29872 ) Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29872/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nami/gpio.c: https://review.coreboot.org/#/c/29872/2/src/mainboard/google/poppy/variants… PS2, Line 413: PAD_CFG_GPI_APIC Did you try PAD_CFG_GPI_APIC_INVERT? -- To view, visit https://review.coreboot.org/c/coreboot/+/29872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Gerrit-Change-Number: 29872 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 28 Nov 2018 03:13:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common/acpi: Add common CPU methods
by Duncan Laurie (Code Review) 28 Nov '18

28 Nov '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29754 ) Change subject: soc/intel/common/acpi: Add common CPU methods ...................................................................... Patch Set 1: It is a good idea, but I think it is a much larger change than just fixing the cannonlake bug where these methods don't exist, which I could do instead of refactoring it into common code if we want to instead push for a change in this direction. However, I think calling back into an SSDT from the DSDT is still not allowed by the linux kernel, and currently all the DPTF code is in the DSDT... -- To view, visit https://review.coreboot.org/c/coreboot/+/29754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd467ef84a391698cd395172c3f0d4e801bdd09b Gerrit-Change-Number: 29754 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 28 Nov 2018 01:49:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common/acpi: Add common CPU methods
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29754 ) Change subject: soc/intel/common/acpi: Add common CPU methods ...................................................................... Patch Set 1: Please try to implement it with the dynamic SSDT generator, like done in https://review.coreboot.org/c/coreboot/+/23144 -- To view, visit https://review.coreboot.org/c/coreboot/+/29754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd467ef84a391698cd395172c3f0d4e801bdd09b Gerrit-Change-Number: 29754 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 28 Nov 2018 01:30:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
by Shelley Chen (Code Review) 28 Nov '18

28 Nov '18

Shelley Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/29872 ) Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group ...................................................................... mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group We discovered that the gpios previously used for FPMCU_INT_L were in two different groups with two different voltages (C group was at 3.3V and D group was at 1.8V). Moving both to B group which is at 3.3V. BUG=b:119447525 BRANCH=Nami TEST=unlock OS with fingerprint register fingerprint run powerd_dbus_suspend and see if it goes int s0ix Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nami/gpio.c 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29872/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Gerrit-Change-Number: 29872 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
by Shelley Chen (Code Review) 28 Nov '18

28 Nov '18

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29872 Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group ...................................................................... mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group We discovered that the gpios previously used for FPMCU_INT_L were in two different groups with two different voltages (C group was at 3.3V and D group was at 1.8V). Moving both to B group which is at 3.3V. BUG=b:119447525 BRANCH=Nami TEST=unlock OS with fingerprint register fingerprint run powerd_dbus_suspend and see if it goes int s0ix Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nami/gpio.c 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29872/1 diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 49e35b2..cd57398 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -455,8 +455,8 @@ register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)" - register "wake" = "GPE0_DW1_06" # GPP_D6 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B0_IRQ)" + register "wake" = "GPE0_DW0_01" # GPP_B1 device spi 0 on end end # FPMCU end # GSPI #1 diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 2c9b932..0fa25a8 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -421,14 +421,14 @@ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ PAD_CFG_GPO(GPP_C3, 0, DEEP), - /* C8 : UART0_RXD ==> FPMCU_INT_L */ - PAD_CFG_GPI_APIC(GPP_C8, NONE, DEEP), + /* B0 : CORE_VID0 ==> FPMCU_INT_L */ + PAD_CFG_GPI_APIC(GPP_B0, NONE, DEEP), /* C9 : UART0_TXD ==> FP_RST_ODL */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_D5, 0, DEEP), - /* D6 : ISH_I2C0_SCL ==> FPMCU_INT_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_D6, 20K_PU, DEEP, INVERT), + /* B1 : CORE_VID1 ==> FPMCU_INT_L */ + PAD_CFG_GPI_ACPI_SCI(GPP_B1, 20K_PU, DEEP, INVERT), /* D17 : DMIC_CLK1 ==> NC */ PAD_CFG_NC(GPP_D17), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/29872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Gerrit-Change-Number: 29872 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Program HD Audio SVID/SSID
by Duncan Laurie (Code Review) 27 Nov '18

27 Nov '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29651 ) Change subject: mb/google/sarien: Program HD Audio SVID/SSID ...................................................................... Patch Set 1: Could we do this at the SOC level? If we had a Kconfig entry in the SOC that allowed the mainboard to define an HDA codec device ID then the SOC level code could have this structure (filled with CONFIG_SUBSYSTEM_VENDOR_ID and something like CONFIG_HDA_CODEC_ID) and pass it to FSP if HDA is enabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Comment-Date: Tue, 27 Nov 2018 21:15:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2018