coreboot-gerrit November 2018

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Change in ...coreboot[master]: siemens/mc_apl5: Set bus master bit for on-board PCI device
by Mario Scheithauer (Code Review) 28 Nov '18

28 Nov '18

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29881 ) Change subject: siemens/mc_apl5: Set bus master bit for on-board PCI device ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/29881/1/src/mainboard/siemens/mc_apl1/varia… File src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c: https://review.coreboot.org/#/c/29881/1/src/mainboard/siemens/mc_apl1/varia… PS1, Line 37: ; > Not needed as it will be set explicitly to a value on line 82. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb Gerrit-Change-Number: 29881 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 08:43:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: siemens/mc_apl5: Set bus master bit for on-board PCI device
by Mario Scheithauer (Code Review) 28 Nov '18

28 Nov '18

Hello Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29881 to look at the new patch set (#3). Change subject: siemens/mc_apl5: Set bus master bit for on-board PCI device ...................................................................... siemens/mc_apl5: Set bus master bit for on-board PCI device There is an on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29881/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb Gerrit-Change-Number: 29881 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: siemens/mc_apl5: Set bus master bit for on-board PCI device
by Mario Scheithauer (Code Review) 28 Nov '18

28 Nov '18

Hello Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29881 to look at the new patch set (#2). Change subject: siemens/mc_apl5: Set bus master bit for on-board PCI device ...................................................................... siemens/mc_apl5: Set bus master bit for on-board PCI device There is an on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29881/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb Gerrit-Change-Number: 29881 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: siemens/mc_apl5: Disable PCI clock outputs on XIO bridges
by Mario Scheithauer (Code Review) 28 Nov '18

28 Nov '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29882 Change subject: siemens/mc_apl5: Disable PCI clock outputs on XIO bridges ...................................................................... siemens/mc_apl5: Disable PCI clock outputs on XIO bridges On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c 1 file changed, 16 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/29882/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index 5ad3172..e859380 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -52,11 +52,6 @@ */ pcr_write16(PID_ITSS, 0x314c, 0x0321); - /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ - dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); - if (dev) - pci_write_config8(dev, 0xd8, 0x3e); - /* Enable CLKRUN_EN for power gating LPC */ lpc_enable_pci_clk_cntl(); @@ -82,6 +77,22 @@ cmd = pci_read_config16(dev, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); + + /* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe + * to PCI Bridge. */ + struct device *parent = dev->bus->dev; + if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) + pci_write_config8(parent, 0xd8, 0x0f); + } + + /* Disable clock outputs 1-5 (CLKOUT) for another XIO2001 PCIe to PCI + * Bridge on this mainboard. + */ + dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); + if (dev) { + struct device *parent = dev->bus->dev; + if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) + pci_write_config8(parent, 0xd8, 0x3e); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/29882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91 Gerrit-Change-Number: 29882 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: siemens/mc_apl5: Set bus master bit for on-board PCI device
by Werner Zeh (Code Review) 28 Nov '18

28 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29881 ) Change subject: siemens/mc_apl5: Set bus master bit for on-board PCI device ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29881/1/src/mainboard/siemens/mc_apl1/varia… File src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c: https://review.coreboot.org/#/c/29881/1/src/mainboard/siemens/mc_apl1/varia… PS1, Line 37: = 0 Not needed as it will be set explicitly to a value on line 82. -- To view, visit https://review.coreboot.org/c/coreboot/+/29881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb Gerrit-Change-Number: 29881 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 28 Nov 2018 08:19:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: siemens/mc_apl5: Enable SDCARD
by Werner Zeh (Code Review) 28 Nov '18

28 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29879 ) Change subject: siemens/mc_apl5: Enable SDCARD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I969e8ecb27aee4c8be212e67dfe6bd807ecd3b2f Gerrit-Change-Number: 29879 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 08:17:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: siemens/mc_apl5: Set bus master bit for on-board PCI device
by Mario Scheithauer (Code Review) 28 Nov '18

28 Nov '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29881 Change subject: siemens/mc_apl5: Set bus master bit for on-board PCI device ...................................................................... siemens/mc_apl5: Set bus master bit for on-board PCI device There is an on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29881/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index 6d22fd9..5ad3172 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -15,6 +15,7 @@ #include <bootstate.h> #include <console/console.h> +#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <gpio.h> @@ -33,6 +34,7 @@ { int status; struct device *dev = NULL; + uint16_t cmd = 0; /* * Set up the DP2LVDS converter. @@ -73,6 +75,14 @@ * The value 0x4a sets the swing level to 0.58 V. */ pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); + + /* Set Master Enable for on-board PCI device. */ + dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); + if (dev) { + cmd = pci_read_config16(dev, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, cmd); + } } static void wait_for_legacy_dev(void *unused) -- To view, visit https://review.coreboot.org/c/coreboot/+/29881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb Gerrit-Change-Number: 29881 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/gma: Fix typo in header
by Frans Hendriks (Code Review) 28 Nov '18

28 Nov '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29880 Change subject: drivers/intel/gma: Fix typo in header ...................................................................... drivers/intel/gma: Fix typo in header Correct typo of 'version' BUG=N/A TEST=N/A Change-Id: I05d7856072042c79f9d7aafdfecc9b3635f1d0cc Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/gma/edid.c M src/drivers/intel/gma/opregion.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29880/1 diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 74bb6c6..d2475cf 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -7,7 +7,7 @@ * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2, or (at your option) - * any later verion of the License. + * any later version of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 5def085..57d03ad 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -6,7 +6,7 @@ * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2, or (at your option) - * any later verion of the License. + * any later version of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of -- To view, visit https://review.coreboot.org/c/coreboot/+/29880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05d7856072042c79f9d7aafdfecc9b3635f1d0cc Gerrit-Change-Number: 29880 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Remove duplicated round up function
by build bot (Jenkins) (Code Review) 28 Nov '18

28 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29847 ) Change subject: src: Remove duplicated round up function ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/29847/5/src/soc/nvidia/tegra210/include/soc… File src/soc/nvidia/tegra210/include/soc/clock.h: https://review.coreboot.org/#/c/29847/5/src/soc/nvidia/tegra210/include/soc… PS5, Line 327: #define get_i2c_clk_div(src,freq) (DIV_ROUND_UP(src, (freq) * (0x19 + 1) * 8) - 1) line over 80 characters https://review.coreboot.org/#/c/29847/5/src/soc/nvidia/tegra210/include/soc… PS5, Line 327: #define get_i2c_clk_div(src,freq) (DIV_ROUND_UP(src, (freq) * (0x19 + 1) * 8) - 1) space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/29847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Gerrit-Change-Number: 29847 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Nov 2018 08:03:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/siemens/mc_{apl1, tcu3}: [test] Fix sizeof on array function
by HAOUAS Elyes (Code Review) 28 Nov '18

28 Nov '18

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29858 ) Change subject: mb/siemens/mc_{apl1,tcu3}: [test] Fix sizeof on array function ...................................................................... Abandoned my mistake... -- To view, visit https://review.coreboot.org/c/coreboot/+/29858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I982a7a9baf22998503da0e94952fbb30124dfe28 Gerrit-Change-Number: 29858 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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coreboot-gerrit November 2018