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Change in ...coreboot[master]: soc/intel/denverton_ns: Rework acpi/cpu.asl
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29892 Change subject: soc/intel/denverton_ns: Rework acpi/cpu.asl ...................................................................... soc/intel/denverton_ns: Rework acpi/cpu.asl Change-Id: If482c64e7133cc6d82472d121ac138fc1b60a183 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/acpi/cpu.asl 2 files changed, 22 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/29892/1 diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index a75a182..416d1e4 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -253,6 +253,22 @@ acpigen_pop_len(); } + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, num_cpus); + + /* Add a method to notify processor nodes */ + acpigen_write_method("\\_PR.CNOT", 1); + for (core = 0; core < num_cpus; core++) { + char buffer[DEVICE_PATH_MAX]; + snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c", + '0' + core / 10, '0' + core % 10); + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(buffer); + acpigen_emit_byte(ARG0_OP); + } + acpigen_pop_len(); + } unsigned long acpi_madt_irq_overrides(unsigned long current) diff --git a/src/soc/intel/denverton_ns/acpi/cpu.asl b/src/soc/intel/denverton_ns/acpi/cpu.asl index 00dc6c7..60ecc5c 100644 --- a/src/soc/intel/denverton_ns/acpi/cpu.asl +++ b/src/soc/intel/denverton_ns/acpi/cpu.asl @@ -15,127 +15,23 @@ * */ -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) -External (\_PR.CP04, DeviceObj) -External (\_PR.CP05, DeviceObj) -External (\_PR.CP06, DeviceObj) -External (\_PR.CP07, DeviceObj) -External (\_PR.CP08, DeviceObj) -External (\_PR.CP09, DeviceObj) -External (\_PR.CP10, DeviceObj) -External (\_PR.CP11, DeviceObj) -External (\_PR.CP12, DeviceObj) -External (\_PR.CP13, DeviceObj) -External (\_PR.CP14, DeviceObj) -External (\_PR.CP15, DeviceObj) +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x81) // _CST - Notify (\_PR.CP05, 0x81) // _CST - Notify (\_PR.CP06, 0x81) // _CST - Notify (\_PR.CP07, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 16)) { - Notify (\_PR.CP08, 0x81) // _CST - Notify (\_PR.CP09, 0x81) // _CST - Notify (\_PR.CP10, 0x81) // _CST - Notify (\_PR.CP11, 0x81) // _CST - Notify (\_PR.CP12, 0x81) // _CST - Notify (\_PR.CP13, 0x81) // _CST - Notify (\_PR.CP14, 0x81) // _CST - Notify (\_PR.CP15, 0x81) // _CST - } + \_PR.CNOT (0x81) } /* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ Method (PPCN) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) // _PPC - Notify (\_PR.CP01, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) // _PPC - Notify (\_PR.CP03, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x80) // _PPC - Notify (\_PR.CP05, 0x80) // _PPC - Notify (\_PR.CP06, 0x80) // _PPC - Notify (\_PR.CP07, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 16)) { - Notify (\_PR.CP08, 0x80) // _PPC - Notify (\_PR.CP09, 0x80) // _PPC - Notify (\_PR.CP10, 0x80) // _PPC - Notify (\_PR.CP11, 0x80) // _PPC - Notify (\_PR.CP12, 0x80) // _PPC - Notify (\_PR.CP13, 0x80) // _PPC - Notify (\_PR.CP14, 0x80) // _PPC - Notify (\_PR.CP15, 0x80) // _PPC - } + \_PR.CNOT (0x81) } /* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ Method (TNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) // _TPC - Notify (\_PR.CP01, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) // _TPC - Notify (\_PR.CP03, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x82) // _TPC - Notify (\_PR.CP05, 0x82) // _TPC - Notify (\_PR.CP06, 0x82) // _TPC - Notify (\_PR.CP07, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 16)) { - Notify (\_PR.CP08, 0x82) // _TPC - Notify (\_PR.CP09, 0x82) // _TPC - Notify (\_PR.CP10, 0x82) // _TPC - Notify (\_PR.CP11, 0x82) // _TPC - Notify (\_PR.CP12, 0x82) // _TPC - Notify (\_PR.CP13, 0x82) // _TPC - Notify (\_PR.CP14, 0x82) // _TPC - Notify (\_PR.CP15, 0x82) // _TPC - } -} - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (LGreaterEqual (\PCNT, 16)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, - \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07, - \_PR.CP08, \_PR.CP09, \_PR.CP10, \_PR.CP11, - \_PR.CP12, \_PR.CP13, \_PR.CP14, \_PR.CP15}) - } ElseIf (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, - \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) - } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) - } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CP00, \_PR.CP01}) - } Else { - Return (Package() {\_PR.CP00}) - } -} + \_PR.CNOT (0x82) +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/29892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If482c64e7133cc6d82472d121ac138fc1b60a183 Gerrit-Change-Number: 29892 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: soc/intel/common: Rework acpi/cpu.asl
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29891 Change subject: soc/intel/common: Rework acpi/cpu.asl ...................................................................... soc/intel/common: Rework acpi/cpu.asl Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/acpi/cpu.asl M src/soc/intel/cannonlake/acpi/cpu.asl M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/icelake/acpi/cpu.asl 4 files changed, 51 insertions(+), 135 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/29891/1 diff --git a/src/soc/intel/apollolake/acpi/cpu.asl b/src/soc/intel/apollolake/acpi/cpu.asl index a202ceb..8b2e080 100644 --- a/src/soc/intel/apollolake/acpi/cpu.asl +++ b/src/soc/intel/apollolake/acpi/cpu.asl @@ -13,106 +13,23 @@ * GNU General Public License for more details. */ -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) -External (\_PR.CP04, DeviceObj) -External (\_PR.CP05, DeviceObj) -External (\_PR.CP06, DeviceObj) -External (\_PR.CP07, DeviceObj) +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x81) // _CST - Notify (\_PR.CP05, 0x81) // _CST - Notify (\_PR.CP06, 0x81) // _CST - Notify (\_PR.CP07, 0x81) // _CST - } + \_PR.CNOT (0x81) } /* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ Method (PPCN) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) // _PPC - Notify (\_PR.CP01, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) // _PPC - Notify (\_PR.CP03, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x80) // _PPC - Notify (\_PR.CP05, 0x80) // _PPC - Notify (\_PR.CP06, 0x80) // _PPC - Notify (\_PR.CP07, 0x80) // _PPC - } + \_PR.CNOT (0x81) } /* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ Method (TNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) // _TPC - Notify (\_PR.CP01, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) // _TPC - Notify (\_PR.CP03, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x82) // _TPC - Notify (\_PR.CP05, 0x82) // _TPC - Notify (\_PR.CP06, 0x82) // _TPC - Notify (\_PR.CP07, 0x82) // _TPC - } -} - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (LGreaterEqual (\PCNT, 8)) { - Return (Package() - { - \_PR.CP00, - \_PR.CP01, - \_PR.CP02, - \_PR.CP03, - \_PR.CP04, - \_PR.CP05, - \_PR.CP06, - \_PR.CP07 - }) - } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package () - { - \_PR.CP00, - \_PR.CP01, - \_PR.CP02, - \_PR.CP03 - }) - } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package () - { - \_PR.CP00, - \_PR.CP01 - }) - } Else { - Return (Package () - { - \_PR.CP00 - }) - } -} + \_PR.CNOT (0x82) +} \ No newline at end of file diff --git a/src/soc/intel/cannonlake/acpi/cpu.asl b/src/soc/intel/cannonlake/acpi/cpu.asl index 79314e6..7c074b8 100644 --- a/src/soc/intel/cannonlake/acpi/cpu.asl +++ b/src/soc/intel/cannonlake/acpi/cpu.asl @@ -13,31 +13,23 @@ * GNU General Public License for more details. */ -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) -External (\_PR.CP04, DeviceObj) -External (\_PR.CP05, DeviceObj) -External (\_PR.CP06, DeviceObj) -External (\_PR.CP07, DeviceObj) +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x81) // _CST - Notify (\_PR.CP05, 0x81) // _CST - Notify (\_PR.CP06, 0x81) // _CST - Notify (\_PR.CP07, 0x81) // _CST - } + \_PR.CNOT (0x81) } + +/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ +Method (PPCN) +{ + \_PR.CNOT (0x81) +} + +/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ +Method (TNOT) +{ + \_PR.CNOT (0x82) +} \ No newline at end of file diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 870e371..0b62a73 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -436,6 +436,21 @@ acpigen_pop_len(); } } + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_method("\\_PR.CNOT", 1); + for (core_id = 0; core_id < cores_per_package; core_id++) { + char buffer[DEVICE_PATH_MAX]; + snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c", + '0' + core_id / 10, '0' + core_id % 10); + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(buffer); + acpigen_emit_byte(ARG0_OP); + } + acpigen_pop_len(); } #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) diff --git a/src/soc/intel/icelake/acpi/cpu.asl b/src/soc/intel/icelake/acpi/cpu.asl index be6e793..76d2201 100644 --- a/src/soc/intel/icelake/acpi/cpu.asl +++ b/src/soc/intel/icelake/acpi/cpu.asl @@ -13,31 +13,23 @@ * GNU General Public License for more details. */ -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) -External (\_PR.CP04, DeviceObj) -External (\_PR.CP05, DeviceObj) -External (\_PR.CP06, DeviceObj) -External (\_PR.CP07, DeviceObj) +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x81) // _CST - Notify (\_PR.CP05, 0x81) // _CST - Notify (\_PR.CP06, 0x81) // _CST - Notify (\_PR.CP07, 0x81) // _CST - } + \_PR.CNOT (0x81) } + +/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ +Method (PPCN) +{ + \_PR.CNOT (0x81) +} + +/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ +Method (TNOT) +{ + \_PR.CNOT (0x82) +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/29891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae Gerrit-Change-Number: 29891 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/broadwell: Rework acpi/cpu.asl
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29890 Change subject: soc/intel/broadwell: Rework acpi/cpu.asl ...................................................................... soc/intel/broadwell: Rework acpi/cpu.asl Change-Id: I79d2eed9b89b420554ce10d1fc0f151b1872afe2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/acpi/cpu.asl 2 files changed, 22 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/29890/1 diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 2d9d0b7..7a24250 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -570,6 +570,22 @@ acpigen_pop_len(); } } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_method("\\_PR.CNOT", 1); + for (coreID = 0; coreID < cores_per_package; coreID++) { + char buffer[DEVICE_PATH_MAX]; + snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c", + '0' + coreID / 10, '0' + coreID % 10); + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(buffer); + acpigen_emit_byte(ARG0_OP); + } + acpigen_pop_len(); } static unsigned long acpi_fill_dmar(unsigned long current) diff --git a/src/soc/intel/broadwell/acpi/cpu.asl b/src/soc/intel/broadwell/acpi/cpu.asl index a202ceb..8b2e080 100644 --- a/src/soc/intel/broadwell/acpi/cpu.asl +++ b/src/soc/intel/broadwell/acpi/cpu.asl @@ -13,106 +13,23 @@ * GNU General Public License for more details. */ -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) -External (\_PR.CP04, DeviceObj) -External (\_PR.CP05, DeviceObj) -External (\_PR.CP06, DeviceObj) -External (\_PR.CP07, DeviceObj) +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x81) // _CST - Notify (\_PR.CP05, 0x81) // _CST - Notify (\_PR.CP06, 0x81) // _CST - Notify (\_PR.CP07, 0x81) // _CST - } + \_PR.CNOT (0x81) } /* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ Method (PPCN) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) // _PPC - Notify (\_PR.CP01, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) // _PPC - Notify (\_PR.CP03, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x80) // _PPC - Notify (\_PR.CP05, 0x80) // _PPC - Notify (\_PR.CP06, 0x80) // _PPC - Notify (\_PR.CP07, 0x80) // _PPC - } + \_PR.CNOT (0x81) } /* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ Method (TNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) // _TPC - Notify (\_PR.CP01, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) // _TPC - Notify (\_PR.CP03, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x82) // _TPC - Notify (\_PR.CP05, 0x82) // _TPC - Notify (\_PR.CP06, 0x82) // _TPC - Notify (\_PR.CP07, 0x82) // _TPC - } -} - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (LGreaterEqual (\PCNT, 8)) { - Return (Package() - { - \_PR.CP00, - \_PR.CP01, - \_PR.CP02, - \_PR.CP03, - \_PR.CP04, - \_PR.CP05, - \_PR.CP06, - \_PR.CP07 - }) - } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package () - { - \_PR.CP00, - \_PR.CP01, - \_PR.CP02, - \_PR.CP03 - }) - } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package () - { - \_PR.CP00, - \_PR.CP01 - }) - } Else { - Return (Package () - { - \_PR.CP00 - }) - } -} + \_PR.CNOT (0x82) +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/29890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79d2eed9b89b420554ce10d1fc0f151b1872afe2 Gerrit-Change-Number: 29890 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: soc/intel/braswell: Rework acpi/cpu.asl
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29889 Change subject: soc/intel/braswell: Rework acpi/cpu.asl ...................................................................... soc/intel/braswell: Rework acpi/cpu.asl Change-Id: I93c11e89da34c5432c6ce0415998b47bad339763 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/acpi/cpu.asl 2 files changed, 23 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/29889/1 diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index e791072..191eccf 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -448,6 +448,23 @@ acpigen_pop_len(); } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, pattrs->num_cpus); + + /* Add a method to notify processor nodes */ + acpigen_write_method("\\_PR.CNOT", 1); + for (core = 0; core < pattrs->num_cpus; coreID++) { + char buffer[DEVICE_PATH_MAX]; + snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c", + '0' + core / 10, '0' + core % 10); + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(buffer); + acpigen_emit_byte(ARG0_OP); + } + acpigen_pop_len(); + } unsigned long acpi_madt_irq_overrides(unsigned long current) diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl index 8bfd632..775b32f 100644 --- a/src/soc/intel/braswell/acpi/cpu.asl +++ b/src/soc/intel/braswell/acpi/cpu.asl @@ -14,60 +14,23 @@ * GNU General Public License for more details. */ -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) - +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) /* _CST */ - Notify (\_PR.CP01, 0x81) /* _CST */ - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) /* _CST */ - Notify (\_PR.CP03, 0x81) /* _CST */ - } + \_PR.CNOT (0x81) } /* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ Method (PPCN) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) /* _PPC */ - Notify (\_PR.CP01, 0x80) /* _PPC */ - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) /* _PPC */ - Notify (\_PR.CP03, 0x80) /* _PPC */ - } + \_PR.CNOT (0x81) } /* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ Method (TNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) /* _TPC */ - Notify (\_PR.CP01, 0x82) /* _TPC */ - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) /* _TPC */ - Notify (\_PR.CP03, 0x82) /* _TPC */ - } -} - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) - } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CP00, \_PR.CP01}) - } Else { - Return (Package() {\_PR.CP00}) - } -} + \_PR.CNOT (0x82) +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/29889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93c11e89da34c5432c6ce0415998b47bad339763 Gerrit-Change-Number: 29889 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/baytrail: Rework acpi/cpu.asl
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29888 Change subject: soc/intel/baytrail: Rework acpi/cpu.asl ...................................................................... soc/intel/baytrail: Rework acpi/cpu.asl Change-Id: Ifb5a5c1255f9a922063293bf430e849909468eaf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/acpi/cpu.asl 2 files changed, 24 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/29888/1 diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index e9934aa..e9c1e32 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -447,7 +447,7 @@ int pcontrol_blk = get_pmbase(), plen = 6; const struct pattrs *pattrs = pattrs_get(); - for (core=0; core<pattrs->num_cpus; core++) { + for (core=0; core < pattrs->num_cpus; core++) { if (core > 0) { pcontrol_blk = 0; plen = 0; @@ -471,6 +471,23 @@ acpigen_pop_len(); } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, pattrs->num_cpus); + + /* Add a method to notify processor nodes */ + acpigen_write_method("\\_PR.CNOT", 1); + for (core = 0; core < pattrs->num_cpus; coreID++) { + char buffer[DEVICE_PATH_MAX]; + snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c", + '0' + core / 10, '0' + core % 10); + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(buffer); + acpigen_emit_byte(ARG0_OP); + } + acpigen_pop_len(); + } unsigned long acpi_madt_irq_overrides(unsigned long current) diff --git a/src/soc/intel/baytrail/acpi/cpu.asl b/src/soc/intel/baytrail/acpi/cpu.asl index dc26e0a..775b32f 100644 --- a/src/soc/intel/baytrail/acpi/cpu.asl +++ b/src/soc/intel/baytrail/acpi/cpu.asl @@ -14,59 +14,23 @@ * GNU General Public License for more details. */ -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } + \_PR.CNOT (0x81) } /* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ Method (PPCN) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) // _PPC - Notify (\_PR.CP01, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) // _PPC - Notify (\_PR.CP03, 0x80) // _PPC - } + \_PR.CNOT (0x81) } /* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ Method (TNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) // _TPC - Notify (\_PR.CP01, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) // _TPC - Notify (\_PR.CP03, 0x82) // _TPC - } -} - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) - } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CP00, \_PR.CP01}) - } Else { - Return (Package() {\_PR.CP00}) - } -} + \_PR.CNOT (0x82) +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/29888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb5a5c1255f9a922063293bf430e849909468eaf Gerrit-Change-Number: 29888 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/fsp_model_406dx: Rework acpi/cpu.asl
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29887 Change subject: cpu/intel/fsp_model_406dx: Rework acpi/cpu.asl ...................................................................... cpu/intel/fsp_model_406dx: Rework acpi/cpu.asl Change-Id: I00d15d0640a37f89ffd5cc87b89d5ba11fecb9ed Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/fsp_model_406dx/acpi.c M src/cpu/intel/fsp_model_406dx/acpi/cpu.asl 2 files changed, 23 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/29887/1 diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index 80a56c0..b1f212e 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -295,6 +295,23 @@ acpigen_pop_len(); } } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_method("\\_PR.CNOT", 1); + for (coreID = 0; coreID < cores_per_package; coreID++) { + char buffer[DEVICE_PATH_MAX]; + snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c", + '0' + coreID / 10, '0' + coreID % 10); + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(buffer); + acpigen_emit_byte(ARG0_OP); + } + acpigen_pop_len(); + } struct chip_operations cpu_intel_model_406dx_ops = { diff --git a/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl b/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl index a95c54a..3ee5265 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl +++ b/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl @@ -14,84 +14,23 @@ * GNU General Public License for more details. */ -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) -External (\_PR.CP04, DeviceObj) -External (\_PR.CP05, DeviceObj) -External (\_PR.CP06, DeviceObj) -External (\_PR.CP07, DeviceObj) +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x81) // _CST - Notify (\_PR.CP05, 0x81) // _CST - Notify (\_PR.CP06, 0x81) // _CST - Notify (\_PR.CP07, 0x81) // _CST - } + \_PR.CNOT (0x81) } /* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ Method (PPCN) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) // _PPC - Notify (\_PR.CP01, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) // _PPC - Notify (\_PR.CP03, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x80) // _PPC - Notify (\_PR.CP05, 0x80) // _PPC - Notify (\_PR.CP06, 0x80) // _PPC - Notify (\_PR.CP07, 0x80) // _PPC - } + \_PR.CNOT (0x81) } /* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ Method (TNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) // _TPC - Notify (\_PR.CP01, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) // _TPC - Notify (\_PR.CP03, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x82) // _TPC - Notify (\_PR.CP05, 0x82) // _TPC - Notify (\_PR.CP06, 0x82) // _TPC - Notify (\_PR.CP07, 0x82) // _TPC - } -} - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, - \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) - } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) - } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CP00, \_PR.CP01}) - } Else { - Return (Package() {\_PR.CP00}) - } -} + \_PR.CNOT (0x82) +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/29887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00d15d0640a37f89ffd5cc87b89d5ba11fecb9ed Gerrit-Change-Number: 29887 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/model_206ax: Rework acpi/cpu.asl
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29886 Change subject: cpu/intel/model_206ax: Rework acpi/cpu.asl ...................................................................... cpu/intel/model_206ax: Rework acpi/cpu.asl Change-Id: Iecc54e94484f5f11e0ba8ef6d1d844276e484b4d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/acpi/cpu.asl 2 files changed, 23 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/29886/1 diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 8e2c0d1..50528b8 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -334,6 +334,23 @@ acpigen_pop_len(); } } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_method("\\_PR.CNOT", 1); + for (coreID = 0; coreID < cores_per_package; coreID++) { + char buffer[DEVICE_PATH_MAX]; + snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c", + '0' + coreID / 10, '0' + coreID % 10); + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(buffer); + acpigen_emit_byte(ARG0_OP); + } + acpigen_pop_len(); + } struct chip_operations cpu_intel_model_206ax_ops = { diff --git a/src/cpu/intel/model_206ax/acpi/cpu.asl b/src/cpu/intel/model_206ax/acpi/cpu.asl index a95c54a..3ee5265 100644 --- a/src/cpu/intel/model_206ax/acpi/cpu.asl +++ b/src/cpu/intel/model_206ax/acpi/cpu.asl @@ -14,84 +14,23 @@ * GNU General Public License for more details. */ -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) -External (\_PR.CP04, DeviceObj) -External (\_PR.CP05, DeviceObj) -External (\_PR.CP06, DeviceObj) -External (\_PR.CP07, DeviceObj) +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x81) // _CST - Notify (\_PR.CP05, 0x81) // _CST - Notify (\_PR.CP06, 0x81) // _CST - Notify (\_PR.CP07, 0x81) // _CST - } + \_PR.CNOT (0x81) } /* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ Method (PPCN) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) // _PPC - Notify (\_PR.CP01, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) // _PPC - Notify (\_PR.CP03, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x80) // _PPC - Notify (\_PR.CP05, 0x80) // _PPC - Notify (\_PR.CP06, 0x80) // _PPC - Notify (\_PR.CP07, 0x80) // _PPC - } + \_PR.CNOT (0x81) } /* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ Method (TNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) // _TPC - Notify (\_PR.CP01, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) // _TPC - Notify (\_PR.CP03, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x82) // _TPC - Notify (\_PR.CP05, 0x82) // _TPC - Notify (\_PR.CP06, 0x82) // _TPC - Notify (\_PR.CP07, 0x82) // _TPC - } -} - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, - \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) - } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) - } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CP00, \_PR.CP01}) - } Else { - Return (Package() {\_PR.CP00}) - } -} + \_PR.CNOT (0x82) +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/29886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecc54e94484f5f11e0ba8ef6d1d844276e484b4d Gerrit-Change-Number: 29886 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/haswell: Rework acpi/cpu.asl
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29885 Change subject: cpu/intel/haswell: Rework acpi/cpu.asl ...................................................................... cpu/intel/haswell: Rework acpi/cpu.asl Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/acpi/cpu.asl 2 files changed, 23 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/29885/1 diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 40279bf..6de1fb4 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -339,6 +339,23 @@ acpigen_pop_len(); } } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_method("\\_PR.CNOT", 1); + for (coreID = 0; coreID < cores_per_package; coreID++) { + char buffer[DEVICE_PATH_MAX]; + snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c", + '0' + coreID / 10, '0' + coreID % 10); + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(buffer); + acpigen_emit_byte(ARG0_OP); + } + acpigen_pop_len(); + } struct chip_operations cpu_intel_haswell_ops = { diff --git a/src/cpu/intel/haswell/acpi/cpu.asl b/src/cpu/intel/haswell/acpi/cpu.asl index a95c54a..3ee5265 100644 --- a/src/cpu/intel/haswell/acpi/cpu.asl +++ b/src/cpu/intel/haswell/acpi/cpu.asl @@ -14,84 +14,23 @@ * GNU General Public License for more details. */ -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) -External (\_PR.CP04, DeviceObj) -External (\_PR.CP05, DeviceObj) -External (\_PR.CP06, DeviceObj) -External (\_PR.CP07, DeviceObj) +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x81) // _CST - Notify (\_PR.CP05, 0x81) // _CST - Notify (\_PR.CP06, 0x81) // _CST - Notify (\_PR.CP07, 0x81) // _CST - } + \_PR.CNOT (0x81) } /* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ Method (PPCN) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) // _PPC - Notify (\_PR.CP01, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) // _PPC - Notify (\_PR.CP03, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x80) // _PPC - Notify (\_PR.CP05, 0x80) // _PPC - Notify (\_PR.CP06, 0x80) // _PPC - Notify (\_PR.CP07, 0x80) // _PPC - } + \_PR.CNOT (0x81) } /* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ Method (TNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) // _TPC - Notify (\_PR.CP01, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) // _TPC - Notify (\_PR.CP03, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x82) // _TPC - Notify (\_PR.CP05, 0x82) // _TPC - Notify (\_PR.CP06, 0x82) // _TPC - Notify (\_PR.CP07, 0x82) // _TPC - } -} - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (LGreaterEqual (\PCNT, 8)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03, - \_PR.CP04, \_PR.CP05, \_PR.CP06, \_PR.CP07}) - } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) - } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CP00, \_PR.CP01}) - } Else { - Return (Package() {\_PR.CP00}) - } -} + \_PR.CNOT (0x82) +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/29885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620 Gerrit-Change-Number: 29885 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/skylake: Rework acpi/cpu.asl
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29884 Change subject: soc/intel/skylake: Rework acpi/cpu.asl ...................................................................... soc/intel/skylake: Rework acpi/cpu.asl Change-Id: I182585fd09e4ce848c860d00eb612e8f5fdde35e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/cpu.asl 2 files changed, 20 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29884/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 6687ea1..db1b77b 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -550,6 +550,21 @@ acpigen_pop_len(); } } + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_method("\\_PR.CNOT", 1); + for (core_id = 0; core_id < cores_per_package; core_id++) { + char buffer[DEVICE_PATH_MAX]; + snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c", + '0' + core_id / 10, '0' + core_id % 10); + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(buffer); + acpigen_emit_byte(ARG0_OP); + } + acpigen_pop_len(); } static unsigned long acpi_fill_dmar(unsigned long current) diff --git a/src/soc/intel/skylake/acpi/cpu.asl b/src/soc/intel/skylake/acpi/cpu.asl index a202ceb..761c435 100644 --- a/src/soc/intel/skylake/acpi/cpu.asl +++ b/src/soc/intel/skylake/acpi/cpu.asl @@ -13,106 +13,23 @@ * GNU General Public License for more details. */ -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) -External (\_PR.CP04, DeviceObj) -External (\_PR.CP05, DeviceObj) -External (\_PR.CP06, DeviceObj) -External (\_PR.CP07, DeviceObj) +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x81) // _CST - Notify (\_PR.CP05, 0x81) // _CST - Notify (\_PR.CP06, 0x81) // _CST - Notify (\_PR.CP07, 0x81) // _CST - } + \_PR.CNOT (0x81) } /* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ Method (PPCN) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) // _PPC - Notify (\_PR.CP01, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) // _PPC - Notify (\_PR.CP03, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x80) // _PPC - Notify (\_PR.CP05, 0x80) // _PPC - Notify (\_PR.CP06, 0x80) // _PPC - Notify (\_PR.CP07, 0x80) // _PPC - } + \_PR.CNOT (0x81) } /* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ Method (TNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) // _TPC - Notify (\_PR.CP01, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) // _TPC - Notify (\_PR.CP03, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 8)) { - Notify (\_PR.CP04, 0x82) // _TPC - Notify (\_PR.CP05, 0x82) // _TPC - Notify (\_PR.CP06, 0x82) // _TPC - Notify (\_PR.CP07, 0x82) // _TPC - } -} - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (LGreaterEqual (\PCNT, 8)) { - Return (Package() - { - \_PR.CP00, - \_PR.CP01, - \_PR.CP02, - \_PR.CP03, - \_PR.CP04, - \_PR.CP05, - \_PR.CP06, - \_PR.CP07 - }) - } ElseIf (LGreaterEqual (\PCNT, 4)) { - Return (Package () - { - \_PR.CP00, - \_PR.CP01, - \_PR.CP02, - \_PR.CP03 - }) - } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package () - { - \_PR.CP00, - \_PR.CP01 - }) - } Else { - Return (Package () - { - \_PR.CP00 - }) - } + \_PR.CNOT (0x82) } -- To view, visit https://review.coreboot.org/c/coreboot/+/29884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I182585fd09e4ce848c860d00eb612e8f5fdde35e Gerrit-Change-Number: 29884 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/braswell/include/soc/iomap.h: Correct IO_BASE_SIZE and ...
by Patrick Georgi (Code Review) 28 Nov '18

28 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29392 ) Change subject: src/soc/intel/braswell/include/soc/iomap.h: Correct IO_BASE_SIZE and ILB_BASE_SIZE ...................................................................... src/soc/intel/braswell/include/soc/iomap.h: Correct IO_BASE_SIZE and ILB_BASE_SIZE The sizes of IO_BASE and ILB_BASE areas a incorrect. Correct IO_BASE_SIZE and ILB_BASE_SIZE values. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I23c3fd608598c5ec2271d393168ac4bf406772b4 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/29392 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/intel/braswell/include/soc/iomap.h 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/soc/intel/braswell/include/soc/iomap.h b/src/soc/intel/braswell/include/soc/iomap.h index c61983b..f49993e 100644 --- a/src/soc/intel/braswell/include/soc/iomap.h +++ b/src/soc/intel/braswell/include/soc/iomap.h @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,7 +36,7 @@ /* IO Memory */ #define IO_BASE_ADDRESS 0xfed80000 -#define IO_BASE_SIZE 0x4000 +#define IO_BASE_SIZE 0x40000 #define COMMUNITY_OFFSET_GPSOUTHWEST 0x00000 #define COMMUNITY_OFFSET_GPNORTH 0x08000 #define COMMUNITY_OFFSET_GPEAST 0x10000 @@ -43,7 +44,7 @@ /* Intel Legacy Block */ #define ILB_BASE_ADDRESS 0xfed08000 -#define ILB_BASE_SIZE 0x400 +#define ILB_BASE_SIZE 0x2000 /* SPI Bus */ #define SPI_BASE_ADDRESS 0xfed01000 -- To view, visit https://review.coreboot.org/c/coreboot/+/29392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23c3fd608598c5ec2271d393168ac4bf406772b4 Gerrit-Change-Number: 29392 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2018