coreboot-gerrit November 2018

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Add hook to fix up FSP-S
by Nico Huber (Code Review) 28 Nov '18

28 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29899 Change subject: drivers/intel/fsp2_0: Add hook to fix up FSP-S ...................................................................... drivers/intel/fsp2_0: Add hook to fix up FSP-S There may be bugs in one revision or another. Add a hook that is directly called after FSP-S to allow the platform to fix things up. Change-Id: I6e5a52752d757159f12a65dfa5d08ac5fd65c259 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/silicon_init.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/29899/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 5ed3801..dc3031e 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -72,6 +72,12 @@ struct mma_config_param *mma_cfg); /* + * Hook to fix settings made by FSP-S. Called directly after + * returning from the blob. + */ +void soc_fsp_silicon_init_fixups(void); + +/* * # DOCUMENTATION: * * This file defines the interface between coreboot and the FSP 2.0 wrapper diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 0670663..7f56533 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -24,6 +24,8 @@ struct fsp_header fsps_hdr; +__weak void soc_fsp_silicon_init_fixups(void) {} + static void do_silicon_init(struct fsp_header *hdr) { FSPS_UPD *upd, *supd; @@ -50,6 +52,7 @@ timestamp_add_now(TS_FSP_SILICON_INIT_START); post_code(POST_FSP_SILICON_INIT); status = silicon_init(upd); + soc_fsp_silicon_init_fixups(); timestamp_add_now(TS_FSP_SILICON_INIT_END); post_code(POST_FSP_SILICON_EXIT); -- To view, visit https://review.coreboot.org/c/coreboot/+/29899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e5a52752d757159f12a65dfa5d08ac5fd65c259 Gerrit-Change-Number: 29899 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common/lpc_lib: Add function to disable LPC Clock Run
by Nico Huber (Code Review) 28 Nov '18

28 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29898 Change subject: soc/intel/common/lpc_lib: Add function to disable LPC Clock Run ...................................................................... soc/intel/common/lpc_lib: Add function to disable LPC Clock Run Needed to fix up FSP-S bug on Apollo Lake. Change-Id: If09fee07debb1f0de840b0c0bd7a65d338665f7c Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/29898/1 diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index e7b844f..a600f52 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -97,6 +97,7 @@ void lpc_set_serirq_mode(enum serirq_mode mode); /* Enable CLKRUN_EN for power gating LPC. */ void lpc_enable_pci_clk_cntl(void); +void lpc_disable_pci_clkrun(void); /* * Setup I/O Decode Range Register for LPC * ComA Range 3F8h-3FFh [2:0] diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index d27f877..0f26545 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -301,3 +301,9 @@ { pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN); } + +void lpc_disable_pci_clkrun(void) +{ + const u8 pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL); + pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If09fee07debb1f0de840b0c0bd7a65d338665f7c Gerrit-Change-Number: 29898 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by Nico Huber (Code Review) 28 Nov '18

28 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29897 Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... util/inteltool: Add Apollo Lake GPIO groups and names Apollo Lake has four GPIO communities each with a single group named after the physical location of the pads (I guess): North West, North, West and South West. Also add some logic to be able to tag the default function of a pad (with an asterisk before its name). This seems easier to review in the tables, but we could also encode the number of the default explicitly instead. Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c 2 files changed, 353 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/29897/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index b4225a7..12b21c6 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1026,6 +1026,7 @@ break; case PCI_DEVICE_ID_INTEL_B150: case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_APL_LPC: print_gpio_groups(sb); return 0; case PCI_DEVICE_ID_INTEL_82371XX: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 2bb4edc..fed5b74 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -39,6 +39,345 @@ const struct gpio_group *const *groups; }; +/* + * Names prefixed with an *asterisk are the default. + * (if it's the first column, GPIO is the default, no matter the name) + */ + +static const char *const apl_group_north_names[] = { + "*GPIO_0", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_1", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_2", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_3", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_4", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_5", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_6", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_7", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_8", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_9", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_10", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_11", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_12", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_13", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_14", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_15", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_16", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_17", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_18", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_19", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_20", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_21", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_22", "n/a", "n/a", "n/a", "n/a", "SATA_GP0", + "*GPIO_23", "n/a", "n/a", "n/a", "n/a", "SATA_GP1", + "*GPIO_24", "n/a", "n/a", "n/a", "n/a", "SATA_DEVSLP0", + "*GPIO_25", "n/a", "n/a", "n/a", "n/a", "SATA_DEVSLP1", + "*GPIO_26", "n/a", "n/a", "n/a", "n/a", "SATA_LEDN", + "*GPIO_27", "n/a", "n/a", "n/a", "n/a", "n/a", + "*GPIO_28", "n/a", "ISH_GPIO_10", "n/a", "n/a", "n/a", + "*GPIO_29", "n/a", "ISH_GPIO_11", "n/a", "n/a", "n/a", + "*GPIO_30", "ISH_GPIO_12", "n/a", "n/a", "n/a", "n/a", + "*GPIO_31", "ISH_GPIO_13", "n/a", "n/a", "n/a", "SUSCLK1", + "*GPIO_32", "ISH_GPIO_14", "n/a", "n/a", "n/a", "SUSCLK2", + "*GPIO_33", "ISH_GPIO_15", "n/a", "n/a", "n/a", "SUSCLK3", + "*GPIO_34", "PWM0", "n/a", "n/a", "n/a", "n/a", + "*GPIO_35", "PWM1", "n/a", "n/a", "n/a", "n/a", + "*GPIO_36", "PWM2", "n/a", "n/a", "n/a", "n/a", + "*GPIO_37", "PWM3", "n/a", "n/a", "n/a", "n/a", + "*GPIO_38", "LPSS_UART0_RXD", "n/a", "n/a", "n/a", "n/a", + "*GPIO_39", "LPSS_UART0_TXD", "n/a", "n/a", "n/a", "n/a", + "*GPIO_40", "LPSS_UART0_RTS_N", "n/a", "n/a", "n/a", "n/a", + "*GPIO_41", "LPSS_UART0_CTS_N", "n/a", "n/a", "n/a", "n/a", + "*GPIO_42", "LPSS_UART1_RXD", "n/a", "n/a", "n/a", "n/a", + "*GPIO_43", "LPSS_UART1_TXD", "n/a", "n/a", "n/a", "n/a", + "*GPIO_44", "LPSS_UART1_RTS_N", "n/a", "n/a", "n/a", "n/a", + "*GPIO_45", "LPSS_UART1_CTS_N", "n/a", "n/a", "n/a", "n/a", + "*GPIO_46", "LPSS_UART2_RXD", "n/a", "n/a", "n/a", "n/a", + "*GPIO_47", "LPSS_UART2_TXD", "n/a", "n/a", "n/a", "n/a", + "*GPIO_48", "LPSS_UART2_RTS_N", "n/a", "n/a", "n/a", "n/a", + "*GPIO_49", "LPSS_UART2_CTS_N", "n/a", "n/a", "n/a", "n/a", + "*GPIO_62", "GP_CAMERASB0", "n/a", "n/a", "n/a", "n/a", + "*GPIO_63", "GP_CAMERASB1", "n/a", "n/a", "n/a", "n/a", + "*GPIO_64", "GP_CAMERASB2", "n/a", "n/a", "n/a", "n/a", + "*GPIO_65", "GP_CAMERASB3", "n/a", "n/a", "n/a", "n/a", + "*GPIO_66", "GP_CAMERASB4", "n/a", "n/a", "n/a", "n/a", + "*GPIO_67", "GP_CAMERASB5", "n/a", "n/a", "n/a", "n/a", + "*GPIO_68", "GP_CAMERASB6", "n/a", "n/a", "n/a", "n/a", + "*GPIO_69", "GP_CAMERASB7", "n/a", "n/a", "n/a", "n/a", + "*GPIO_70", "GP_CAMERASB8", "n/a", "n/a", "n/a", "n/a", + "*GPIO_71", "GP_CAMERASB9", "n/a", "n/a", "n/a", "n/a", + "*GPIO_72", "GP_CAMERASB10","n/a", "n/a", "n/a", "n/a", + "*GPIO_73", "GP_CAMERASB11","n/a", "n/a", "n/a", "n/a", + "JTAG_TCK", "*JTAG_TCK", "n/a", "n/a", "n/a", "n/a", + "JTAG_TRST_B", "*JTAG_TRST_N", "n/a", "n/a", "n/a", "n/a", + "JTAG_TMS", "*JTAG_TMS", "n/a", "n/a", "n/a", "n/a", + "JTAG_TDI", "*JTAG_TDI", "n/a", "n/a", "n/a", "n/a", + "JTAG_PMODE", "*JTAG_PMODE", "n/a", "n/a", "n/a", "n/a", + "JTAG_PREQ_B", "*JTAG_PREQ_N", "n/a", "n/a", "n/a", "n/a", + "JTAGX" , "*JTAGX", "n/a", "n/a", "n/a", "n/a", + "JTAG_PRDY_B", "*JTAG_PRDY_N", "n/a", "n/a", "n/a", "n/a", + "JTAG_TDO", "*JTAG_TDO", "n/a", "n/a", "n/a", "n/a", + "CNV_BRI_DT", "*GPIO_216", "n/a", "n/a", "n/a", "n/a", + "CNV_BRI_RSP", "*GPIO_217", "n/a", "n/a", "n/a", "n/a", + "CNV_RGI_DT", "*GPIO_218", "n/a", "n/a", "n/a", "n/a", + "CNV_RGI_RSP", "*n/a", "n/a", "n/a", "n/a", "n/a", + "SVID0_ALERT_B","*SVID0_ALERT_N","n/a", "n/a", "n/a", "n/a", + "SVID0_DATA", "*SVID0_DATA", "n/a", "n/a", "n/a", "n/a", + "SVID0_CLK", "*SVID0_CLK", "n/a", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group apl_group_north = { + .display = "------- GPIO Group North -------", + .pad_count = ARRAY_SIZE(apl_group_north_names) / 6, + .func_count = 6, + .pad_names = apl_group_north_names, +}; + +static const struct gpio_group *const apl_community_north_groups[] = { + &apl_group_north, +}; + +static const struct gpio_community apl_community_north = { + .name = "----- GPIO Community North -----", + .pcr_port_id = 0xc5, + .group_count = ARRAY_SIZE(apl_community_north_groups), + .groups = apl_community_north_groups, +}; + +static const char *const apl_group_northwest_names[] = { + "GPIO_187", "*DDI0_DDC_SDA", "n/a", "n/a", + "GPIO_188", "*DDI0_DDC_SCL", "n/a", "n/a", + "GPIO_189", "*DDI1_DDC_SDA", "n/a", "n/a", + "GPIO_190", "*DDI1_DDC_SCL", "n/a", "n/a", + "GPIO_191", "*MIPI_I2C_SDA", "n/a", "n/a", + "GPIO_192", "*MIPI_I2C_SCL", "n/a", "n/a", + "GPIO_193", "*PNL0_VDDEN", "n/a", "n/a", + "GPIO_194", "*PNL0_BKLTEN", "n/a", "n/a", + "GPIO_195", "*PNL0_BKLTCTL", "n/a", "n/a", + "GPIO_196", "*PNL1_VDDEN", "n/a", "n/a", + "GPIO_197", "*PNL1_BKLTEN", "n/a", "n/a", + "GPIO_198", "*PNL1_BKLTCTL", "n/a", "n/a", + "GPIO_199", "*GPIO_199", "DDI1_HPD", "n/a", + "GPIO_200", "*GPIO_200", "DDI0_HPD", "n/a", + "GPIO_201", "*MDSI_A_TE", "n/a", "n/a", + "GPIO_202", "*MDSI_C_TE", "n/a", "n/a", + "GPIO_203", "*USB_OC0_N", "n/a", "n/a", + "GPIO_204", "*USB_OC1_N", "n/a", "n/a", + "PMC_SPI_FS0", "*PMC_SPI_FS0", "n/a", "n/a", + "PMC_SPI_FS1", "*PMC_SPI_FS1", "DDI2_HPD", "n/a", + "PMC_SPI_FS2", "*PMC_SPI_FS2", "FST_SPI_CS2_N","n/a", + "PMC_SPI_RXD", "*PMC_SPI_RXD", "n/a", "n/a", + "PMC_SPI_TXD", "*PMC_SPI_TXD", "n/a", "n/a", + "PMC_SPI_CLK", "*PMC_SPI_CLK", "n/a", "n/a", + "PMIC_PWRGOOD", "*n/a", "n/a", "n/a", + "PMIC_RESET_B", "*GPIO_223", "n/a", "n/a", + "GPIO_213", "*GPIO_213", "n/a", "n/a", + "GPIO_214", "*GPIO_214", "n/a", "n/a", + "GPIO_215", "*GPIO_215", "n/a", "n/a", + "PMIC_THERMTRIP_B", "*THERMTRIP_N", "n/a", "n/a", + "PMIC_STDBY", "*GPIO_224", "n/a", "n/a", + "PROCHOT_B", "*PROCHOT_N", "n/a", "n/a", + "PMIC_I2C_SCL", "*PMIC_I2C_SCL", "n/a", "n/a", + "PMIC_I2C_SDA", "*PMIC_I2C_SDA", "n/a", "n/a", + "*GPIO_74", "AVS_I2S1_MCLK" , "n/a", "n/a", + "*GPIO_75", "AVS_I2S1_BCLK", "n/a", "n/a", + "*GPIO_76", "AVS_I2S1_WS_SYNC", "n/a", "n/a", + "*GPIO_77", "AVS_I2S1_SDI", "n/a", "n/a", + "*GPIO_78", "AVS_I2S1_SDO", "n/a", "n/a", + "*GPIO_79", "AVS_DMIC_CLK_A1", "AVS_I2S4_BCLK","n/a", + "*GPIO_80", "AVS_DMIC_CLK_B1", "AVS_I2S4_WS_SYNC","n/a", + "*GPIO_81", "AVS_DMIC_DATA_1", "AVS_I2C4_SDI", "n/a", + "*GPIO_82", "AVS_DMIC_CLK_AB2", "AVS_I2S4_SDO", "n/a", + "*GPIO_83", "AVS_DMIC_DATA_2", "n/a", "n/a", + "*GPIO_84", "AVS_I2S2_MCLK", "AVS_HDA_RST_N","n/a", + "*GPIO_85", "AVS_I2S2_BCLK", "n/a", "n/a", + "*GPIO_86", "AVS_I2S2_WS_SYNC", "n/a", "n/a", + "*GPIO_87", "AVS_I2S2_SDI", "n/a", "n/a", + "*GPIO_88", "AVS_I2S2_SDO", "n/a", "n/a", + "*GPIO_89", "AVS_I2S3_BCLK", "n/a", "n/a", + "*GPIO_90", "AVS_I2S3_WS_SYNC", "n/a", "n/a", + "*GPIO_91", "AVS_I2S3_SDI", "n/a", "n/a", + "*GPIO_92", "AVS_I2S3_SDO", "n/a", "n/a", + "GPIO_97", "*FST_SPI_CS0_N", "n/a", "n/a", + "GPIO_98", "*FST_SPI_CS1_N", "n/a", "n/a", + "GPIO_99", "*FST_SPI_MOSI_IO0", "n/a", "n/a", + "GPIO_100", "*FST_SPI_MISO_IO1", "n/a", "n/a", + "GPIO_101", "*FST_SPI_IO2", "n/a", "n/a", + "GPIO_102", "*FST_SPI_IO3", "n/a", "n/a", + "GPIO_103", "*FST_SPI_CLK", "n/a", "n/a", + "FST_SPI_CLK_FB", "*n/a", "n/a", "n/a", + "*GPIO_104", "SIO_SPI_0_CLK", "n/a", "n/a", + "*GPIO_105", "SIO_SPI_0_FS0", "n/a", "n/a", + "*GPIO_106", "SIO_SPI_0_FS1", "n/a", "FST_SPI_CS2_N", + "*GPIO_109", "SIO_SPI_0_RXD", "n/a", "n/a", + "*GPIO_110", "SIO_SPI_0_TXD", "n/a", "n/a", + "*GPIO_111", "SIO_SPI_1_CLK", "n/a", "n/a", + "*GPIO_112", "SIO_SPI_1_FS0", "n/a", "n/a", + "*GPIO_113", "SIO_SPI_1_FS1", "n/a", "n/a", + "*GPIO_116", "SIO_SPI_1_RXD", "n/a", "n/a", + "*GPIO_117", "SIO_SPI_1_TXD", "n/a", "n/a", + "*GPIO_118", "SIO_SPI_2_CLK", "n/a", "n/a", + "*GPIO_119", "SIO_SPI_2_FS0", "n/a", "n/a", + "*GPIO_120", "SIO_SPI_2_FS1", "n/a", "n/a", + "*GPIO_121", "SIO_SPI_2_FS2", "n/a", "n/a", + "*GPIO_122", "SIO_SPI_2_RXD", "n/a", "n/a", + "*GPIO_123", "SIO_SPI_2_TXD", "n/a", "n/a", +}; + +static const struct gpio_group apl_group_northwest = { + .display = "----- GPIO Group NorthWest -----", + .pad_count = ARRAY_SIZE(apl_group_northwest_names) / 4, + .func_count = 4, + .pad_names = apl_group_northwest_names, +}; + +static const struct gpio_group *const apl_community_northwest_groups[] = { + &apl_group_northwest, +}; + +static const struct gpio_community apl_community_northwest = { + .name = "--- GPIO Community NorthWest ---", + .pcr_port_id = 0xc4, + .group_count = ARRAY_SIZE(apl_community_northwest_groups), + .groups = apl_community_northwest_groups, +}; + +static const char *const apl_group_southwest_names[] = { + "*GPIO_205", "PCIE_WAKE0_N", "n/a", + "*GPIO_206", "PCIE_WAKE1_N", "n/a", + "*GPIO_207", "PCIE_WAKE2_N", "n/a", + "*GPIO_208", "PCIE_WAKE3_N", "n/a", + "GPIO_156", "*EMMC_CLK", "n/a", + "GPIO_157", "*EMMC_D0", "n/a", + "GPIO_158", "*EMMC_D1", "n/a", + "GPIO_159", "*EMMC_D2", "n/a", + "GPIO_160", "*EMMC_D3", "n/a", + "GPIO_161", "*EMMC_D4", "n/a", + "GPIO_162", "*EMMC_D5", "n/a", + "GPIO_163", "*EMMC_D6", "n/a", + "GPIO_164", "*EMMC_D7", "n/a", + "GPIO_165", "*EMMC_CMD", "n/a", + "*GPIO_166", "GPIO_166", "n/a", + "*GPIO_167", "GPIO_167", "n/a", + "*GPIO_168", "GPIO_168", "n/a", + "*GPIO_169", "GPIO_169", "n/a", + "*GPIO_170", "GPIO_170", "n/a", + "*GPIO_171", "GPIO_171", "n/a", + "*GPIO_172", "SDCARD_CLK", "n/a", + "*GPIO_179", "n/a", "n/a", + "*GPIO_173", "SDCARD_D0", "n/a", + "*GPIO_174", "SDCARD_D1", "n/a", + "*GPIO_175", "SDCARD_D2", "n/a", + "*GPIO_176", "SDCARD_D3", "n/a", + "*GPIO_177", "SDCARD_CD_B", "n/a", + "*GPIO_178", "SDCARD_CMD", "n/a", + "*GPIO_186", "SDCARD_LVL_WP", "n/a", + "GPIO_182", "*EMMC_RCLK", "n/a", + "GPIO_183", "GPIO_183", "n/a", + "*SMB_ALERTB", "SMB_ALERT_N", "n/a", + "*SMB_CLK", "SMB_CLK", "LPSS_I2C7_SCL", + "*SMB_DATA", "SMB_DATA", "LPSS_I2C7_SDA", + "*LPC_ILB_SERIRQ", "LPC_ILB_SERIRQ", "n/a", + "*LPC_CLKOUT0", "LPC_CLKOUT0", "n/a", + "*LPC_CLKOUT1", "LPC_CLKOUT1", "n/a", + "*LPC_AD0", "LPC_AD0", "n/a", + "*LPC_AD1", "LPC_AD1", "n/a", + "*LPC_AD2", "LPC_AD2", "n/a", + "*LPC_AD3", "LPC_AD3", "n/a", + "*LPC_CLKRUNB", "LPC_CLKRUNB", "n/a", + "*LPC_FRAMEB", "LPC_FRAMEB", "n/a", +}; + +static const struct gpio_group apl_group_southwest = { + .display = "----- GPIO Group SouthWest -----", + .pad_count = ARRAY_SIZE(apl_group_southwest_names) / 3, + .func_count = 3, + .pad_names = apl_group_southwest_names, +}; + +static const struct gpio_group *const apl_community_southwest_groups[] = { + &apl_group_southwest, +}; + +static const struct gpio_community apl_community_southwest = { + .name = "--- GPIO Community SouthWest ---", + .pcr_port_id = 0xc0, + .group_count = ARRAY_SIZE(apl_community_southwest_groups), + .groups = apl_community_southwest_groups, +}; + +static const char *const apl_group_west_names[] = { + "*GPIO_124", "LPSS_I2C0_SDA", "n/a", "n/a", + "*GPIO_125", "LPSS_I2C0_SCL", "n/a", "n/a", + "*GPIO_126", "LPSS_I2C1_SDA", "n/a", "n/a", + "*GPIO_127", "LPSS_I2C1_SCL", "n/a", "n/a", + "*GPIO_128", "LPSS_I2C2_SDA", "n/a", "n/a", + "*GPIO_129", "LPSS_I2C2_SCL", "n/a", "n/a", + "*GPIO_130", "LPSS_I2C3_SDA", "n/a", "n/a", + "*GPIO_131", "LPSS_I2C3_SCL", "n/a", "n/a", + "*GPIO_132", "LPSS_I2C4_SDA", "n/a", "n/a", + "*GPIO_133", "LPSS_I2C4_SCL", "n/a", "n/a", + "*GPIO_134", "LPSS_I2C5_SDA","ISH_I2C0_SDA", "n/a", + "*GPIO_135", "LPSS_I2C5_SCL","ISH_I2C0_SCL", "n/a", + "*GPIO_136", "LPSS_I2C6_SDA","ISH_I2C1_SDA", "n/a", + "*GPIO_137", "LPSS_I2C6_SCL","ISH_I2C1_SCL", "n/a", + "*GPIO_138", "LPSS_I2C7_SDA","ISH_I2C2_SDA", "n/a", + "*GPIO_139", "LPSS_I2C7_SCL","ISH_I2C2_SCL", "n/a", + "*GPIO_146", "ISH_GPIO_0", "AVS_I2S6_BCLK", "AVS_HDA_BCLK", + "*GPIO_147", "ISH_GPIO_1", "AVS_I2S6_WS_SYNC", "AVS_HDA_WS_SYNC", + "*GPIO_148", "ISH_GPIO_2", "AVS_I2S6_SDI", "AVS_HDA_SDI", + "*GPIO_149", "ISH_GPIO_3", "AVS_I2S6_SDO", "AVS_HDA_SDO", + "*GPIO_150", "ISH_GPIO_4", "AVS_I2S5_BLK", "LPSS_UART2_RXD", + "*GPIO_151", "ISH_GPIO_5", "AVS_I2S5_WS_SYNC", "LPSS_UART2_TXD", + "*GPIO_152", "ISH_GPIO_6", "AVS_I2S5_SDI", "LPSS_UART2_RTS_B", + "*GPIO_153", "ISH_GPIO_7", "AVS_I2S5_SDO", "LPSS_UART2_CTS_B", + "*GPIO_154", "ISH_GPIO_8", "n/a", "n/a", + "*GPIO_155", "ISH_GPIO_9", "SPKR", "n/a", + "GPIO_209", "*PCIE_CLKREQ0_N", "MODEM_CLK_REQ","n/a", + "GPIO_210", "*PCIE_CLKREQ1_N", "n/a", "n/a", + "GPIO_211", "*PCIE_CLKREQ2_N", "n/a", "n/a", + "GPIO_212", "*PCIE_CLKREQ3_N", "n/a", "n/a", + "OSC_CLK_OUT_0","*OSC_CLK_OUT_0", "n/a", "n/a", + "OSC_CLK_OUT_1","*OSC_CLK_OUT_1", "n/a", "n/a", + "OSC_CLK_OUT_2","*OSC_CLK_OUT_2", "n/a", "n/a", + "OSC_CLK_OUT_3","*OSC_CLK_OUT_3", "n/a", "n/a", + "OSC_CLK_OUT_4","*OSC_CLK_OUT_4", "n/a", "n/a", + "*PMU_AC_PRESENT","PMU_AC_PRESENT", "n/a", "n/a", + "PMU_BATLOW_B", "*PMU_BATLOW_N", "n/a", "n/a", + "PMU_PLTRST_B", "*PMU_PLTRST_N", "n/a", "n/a", + "PMU_PWRBTN_B", "*PMU_PWRBTN_N", "n/a", "n/a", + "PMU_RSTBTN_B", "*PMU_RSTBTN_N", "n/a", "n/a", + "PMU_SLP_S0_B", "*PMU_SLP_S0_N", "n/a", "n/a", + "PMU_SLP_S3_B", "*PMU_SLP_S3_N", "n/a", "n/a", + "PMU_SLP_S4_B", "*PMU_SLP_S4_N", "n/a", "n/a", + "PMU_SUSCLK", "*PMU_SUSCLK", "n/a", "n/a", + "*PMU_WAKE_B", "PMU_WAKE_B/EMMC_PWR_EN_N","n/a", "n/a", + "SUS_STAT_B", "*SUS_STAT_B", "n/a", "n/a", + "SUSPWRDNACK", "*SUSPWRDNACK", "n/a", "n/a", +}; + +static const struct gpio_group apl_group_west = { + .display = "-------- GPIO Group West -------", + .pad_count = ARRAY_SIZE(apl_group_west_names) / 4, + .func_count = 4, + .pad_names = apl_group_west_names, +}; + +static const struct gpio_group *const apl_community_west_groups[] = { + &apl_group_west, +}; + +static const struct gpio_community apl_community_west = { + .name = "------ GPIO Community West -----", + .pcr_port_id = 0xc7, + .group_count = ARRAY_SIZE(apl_community_west_groups), + .groups = apl_community_west_groups, +}; + +static const struct gpio_community *const apl_communities[] = { + &apl_community_north, &apl_community_northwest, + &apl_community_southwest, &apl_community_west, +}; + static const char *const sunrise_group_a_names[] = { "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", "GPP_A1", "LAD0", "n/a", "ESPI_IO0", @@ -397,8 +736,11 @@ const size_t pad, const uint32_t dw0) { const size_t pad_mode = dw0 >> 10 & 7; + const char *const pad_name = + group->pad_names[pad * group->func_count + pad_mode]; + if (!pad_mode) - return "GPIO"; + return pad_name[0] == '*' ? "*GPIO" : "GPIO"; else if (pad_mode < group->func_count) return group->pad_names[pad * group->func_count + pad_mode]; else @@ -415,10 +757,12 @@ for (p = 0; p < group->pad_count; ++p, pad_cfg += 8) { const uint32_t dw0 = read_pcr32(pid, pad_cfg); const uint32_t dw1 = read_pcr32(pid, pad_cfg + 4); + const char *const pad_name = + group->pad_names[p * group->func_count]; - printf("0x%04zx: 0x%016"PRIx64" %-8s %-20s\n", pad_cfg, + printf("0x%04zx: 0x%016"PRIx64" %-12s %-20s\n", pad_cfg, (uint64_t)dw1 << 32 | dw0, - group->pad_names[p * group->func_count], + pad_name[0] == '*' ? &pad_name[1] : pad_name, decode_pad_mode(group, p, dw0)); } } @@ -460,6 +804,11 @@ communities = sunrise_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_APL_LPC: + community_count = ARRAY_SIZE(apl_communities); + communities = apl_communities; + pcr_init(sb); + break; default: return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/inteltool: Add Apollo Lake LPC ID and allow to read PCRs
by Nico Huber (Code Review) 28 Nov '18

28 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29896 Change subject: util/inteltool: Add Apollo Lake LPC ID and allow to read PCRs ...................................................................... util/inteltool: Add Apollo Lake LPC ID and allow to read PCRs The P2SB (PCI to Side-Band) bridge is on a different PCI device on APL. Hence, we have to decide based on the LPC ID which device to query. Also fix a comment. Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 3 files changed, 31 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/29896/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index d0b4279..6966915 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -247,6 +247,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"}, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" }, /* Intel GPUs */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS, "Intel(R) G35 Express Chipset Family" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 5de73aa..f232135 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -227,6 +227,8 @@ #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX 0x0f31 #define CPUID_BAYTRAIL 0x30670 +#define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 + /* Intel starts counting these generations with the integration of the DRAM controller */ #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index 7223e19..4e75905 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -70,11 +70,36 @@ { bool error_exit = false; bool p2sb_revealed = false; + struct pci_dev *p2sb; if (sbbar) return; - struct pci_dev *const p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); + switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE: + case PCI_DEVICE_ID_INTEL_H110: + case PCI_DEVICE_ID_INTEL_H170: + case PCI_DEVICE_ID_INTEL_Z170: + case PCI_DEVICE_ID_INTEL_Q170: + case PCI_DEVICE_ID_INTEL_Q150: + case PCI_DEVICE_ID_INTEL_B150: + case PCI_DEVICE_ID_INTEL_C236: + case PCI_DEVICE_ID_INTEL_C232: + case PCI_DEVICE_ID_INTEL_QM170: + case PCI_DEVICE_ID_INTEL_HM170: + case PCI_DEVICE_ID_INTEL_CM236: + case PCI_DEVICE_ID_INTEL_HM175: + case PCI_DEVICE_ID_INTEL_QM175: + case PCI_DEVICE_ID_INTEL_CM238: + p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); + break; + case PCI_DEVICE_ID_INTEL_APL_LPC: + p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0); + break; + default: + perror("Unknown LPC device."); + exit(1); + } if (!p2sb) { perror("Can't allocate device node for P2SB."); @@ -86,8 +111,8 @@ if (p2sb->vendor_id == 0xffff && p2sb->device_id == 0xffff) { printf("Trying to reveal Primary to Sideband Bridge " "(P2SB),\nlet's hope the OS doesn't mind... "); - /* Do not use pci_write_long(). Surrounding - bytes 0xe0 must be maintained. */ + /* Do not use pci_write_long(). Bytes + surrounding 0xe0 must be maintained. */ pci_write_byte(p2sb, 0xe0 + 1, 0); pci_fill_info(p2sb, PCI_FILL_IDENT | PCI_FILL_RESCAN); -- To view, visit https://review.coreboot.org/c/coreboot/+/29896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a Gerrit-Change-Number: 29896 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86/acpigen.c: Add a method to notify all CPU cores
by Nico Huber (Code Review) 28 Nov '18

28 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29895 ) Change subject: arch/x86/acpigen.c: Add a method to notify all CPU cores ...................................................................... Patch Set 3: Code-Review+2 (2 comments) https://review.coreboot.org/#/c/29895/3/src/arch/x86/acpigen.c File src/arch/x86/acpigen.c: https://review.coreboot.org/#/c/29895/3/src/arch/x86/acpigen.c@349 PS3, Line 349: unsigned hmmm? https://review.coreboot.org/#/c/29895/3/src/arch/x86/acpigen.c@381 PS3, Line 381: core_id); Don't tell it would have fit a single line with `coreID` :-/ OTOH, once we got rid of all the static ASL code, there shouldn't be a need for CONFIG_ACPI_CPU_STRING anymore... -- To view, visit https://review.coreboot.org/c/coreboot/+/29895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf Gerrit-Change-Number: 29895 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 14:47:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/acpigen.c: Add a method to notify all CPU cores
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Hello Patrick Rudolph, Felix Held, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29895 to look at the new patch set (#3). Change subject: arch/x86/acpigen.c: Add a method to notify all CPU cores ...................................................................... arch/x86/acpigen.c: Add a method to notify all CPU cores Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/acpigen.c M src/arch/x86/include/arch/acpigen.h M src/cpu/intel/speedstep/acpi.c 3 files changed, 19 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/29895/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf Gerrit-Change-Number: 29895 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86/acpigen.c: Add a method to notify all CPU cores
by Nico Huber (Code Review) 28 Nov '18

28 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29895 ) Change subject: arch/x86/acpigen.c: Add a method to notify all CPU cores ...................................................................... Patch Set 2: Code-Review-1 (3 comments) https://review.coreboot.org/#/c/29895/2/src/arch/x86/acpigen.c File src/arch/x86/acpigen.c: https://review.coreboot.org/#/c/29895/2/src/arch/x86/acpigen.c@375 PS2, Line 375: int coreID; I know it might have been me who named it like that... but give it a proper identifier? e.g. core_id? https://review.coreboot.org/#/c/29895/2/src/arch/x86/acpigen.c@377 PS2, Line 377: \\_PR. NB. Why the absolute path? At some point we might want to just ensure that these functions are called in the proper scope. CONFIG_ACPI_CPU_ STRING would have to change too... https://review.coreboot.org/#/c/29895/2/src/arch/x86/acpigen.c@380 PS2, Line 380: snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c", : '0' + coreID / 10, '0' + coreID % 10); snprintf(buffer, sizeof(buffer), CONFIG_ACPI_CPU_STRING, coreID); -- To view, visit https://review.coreboot.org/c/coreboot/+/29895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf Gerrit-Change-Number: 29895 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 14:05:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/acpigen.c: Add a method to notify all CPU cores
by Felix Held (Code Review) 28 Nov '18

28 Nov '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29895 ) Change subject: arch/x86/acpigen.c: Add a method to notify all CPU cores ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf Gerrit-Change-Number: 29895 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 13:28:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/acpigen.c: Add a method to notify all CPU cores
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29895 to look at the new patch set (#2). Change subject: arch/x86/acpigen.c: Add a method to notify all CPU cores ...................................................................... arch/x86/acpigen.c: Add a method to notify all CPU cores Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/acpigen.c M src/arch/x86/include/arch/acpigen.h M src/cpu/intel/speedstep/acpi.c 3 files changed, 19 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/29895/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf Gerrit-Change-Number: 29895 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/baytrail: Rework acpi/cpu.asl
by build bot (Jenkins) (Code Review) 28 Nov '18

28 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29888 ) Change subject: soc/intel/baytrail: Rework acpi/cpu.asl ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29888/2/src/soc/intel/baytrail/acpi.c File src/soc/intel/baytrail/acpi.c: https://review.coreboot.org/#/c/29888/2/src/soc/intel/baytrail/acpi.c@450 PS2, Line 450: for (core=0; core < pattrs->num_cpus; core++) { spaces required around that '=' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/29888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb5a5c1255f9a922063293bf430e849909468eaf Gerrit-Change-Number: 29888 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 28 Nov 2018 12:37:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2018