coreboot-gerrit November 2018

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Change in ...coreboot[master]: hostevent: Enable lazy events for SCI mask
by Jenny Tc (Code Review) 28 Nov '18

28 Nov '18

Jenny Tc has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29774 ) Change subject: hostevent: Enable lazy events for SCI mask ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/29774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff3aea2e7f11f1196d8d9ece03ae000354e884b Gerrit-Change-Number: 29774 Gerrit-PatchSet: 2 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 28 Nov 2018 17:23:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI
by Jenny Tc (Code Review) 28 Nov '18

28 Nov '18

Jenny Tc has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29775 ) Change subject: SMI: Introduce CONFIG_SOC_INTEL_BYPASS_PORT_B2_SMI ...................................................................... Abandoned Merged with CL https://review.coreboot.org/c/coreboot/+/29774 -- To view, visit https://review.coreboot.org/c/coreboot/+/29775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ca93972fa4d870632707cb9a9e74ab80cbd5d5 Gerrit-Change-Number: 29775 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mainboard/lenovo/t530/thermal.h: adjust W530 junction temperature
by Philipp Deppenwiese (Code Review) 28 Nov '18

28 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29822 ) Change subject: mainboard/lenovo/t530/thermal.h: adjust W530 junction temperature ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib13d4d7c3f710b7e353bbedefd30f2ee300a01f9 Gerrit-Change-Number: 29822 Gerrit-PatchSet: 9 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Hellsenberg <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 17:20:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: payloads/external/SeaBIOS/Kconfig: relax native VGA dependency
by Philipp Deppenwiese (Code Review) 28 Nov '18

28 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29823 ) Change subject: payloads/external/SeaBIOS/Kconfig: relax native VGA dependency ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3a219c2dc2133c3328192840538f0fbd1ed935a Gerrit-Change-Number: 29823 Gerrit-PatchSet: 4 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 17:20:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: hostevent: Enable lazy events for SCI mask
by Jenny Tc (Code Review) 28 Nov '18

28 Nov '18

Hello dhaval v sharma, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29774 to look at the new patch set (#2). Change subject: hostevent: Enable lazy events for SCI mask ...................................................................... hostevent: Enable lazy events for SCI mask With Lazy SCI events, dependancy on SMI handler for setting SCI events during boot can be avoided. On boot, coreboot notifies the SCI Lazy mask to EC. Once the EC driver is up in OS, it can notify the EC to convert SCI mask to ACTIVE SCI mask. Change-Id: I6ff3aea2e7f11f1196d8d9ece03ae000354e884b Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_commands.h M src/ec/google/chromeec/smihandler.c 4 files changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29774/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff3aea2e7f11f1196d8d9ece03ae000354e884b Gerrit-Change-Number: 29774 Gerrit-PatchSet: 2 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security/tpm: Move TPM2 NVRAM specific settings
by Philipp Deppenwiese (Code Review) 28 Nov '18

28 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29326 ) Change subject: security/tpm: Move TPM2 NVRAM specific settings ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/29326/5/src/security/tpm/tss/tcg-2.0/tss_st… File src/security/tpm/tss/tcg-2.0/tss_structures.h: https://review.coreboot.org/#/c/29326/5/src/security/tpm/tss/tcg-2.0/tss_st… PS5, Line 161: 0x94, 0x46, 0x62, 0x26, 0x68, 0x8E, 0xEE, 0xE6, 0x6A, 0xA1}; > What is this? how is this related to NVRAM? NVRAM policy https://review.coreboot.org/#/c/29326/5/src/security/vboot/secdata_tpm.c File src/security/vboot/secdata_tpm.c: https://review.coreboot.org/#/c/29326/5/src/security/vboot/secdata_tpm.c@41 PS5, Line 41: > missing include for tss_structures. […] Already exposed through tss.h -> tspi.h -- To view, visit https://review.coreboot.org/c/coreboot/+/29326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec9d1c272ed8d0872c9bbc406e98a19ac7a376bd Gerrit-Change-Number: 29326 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 28 Nov 2018 17:16:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/fit: Make FIT microcode updates selectable
by Philipp Deppenwiese (Code Review) 28 Nov '18

28 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29863 ) Change subject: cpu/intel/fit: Make FIT microcode updates selectable ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29863/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29863/2//COMMIT_MSG@7 PS2, Line 7: Make FIT microcode updates selectable > Can't you increase the number of FIT entries? @Aaron No they are done afterward. @Arthuer No they are hard defined by the SoC itself. For old platforms 4 entries are the maximum -- To view, visit https://review.coreboot.org/c/coreboot/+/29863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7da926943aef89e49e98d0b990ab46f5f8200e6e Gerrit-Change-Number: 29863 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 28 Nov 2018 17:06:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]mb/intel/x200: Add data.vbt
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29904 ) Change subject: [WIP]mb/intel/x200: Add data.vbt ...................................................................... Patch Set 1: Untested Is this really worth it? Linux does not seem to care anyway... -- To view, visit https://review.coreboot.org/c/coreboot/+/29904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4a7011ce03cdd511fa2e2160c2f006ba2707ba Gerrit-Change-Number: 29904 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 16:35:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]mb/intel/x200: Add data.vbt
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Hello Alexander Couzens, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29904 to look at the new patch set (#2). Change subject: [WIP]mb/intel/x200: Add data.vbt ...................................................................... [WIP]mb/intel/x200: Add data.vbt There are 2 vendor BIOS's for the Lenovo X200 with the difference being the settings in the VBT blob to accommodate different backlight frequencies. Linux however sticks with the setting set by the firmware. Change-Id: I4c4a7011ce03cdd511fa2e2160c2f006ba2707ba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/Makefile.inc M src/mainboard/lenovo/x200/blc.c A src/mainboard/lenovo/x200/data_ccfl.vbt A src/mainboard/lenovo/x200/data_led.vbt 5 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/29904/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4a7011ce03cdd511fa2e2160c2f006ba2707ba Gerrit-Change-Number: 29904 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: [WIP]mb/intel/x200: Add data.vbt
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29904 Change subject: [WIP]mb/intel/x200: Add data.vbt ...................................................................... [WIP]mb/intel/x200: Add data.vbt There are 2 vendor BIOS's for the Lenovo X200 with the difference being the settings in the VBT blob to accommodate different backlight frequencies. Linux however sticks with the setting set by the firmware. Change-Id: I4c4a7011ce03cdd511fa2e2160c2f006ba2707ba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/Makefile.inc M src/mainboard/lenovo/x200/blc.c A src/mainboard/lenovo/x200/data_ccfl.vbt A src/mainboard/lenovo/x200/data_led.vbt 5 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/29904/1 diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 51a08e8..6aa2f9b 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -22,6 +22,7 @@ select SUPERIO_NSC_PC87382 select DRIVERS_LENOVO_WACOM select MAINBOARD_HAS_LIBGFXINIT +# select INTEL_GMA_HAVE_VBT config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index c10bc70..3a86aa7 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -19,3 +19,12 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +add_vbt_to_cbfs= \ + $(eval cbfs-files-y += $1) \ + $(eval $1-file := $2) \ + $(eval $1-type := raw) \ + $(eval $1-compression := lzma) + +$(call add_vbt_to_cbfs, data_ccfl.vbt, data_ccfl.vbt) +$(call add_vbt_to_cbfs, data_led.vbt, data_led.vbt) \ No newline at end of file diff --git a/src/mainboard/lenovo/x200/blc.c b/src/mainboard/lenovo/x200/blc.c index 3f8aadb..e764602 100644 --- a/src/mainboard/lenovo/x200/blc.c +++ b/src/mainboard/lenovo/x200/blc.c @@ -13,9 +13,14 @@ * GNU General Public License for more details. */ +#include <device/pci_ops.h> +#include <device/pci_def.h> #include <stdint.h> #include <commonlib/helpers.h> +#include <console/console.h> #include <northbridge/intel/gm45/gm45.h> +#include <drivers/intel/gma/i915_reg.h> +#include <drivers/intel/gma/opregion.h> static const struct blc_pwm_t blc_entries[] = { /* corrected to 320MHz CDClk, vendor set 753; works fine at both: */ @@ -43,3 +48,39 @@ *entries = blc_entries; return ARRAY_SIZE(blc_entries); } + +static u32 get_cdclk(struct device *const dev) +{ + const u16 cdclk_sel = + pci_read_config16(dev, GCFGC_OFFSET) & GCFGC_CD_MASK; + switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) { + case VCO_2666: + case VCO_4000: + case VCO_5333: + return cdclk_sel ? 333333333 : 222222222; + case VCO_3200: + return cdclk_sel ? 320000000 : 228571429; + default: + printk(BIOS_WARNING, + "Unknown VCO frequency, using default cdclk.\n"); + return 222222222; + } +} + +static u32 blc_pwm_ctl_to_freq(void) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + u8 *mmio_base = (void *)(uintptr_t)dev->resource_list[0].base; + u32 blc_pwm_ctl = read32(mmio_base + BLC_PWM_CTL); + + return get_cdclk(dev) / (128 * (blc_pwm_ctl & 0xffff)); +} + +const char *mainboard_vbt_filename(void) +{ + if (blc_pwm_ctl_to_freq() > 200) + return "data_led.vbt"; + else + return "data_ccfl.vbt"; + +} diff --git a/src/mainboard/lenovo/x200/data_ccfl.vbt b/src/mainboard/lenovo/x200/data_ccfl.vbt new file mode 100644 index 0000000..dc044c9 --- /dev/null +++ b/src/mainboard/lenovo/x200/data_ccfl.vbt Binary files differ diff --git a/src/mainboard/lenovo/x200/data_led.vbt b/src/mainboard/lenovo/x200/data_led.vbt new file mode 100644 index 0000000..bcd6c30 --- /dev/null +++ b/src/mainboard/lenovo/x200/data_led.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/29904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c4a7011ce03cdd511fa2e2160c2f006ba2707ba Gerrit-Change-Number: 29904 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit November 2018