coreboot-gerrit November 2018

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Change in ...coreboot[master]: [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29908 ) Change subject: [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage ...................................................................... Patch Set 1: Code-Review-2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic31702514cf84e3480b622c28cd2857e613869d9 Gerrit-Change-Number: 29908 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Comment-Date: Thu, 29 Nov 2018 01:37:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/fsp_baytrail: Implement postcar stage
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29909 Change subject: soc/intel/fsp_baytrail: Implement postcar stage ...................................................................... soc/intel/fsp_baytrail: Implement postcar stage Change-Id: I692bbffe9c37367430191266023ce4e2cf1342a9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_baytrail/Makefile.inc A src/soc/intel/fsp_baytrail/exit_car_fsp.S 3 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/29909/1 diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 7d82f3f..4c5a141 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -46,6 +46,8 @@ # Microcode header files are delivered in FSP package select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN + select POSTCAR_STAGE + select POSTCAR_CONSOLE config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index d8c4f71..a465655 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -30,6 +30,7 @@ ramstage-y += memmap.c romstage-y += memmap.c +postcar-y += memmap.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c @@ -60,4 +61,6 @@ CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp +postcar-y += exit_car_fsp.S + endif diff --git a/src/soc/intel/fsp_baytrail/exit_car_fsp.S b/src/soc/intel/fsp_baytrail/exit_car_fsp.S new file mode 100644 index 0000000..4ac580c --- /dev/null +++ b/src/soc/intel/fsp_baytrail/exit_car_fsp.S @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> + +/* + * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed. + * This version of chipset_teardown_car sets up the stack, then bypasses + * the rest of arch/x86/exit_car.S and calls main() itself instead of + * returning to _start. In main(), the TempRamExit FSP API is called + * to tear down the CAR and set up caching which can be overwritten + * after the API call. More info can be found in the FSP Integration + * Guide included with the FSP binary. + */ + +.text +.global chipset_teardown_car +chipset_teardown_car: + + /* Set up new stack. */ + mov post_car_stack_top, %esp + + /* Call C code */ + call main -- To view, visit https://review.coreboot.org/c/coreboot/+/29909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I692bbffe9c37367430191266023ce4e2cf1342a9 Gerrit-Change-Number: 29909 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage
by Arthur Heymans (Code Review) 29 Nov '18

29 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29908 Change subject: [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage ...................................................................... [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage Change-Id: Ic31702514cf84e3480b622c28cd2857e613869d9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_0/Makefile.inc M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/fsp_broadwell_de/Makefile.inc A src/soc/intel/fsp_broadwell_de/exit_car_fsp.S 4 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/29908/1 diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index 67741a9..b75afad 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -17,6 +17,7 @@ ramstage-y += fsp_util.c hob.c romstage-y += fsp_util.c hob.c +postcar-y += fsp_util.c hob.c ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index fe0fa8d..1203555 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -28,6 +28,8 @@ select HAVE_SMI_HANDLER select TSC_MONOTONIC_TIMER select TSC_CONSTANT_RATE + select POSTCAR_STAGE + select POSTCAR_CONSOLE config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index f88cbba..36d907a 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -19,6 +19,7 @@ ramstage-y += tsc_freq.c romstage-y += memmap.c ramstage-y += memmap.c +postcar-y += memmap.c ramstage-y += southcluster.c ramstage-y += acpi.c ramstage-y += smbus_common.c @@ -38,4 +39,6 @@ CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/ +postcar-y += exit_car_fsp.S + endif # ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) diff --git a/src/soc/intel/fsp_broadwell_de/exit_car_fsp.S b/src/soc/intel/fsp_broadwell_de/exit_car_fsp.S new file mode 100644 index 0000000..4ac580c --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/exit_car_fsp.S @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> + +/* + * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed. + * This version of chipset_teardown_car sets up the stack, then bypasses + * the rest of arch/x86/exit_car.S and calls main() itself instead of + * returning to _start. In main(), the TempRamExit FSP API is called + * to tear down the CAR and set up caching which can be overwritten + * after the API call. More info can be found in the FSP Integration + * Guide included with the FSP binary. + */ + +.text +.global chipset_teardown_car +chipset_teardown_car: + + /* Set up new stack. */ + mov post_car_stack_top, %esp + + /* Call C code */ + call main -- To view, visit https://review.coreboot.org/c/coreboot/+/29908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic31702514cf84e3480b622c28cd2857e613869d9 Gerrit-Change-Number: 29908 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Load FSP teardown optionally
by Lijian Zhao (Code Review) 29 Nov '18

29 Nov '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29907 Change subject: soc/intel/cannonlake: Load FSP teardown optionally ...................................................................... soc/intel/cannonlake: Load FSP teardown optionally Make build still pass in case of no FsptUpd.h available. BUG=N/A TEST=Delete FsptUpd.h and build pass wihtout FSP_CAR set. Change-Id: I3936d3deb8b079bd4db11e444f6bb7f9605520dc Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/bootblock.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/29907/1 diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 4eeef59..b7d00cd 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -19,6 +19,8 @@ #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/pch.h> + +#if IS_ENABLED(CONFIG_FSP_CAR) #include <FsptUpd.h> const FSPT_UPD temp_ram_init_params = { @@ -37,6 +39,7 @@ .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, }, }; +#endif asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { -- To view, visit https://review.coreboot.org/c/coreboot/+/29907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3936d3deb8b079bd4db11e444f6bb7f9605520dc Gerrit-Change-Number: 29907 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/xcompile/xcompile: Enable x86_64 support
by Patrick Georgi (Code Review) 28 Nov '18

28 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29877 ) Change subject: util/xcompile/xcompile: Enable x86_64 support ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29877/2/util/xcompile/xcompile File util/xcompile/xcompile: https://review.coreboot.org/#/c/29877/2/util/xcompile/xcompile@241 PS2, Line 241: nocona why this specific chip? I had to look up what nocona means ;-) -- To view, visit https://review.coreboot.org/c/coreboot/+/29877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied28f98f89610a748be8d66cf35814e9112a4407 Gerrit-Change-Number: 29877 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 21:29:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/Makefile.inc: Fix typo
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29878 ) Change subject: arch/x86/Makefile.inc: Fix typo ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c06f494dcc035d182ab9034e910ceceb236198 Gerrit-Change-Number: 29878 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 21:07:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/microcode: Enable verbose output
by Patrick Rudolph (Code Review) 28 Nov '18

28 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29864 ) Change subject: cpu/intel/microcode: Enable verbose output ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534aa790c8d37b5f1603e1715635446835513a65 Gerrit-Change-Number: 29864 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 20:30:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
by Furquan Shaikh (Code Review) 28 Nov '18

28 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29872 ) Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29872/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nami/gpio.c: https://review.coreboot.org/#/c/29872/2/src/mainboard/google/poppy/variants… PS2, Line 413: PAD_CFG_GPI_APIC > Yes, I tried PAD_CFG_GPI_APIC_INVERT and I don't see the spi device and I don't see interrupts in /p […] If you have SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG selected in your repo for skylake, then I would expect PAD_CFG_GPI_APIC_INVERT to work as expected. One thing to check would be to assert the line manually and see what the pad input is and if you see any interrupts. -- To view, visit https://review.coreboot.org/c/coreboot/+/29872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Gerrit-Change-Number: 29872 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 28 Nov 2018 20:15:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
by Shelley Chen (Code Review) 28 Nov '18

28 Nov '18

Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29872 ) Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29872/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nami/gpio.c: https://review.coreboot.org/#/c/29872/2/src/mainboard/google/poppy/variants… PS2, Line 413: PAD_CFG_GPI_APIC > Done Yes, I tried PAD_CFG_GPI_APIC_INVERT and I don't see the spi device and I don't see interrupts in /proc/interrupts in the chromeos-ec line. Also, I tried unlocking with fingerprint and it doesn't work (also, didn't see any interrupt increase in /proc/interrupts). -- To view, visit https://review.coreboot.org/c/coreboot/+/29872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Gerrit-Change-Number: 29872 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 28 Nov 2018 19:33:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: broadcom: Remove SoC and board support
by Julius Werner (Code Review) 28 Nov '18

28 Nov '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29905 ) Change subject: broadcom: Remove SoC and board support ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a Gerrit-Change-Number: 29905 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 18:53:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2018