coreboot-gerrit November 2018

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Change in ...coreboot[master]: LinuxBoot: refactor payload
by Philipp Deppenwiese (Code Review) 28 Nov '18

28 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29581 ) Change subject: LinuxBoot: refactor payload ...................................................................... Patch Set 11: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/29581/11/payloads/external/Makefile.inc File payloads/external/Makefile.inc: https://review.coreboot.org/#/c/29581/11/payloads/external/Makefile.inc@276 PS11, Line 276: payloads/external/LinuxBoot/linuxboot/uImage: linuxboot sure that we have uImage support and what about zImage and Image? -- To view, visit https://review.coreboot.org/c/coreboot/+/29581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41d0275a5f7efb920e881f43b0acda29f41ee221 Gerrit-Change-Number: 29581 Gerrit-PatchSet: 11 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Andrea Barberio <insomniac(a)slackware.it> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 28 Nov 2018 16:20:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: tss: implement tlcl_save_state
by Philipp Deppenwiese (Code Review) 28 Nov '18

28 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29646 ) Change subject: tss: implement tlcl_save_state ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b51ca68456fc9b655e4dc2d0958b7c040d50510 Gerrit-Change-Number: 29646 Gerrit-PatchSet: 5 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 16:16:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: tss/tcg-2.0: remove unnecessary breaks from marshaling code
by Philipp Deppenwiese (Code Review) 28 Nov '18

28 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29652 ) Change subject: tss/tcg-2.0: remove unnecessary breaks from marshaling code ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I054e0799469bf39499666342a5c639b1f766cd85 Gerrit-Change-Number: 29652 Gerrit-PatchSet: 2 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 28 Nov 2018 16:15:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/apl: Enable graphics with libgfxinit
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29903 ) Change subject: soc/intel/apl: Enable graphics with libgfxinit ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b111f1cdac4d18f2fc3089f57aebf3ad1739e5d Gerrit-Change-Number: 29903 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 15:22:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/apl: Hook microcode update up
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29902 ) Change subject: soc/intel/apl: Hook microcode update up ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53f680fc4342a9bd1cd0ba9d72e025995e25f7f2 Gerrit-Change-Number: 29902 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 15:21:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/inteltool: Add Apollo Lake GPIO groups and names
by build bot (Jenkins) (Code Review) 28 Nov '18

28 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29897 ) Change subject: util/inteltool: Add Apollo Lake GPIO groups and names ...................................................................... Patch Set 1: (24 comments) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c File util/inteltool/gpio_groups.c: https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@108 PS1, Line 108: "*GPIO_72", "GP_CAMERASB10","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@109 PS1, Line 109: "*GPIO_73", "GP_CAMERASB11","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@116 PS1, Line 116: "JTAGX" , "*JTAGX", "n/a", "n/a", "n/a", "n/a", space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@123 PS1, Line 123: "SVID0_ALERT_B","*SVID0_ALERT_N","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@123 PS1, Line 123: "SVID0_ALERT_B","*SVID0_ALERT_N","n/a", "n/a", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@167 PS1, Line 167: "PMC_SPI_FS2", "*PMC_SPI_FS2", "FST_SPI_CS2_N","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@181 PS1, Line 181: "*GPIO_74", "AVS_I2S1_MCLK" , "n/a", "n/a", space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@186 PS1, Line 186: "*GPIO_79", "AVS_DMIC_CLK_A1", "AVS_I2S4_BCLK","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@187 PS1, Line 187: "*GPIO_80", "AVS_DMIC_CLK_B1", "AVS_I2S4_WS_SYNC","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@191 PS1, Line 191: "*GPIO_84", "AVS_I2S2_MCLK", "AVS_HDA_RST_N","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@319 PS1, Line 319: "*GPIO_134", "LPSS_I2C5_SDA","ISH_I2C0_SDA", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@320 PS1, Line 320: "*GPIO_135", "LPSS_I2C5_SCL","ISH_I2C0_SCL", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@321 PS1, Line 321: "*GPIO_136", "LPSS_I2C6_SDA","ISH_I2C1_SDA", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@322 PS1, Line 322: "*GPIO_137", "LPSS_I2C6_SCL","ISH_I2C1_SCL", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@323 PS1, Line 323: "*GPIO_138", "LPSS_I2C7_SDA","ISH_I2C2_SDA", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@324 PS1, Line 324: "*GPIO_139", "LPSS_I2C7_SCL","ISH_I2C2_SCL", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@335 PS1, Line 335: "GPIO_209", "*PCIE_CLKREQ0_N", "MODEM_CLK_REQ","n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@339 PS1, Line 339: "OSC_CLK_OUT_0","*OSC_CLK_OUT_0", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@340 PS1, Line 340: "OSC_CLK_OUT_1","*OSC_CLK_OUT_1", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@341 PS1, Line 341: "OSC_CLK_OUT_2","*OSC_CLK_OUT_2", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@342 PS1, Line 342: "OSC_CLK_OUT_3","*OSC_CLK_OUT_3", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@343 PS1, Line 343: "OSC_CLK_OUT_4","*OSC_CLK_OUT_4", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@344 PS1, Line 344: "*PMU_AC_PRESENT","PMU_AC_PRESENT", "n/a", "n/a", space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29897/1/util/inteltool/gpio_groups.c@353 PS1, Line 353: "*PMU_WAKE_B", "PMU_WAKE_B/EMMC_PWR_EN_N","n/a", "n/a", space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/29897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Gerrit-Change-Number: 29897 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 15:20:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/apl: Enable graphics with libgfxinit
by Nico Huber (Code Review) 28 Nov '18

28 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29903 Change subject: soc/intel/apl: Enable graphics with libgfxinit ...................................................................... soc/intel/apl: Enable graphics with libgfxinit As usual, it just works. Change-Id: I7b111f1cdac4d18f2fc3089f57aebf3ad1739e5d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/drivers/intel/gma/Kconfig M src/soc/intel/apollolake/graphics.c 2 files changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/29903/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 10ccf71..a5c8495 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -68,13 +68,14 @@ depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL \ - || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE + || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE depends on MAINBOARD_HAS_LIBGFXINIT if GFX_GMA config GFX_GMA_CPU string + default "Broxton" if SOC_INTEL_APOLLOLAKE default "Skylake" if SOC_INTEL_SKYLAKE default "Broadwell" if SOC_INTEL_BROADWELL default "Haswell" if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 4857788..37cdda4 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -15,19 +15,44 @@ * GNU General Public License for more details. */ +#include <stdint.h> +#include <arch/acpi.h> #include <arch/acpigen.h> +#include <bootmode.h> #include <console/console.h> #include <fsp/util.h> #include <device/device.h> #include <device/pci.h> #include <intelblocks/graphics.h> #include <drivers/intel/gma/opregion.h> +#include <drivers/intel/gma/libgfxinit.h> uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); } +void graphics_soc_init(struct device *const dev) +{ + if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) + return; + + uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { + if (!acpi_is_wakeup_s3() && display_init_required()) { + int lightup_ok; + gma_gfxinit(&lightup_ok); + gfx_set_init_done(lightup_ok); + } + } else { + /* Initialize PCI device, load/execute BIOS Option ROM */ + pci_dev_init(dev); + } +} + uintptr_t graphics_soc_write_acpi_opregion(struct device *device, uintptr_t current, struct acpi_rsdp *rsdp) { -- To view, visit https://review.coreboot.org/c/coreboot/+/29903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b111f1cdac4d18f2fc3089f57aebf3ad1739e5d Gerrit-Change-Number: 29903 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apl: Hook microcode update up
by Nico Huber (Code Review) 28 Nov '18

28 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29902 Change subject: soc/intel/apl: Hook microcode update up ...................................................................... soc/intel/apl: Hook microcode update up Change-Id: I53f680fc4342a9bd1cd0ba9d72e025995e25f7f2 --- M src/soc/intel/apollolake/Makefile.inc 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/29902/1 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 6168f86..7ac6e0a 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -175,3 +175,6 @@ $(RT5682_RENDER_CAPTURE)-type := raw endif + +# Apollo Lake B0 (506c9) only atm. +cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_506cx/microcode.bin -- To view, visit https://review.coreboot.org/c/coreboot/+/29902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53f680fc4342a9bd1cd0ba9d72e025995e25f7f2 Gerrit-Change-Number: 29902 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apl: Configure LPC serial IRQ mode
by Nico Huber (Code Review) 28 Nov '18

28 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29901 Change subject: soc/intel/apl: Configure LPC serial IRQ mode ...................................................................... soc/intel/apl: Configure LPC serial IRQ mode Sync the FSP settings with what coreboot does. Why both FSP and coreboot configure this redundantly stays a secret. TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC works correctly now, but was confused by the wrong settings before because the FSP defaults allowed to disable the LPC clock. Change-Id: Id1c7180f460678bf0f9458228591050dd628c052 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/apollolake/chip.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/29901/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index cbd5aba..77b82d4 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -610,6 +610,21 @@ memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, sizeof(silconfig->PcieRpHotPlug)); + switch (cfg->serirq_mode) { + case SERIRQ_QUIET: + silconfig->SirqEnable = 1; + silconfig->SirqMode = 0; + break; + case SERIRQ_CONTINUOUS: + silconfig->SirqEnable = 1; + silconfig->SirqMode = 1; + break; + case SERIRQ_OFF: + default: + silconfig->SirqEnable = 0; + break; + } + if (cfg->emmc_tx_cmd_cntl != 0) silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; if (cfg->emmc_tx_data_cntl1 != 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/29901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1c7180f460678bf0f9458228591050dd628c052 Gerrit-Change-Number: 29901 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apl: Disable LPC Clock Run feature after FSP-S
by Nico Huber (Code Review) 28 Nov '18

28 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29900 Change subject: soc/intel/apl: Disable LPC Clock Run feature after FSP-S ...................................................................... soc/intel/apl: Disable LPC Clock Run feature after FSP-S The EDS clearly says that it shouldn't be enabled before all LPC devices are initialized. Change-Id: Ibfad2555cc78ed9639f4f8b54d4b5b4ad28db65d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/apollolake/chip.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/29900/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 85fe30c..cbd5aba 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -35,6 +35,7 @@ #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/itss.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/pmclib.h> #include <romstage_handoff.h> #include <soc/cpu.h> @@ -657,6 +658,13 @@ silconfig->UsbOtg = dev->enabled; } +void soc_fsp_silicon_init_fixups(void) +{ + /* FSP-S enables LPC Clock Run even though it should only + happen after all LPC devices are fully initialized. */ + lpc_disable_pci_clkrun(); +} + struct chip_operations soc_intel_apollolake_ops = { CHIP_NAME("Intel Apollolake SOC") .enable_dev = &enable_dev, -- To view, visit https://review.coreboot.org/c/coreboot/+/29900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfad2555cc78ed9639f4f8b54d4b5b4ad28db65d Gerrit-Change-Number: 29900 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2018