coreboot-gerrit November 2018

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Change in ...coreboot[master]: arch/x86/acpigen.c: Add a method to notify all CPU cores
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29895 Change subject: arch/x86/acpigen.c: Add a method to notify all CPU cores ...................................................................... arch/x86/acpigen.c: Add a method to notify all CPU cores Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/acpigen.c M src/arch/x86/include/arch/acpigen.h M src/cpu/intel/speedstep/acpi.c 3 files changed, 19 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/29895/1 diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 426a542..2bc9b69 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -369,6 +369,23 @@ acpigen_pop_len(); } +/* Method to notify all CPU cores */ +void acpigen_write_processor_cnot(const unsigned int number_of_cores) +{ + int coreID; + + acpigen_write_method("\\_PR.CNOT", 1); + for (coreID = 0; coreID < cores_per_package; coreID++) { + char buffer[DEVICE_PATH_MAX]; + snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c", + '0' + coreID / 10, '0' + coreID % 10); + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(buffer); + acpigen_emit_byte(ARG0_OP); + } + acpigen_pop_len(); +} + /* * Generate ACPI AML code for OperationRegion * Arg0: Pointer to struct opregion opreg = OPREGION(rname, space, offset, len) diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index a27bd6f..d9379eb 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -277,6 +277,7 @@ void acpigen_write_processor_package(const char *name, unsigned int first_core, unsigned int core_count); +void acpigen_write_processor_cnot(const unsigned int number_of_cores); void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list); void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 0feaa2f..b5e2c9e9 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -166,15 +166,5 @@ of the first and only package. */ acpigen_write_processor_package("PPKG", 0, cores_per_package); - /* Add a method to notify processor nodes */ - acpigen_write_method("\\_PR.CNOT", 1); - for (coreID = 0; coreID < cores_per_package; coreID++) { - char buffer[DEVICE_PATH_MAX]; - snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c", - '0' + coreID / 10, '0' + coreID % 10); - acpigen_emit_byte(NOTIFY_OP); - acpigen_emit_namestring(buffer); - acpigen_emit_byte(ARG0_OP); - } - acpigen_pop_len(); + acpigen_write_processor_cnot(cores_per_package); } -- To view, visit https://review.coreboot.org/c/coreboot/+/29895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8b07fdcec51c344a82309d4af3b6127ad758baf Gerrit-Change-Number: 29895 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Remove duplicated round up function
by build bot (Jenkins) (Code Review) 28 Nov '18

28 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29847 ) Change subject: src: Remove duplicated round up function ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/#/c/29847/6/src/soc/nvidia/tegra210/include/soc… File src/soc/nvidia/tegra210/include/soc/clock.h: https://review.coreboot.org/#/c/29847/6/src/soc/nvidia/tegra210/include/soc… PS6, Line 327: #define get_i2c_clk_div(src,freq) (DIV_ROUND_UP(src, (freq) * (0x19 + 1) * 8) - 1) line over 80 characters https://review.coreboot.org/#/c/29847/6/src/soc/nvidia/tegra210/include/soc… PS6, Line 327: #define get_i2c_clk_div(src,freq) (DIV_ROUND_UP(src, (freq) * (0x19 + 1) * 8) - 1) space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/29847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Gerrit-Change-Number: 29847 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Nov 2018 12:11:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/haswell: Rework acpi/cpu.asl
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29885 ) Change subject: cpu/intel/haswell: Rework acpi/cpu.asl ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29885/1/src/cpu/intel/haswell/acpi/cpu.asl File src/cpu/intel/haswell/acpi/cpu.asl: https://review.coreboot.org/#/c/29885/1/src/cpu/intel/haswell/acpi/cpu.asl@… PS1, Line 50: > here changed to 0x81. […] I guess not, I just copied stuff around :( -- To view, visit https://review.coreboot.org/c/coreboot/+/29885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620 Gerrit-Change-Number: 29885 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 28 Nov 2018 12:00:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/haswell: Rework acpi/cpu.asl
by HAOUAS Elyes (Code Review) 28 Nov '18

28 Nov '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29885 ) Change subject: cpu/intel/haswell: Rework acpi/cpu.asl ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29885/1/src/cpu/intel/haswell/acpi/cpu.asl File src/cpu/intel/haswell/acpi/cpu.asl: https://review.coreboot.org/#/c/29885/1/src/cpu/intel/haswell/acpi/cpu.asl@… PS1, Line 50: here changed to 0x81. is it what you want ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620 Gerrit-Change-Number: 29885 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 28 Nov 2018 11:58:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/hp/compaq_8200_elite_sff: Fix SATA port map
by Patrick Georgi (Code Review) 28 Nov '18

28 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29855 ) Change subject: mb/hp/compaq_8200_elite_sff: Fix SATA port map ...................................................................... mb/hp/compaq_8200_elite_sff: Fix SATA port map Assign correct SATA port map. Tested on HP8200: All SATA ports are now usable in GNU/Linux. Change-Id: I5be2b4f33882f6f71213f8173cdb945fc9b7af06 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/29855 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index e7aecdb..61bf43c 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -52,7 +52,7 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0x13" + register "sata_port_map" = "0xf" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x0" device pci 16.0 on # Management Engine Interface 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be2b4f33882f6f71213f8173cdb945fc9b7af06 Gerrit-Change-Number: 29855 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: security/vboot: Add VB2_LIB to romstage sources without dependencies
by Patrick Georgi (Code Review) 28 Nov '18

28 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29827 ) Change subject: security/vboot: Add VB2_LIB to romstage sources without dependencies ...................................................................... security/vboot: Add VB2_LIB to romstage sources without dependencies The coming feature "measured boot" relies on VB2_LIB in romstage. In the case where there is no separate verstage, compile the library just for romstage as it will then be shared across verstage and romstage code. If there is a separate verstage, compile the library separately for verstage and romstage. Change-Id: I8126c21b8fbe8dd65d95af49cbe2ad776b8ef605 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/29827 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/security/vboot/Makefile.inc 1 file changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index da5d5b1..ae80a02 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -110,16 +110,14 @@ CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include -$(eval $(call vboot-for-stage,verstage)) $(eval $(call vboot-for-stage,bootblock)) +$(eval $(call vboot-for-stage,romstage)) $(eval $(call vboot-for-stage,ramstage)) $(eval $(call vboot-for-stage,postcar)) ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y) -ifeq ($(CONFIG_VBOOT_HAS_REC_HASH_SPACE),y) -$(eval $(call vboot-for-stage,romstage)) -endif +$(eval $(call vboot-for-stage,verstage)) cbfs-files-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += $(CONFIG_CBFS_PREFIX)/verstage $(CONFIG_CBFS_PREFIX)/verstage-file := $(objcbfs)/verstage.elf -- To view, visit https://review.coreboot.org/c/coreboot/+/29827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8126c21b8fbe8dd65d95af49cbe2ad776b8ef605 Gerrit-Change-Number: 29827 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/common/acpi: Add common CPU methods
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29754 ) Change subject: soc/intel/common/acpi: Add common CPU methods ...................................................................... Patch Set 1: > Patch Set 1: > > It is a good idea, but I think it is a much larger change than just fixing the cannonlake bug where these methods don't exist, which I could do instead of refactoring it into common code if we want to instead push for a change in this direction. > > However, I think calling back into an SSDT from the DSDT is still not allowed by the linux kernel, and currently all the DPTF code is in the DSDT... https://review.coreboot.org/q/topic:%22common_cpu_asl%22+(status:open%20OR%… implements it for almost all intel targets. (fully untested) -- To view, visit https://review.coreboot.org/c/coreboot/+/29754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd467ef84a391698cd395172c3f0d4e801bdd09b Gerrit-Change-Number: 29754 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 28 Nov 2018 11:51:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/baytrail: Rework acpi/cpu.asl
by build bot (Jenkins) (Code Review) 28 Nov '18

28 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29888 ) Change subject: soc/intel/baytrail: Rework acpi/cpu.asl ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29888/1/src/soc/intel/baytrail/acpi.c File src/soc/intel/baytrail/acpi.c: https://review.coreboot.org/#/c/29888/1/src/soc/intel/baytrail/acpi.c@450 PS1, Line 450: for (core=0; core < pattrs->num_cpus; core++) { spaces required around that '=' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/29888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb5a5c1255f9a922063293bf430e849909468eaf Gerrit-Change-Number: 29888 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 11:50:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/common: Use a common acpi/cpu.asl file
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29894 Change subject: cpu/intel/common: Use a common acpi/cpu.asl file ...................................................................... cpu/intel/common: Use a common acpi/cpu.asl file Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- R src/cpu/intel/common/acpi/cpu.asl D src/cpu/intel/fsp_model_406dx/acpi/cpu.asl D src/cpu/intel/model_206ax/acpi/cpu.asl M src/mainboard/adi/rcc-dff/dsdt.asl M src/mainboard/apple/macbookair4_2/dsdt.asl M src/mainboard/asrock/b75pro3-m/dsdt.asl M src/mainboard/asrock/h81m-hds/dsdt.asl M src/mainboard/asus/maximus_iv_gene-z/dsdt.asl M src/mainboard/asus/p8h61-m_lx/dsdt.asl M src/mainboard/asus/p8h61-m_pro/dsdt.asl M src/mainboard/compulab/intense_pc/dsdt.asl M src/mainboard/esd/atom15/dsdt.asl M src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl M src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl M src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/beltino/dsdt.asl M src/mainboard/google/butterfly/dsdt.asl M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/eve/dsdt.asl M src/mainboard/google/fizz/dsdt.asl M src/mainboard/google/glados/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/google/link/dsdt.asl M src/mainboard/google/octopus/dsdt.asl M src/mainboard/google/parrot/dsdt.asl M src/mainboard/google/poppy/dsdt.asl M src/mainboard/google/rambi/dsdt.asl M src/mainboard/google/reef/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/slippy/dsdt.asl M src/mainboard/google/stout/dsdt.asl M src/mainboard/google/zoombini/dsdt.asl M src/mainboard/hp/2570p/dsdt.asl M src/mainboard/hp/2760p/dsdt.asl M src/mainboard/hp/8460p/dsdt.asl M src/mainboard/hp/8470p/dsdt.asl M src/mainboard/hp/8770w/dsdt.asl M src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl M src/mainboard/hp/folio_9470m/dsdt.asl M src/mainboard/hp/revolve_810_g1/dsdt.asl M src/mainboard/intel/baskingridge/dsdt.asl M src/mainboard/intel/bayleybay_fsp/dsdt.asl M src/mainboard/intel/dcp847ske/dsdt.asl M src/mainboard/intel/emeraldlake2/dsdt.asl M src/mainboard/intel/glkrvp/dsdt.asl M src/mainboard/intel/harcuvar/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl M src/mainboard/intel/kblrvp/dsdt.asl M src/mainboard/intel/kunimitsu/dsdt.asl M src/mainboard/intel/leafhill/dsdt.asl M src/mainboard/intel/littleplains/dsdt.asl M src/mainboard/intel/minnow3/dsdt.asl M src/mainboard/intel/minnowmax/dsdt.asl M src/mainboard/intel/mohonpeak/dsdt.asl M src/mainboard/intel/saddlebrook/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/kontron/ktqm77/dsdt.asl M src/mainboard/lenovo/l520/dsdt.asl M src/mainboard/lenovo/s230u/dsdt.asl M src/mainboard/lenovo/t420/dsdt.asl M src/mainboard/lenovo/t420s/dsdt.asl M src/mainboard/lenovo/t430/dsdt.asl M src/mainboard/lenovo/t430s/dsdt.asl M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t530/dsdt.asl M src/mainboard/lenovo/x131e/dsdt.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl M src/mainboard/lenovo/x201/dsdt.asl M src/mainboard/lenovo/x220/dsdt.asl M src/mainboard/lenovo/x230/dsdt.asl M src/mainboard/opencellular/rotundu/dsdt.asl M src/mainboard/packardbell/ms2290/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl M src/mainboard/purism/librem_skl/dsdt.asl M src/mainboard/roda/rv11/dsdt.asl M src/mainboard/samsung/lumpy/dsdt.asl M src/mainboard/samsung/stumpy/dsdt.asl M src/mainboard/sapphire/pureplatinumh61/dsdt.asl M src/mainboard/scaleway/tagada/dsdt.asl M src/mainboard/siemens/mc_apl1/dsdt.asl M src/mainboard/siemens/mc_tcu3/dsdt.asl D src/soc/intel/apollolake/acpi/cpu.asl D src/soc/intel/baytrail/acpi/cpu.asl D src/soc/intel/braswell/acpi/cpu.asl D src/soc/intel/braswell/acpi/dptf/cpu.asl D src/soc/intel/broadwell/acpi/cpu.asl D src/soc/intel/cannonlake/acpi/cpu.asl D src/soc/intel/denverton_ns/acpi/cpu.asl D src/soc/intel/fsp_baytrail/acpi/cpu.asl D src/soc/intel/icelake/acpi/cpu.asl D src/soc/intel/skylake/acpi/cpu.asl 92 files changed, 79 insertions(+), 679 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29894/1 diff --git a/src/cpu/intel/haswell/acpi/cpu.asl b/src/cpu/intel/common/acpi/cpu.asl similarity index 100% rename from src/cpu/intel/haswell/acpi/cpu.asl rename to src/cpu/intel/common/acpi/cpu.asl diff --git a/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl b/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl deleted file mode 100644 index 3ee5265..0000000 --- a/src/cpu/intel/fsp_model_406dx/acpi/cpu.asl +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ -Method (PPCN) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} \ No newline at end of file diff --git a/src/cpu/intel/model_206ax/acpi/cpu.asl b/src/cpu/intel/model_206ax/acpi/cpu.asl deleted file mode 100644 index 3ee5265..0000000 --- a/src/cpu/intel/model_206ax/acpi/cpu.asl +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ -Method (PPCN) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} \ No newline at end of file diff --git a/src/mainboard/adi/rcc-dff/dsdt.asl b/src/mainboard/adi/rcc-dff/dsdt.asl index 8091a4e..310ad04 100644 --- a/src/mainboard/adi/rcc-dff/dsdt.asl +++ b/src/mainboard/adi/rcc-dff/dsdt.asl @@ -38,7 +38,7 @@ #include "acpi/thermal.asl" - #include <cpu/intel/fsp_model_406dx/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index 10baddb..65ce63e 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -26,7 +26,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index 5c86e77..467a001 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -29,7 +29,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl index 917b2e4..f76c393 100644 --- a/src/mainboard/asrock/h81m-hds/dsdt.asl +++ b/src/mainboard/asrock/h81m-hds/dsdt.asl @@ -28,7 +28,7 @@ #include <southbridge/intel/lynxpoint/acpi/platform.asl> #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> - #include <cpu/intel/haswell/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { diff --git a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl index aef4be6..e3abc26 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl +++ b/src/mainboard/asus/maximus_iv_gene-z/dsdt.asl @@ -25,7 +25,7 @@ ) { #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> diff --git a/src/mainboard/asus/p8h61-m_lx/dsdt.asl b/src/mainboard/asus/p8h61-m_lx/dsdt.asl index aef4be6..e3abc26 100644 --- a/src/mainboard/asus/p8h61-m_lx/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_lx/dsdt.asl @@ -25,7 +25,7 @@ ) { #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> diff --git a/src/mainboard/asus/p8h61-m_pro/dsdt.asl b/src/mainboard/asus/p8h61-m_pro/dsdt.asl index 6714eb7..d9861ef 100644 --- a/src/mainboard/asus/p8h61-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8h61-m_pro/dsdt.asl @@ -27,7 +27,7 @@ // Some generic macros #include "acpi/platform.asl" #include "acpi/superio.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index 41ff6e6..ad0940c 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -29,7 +29,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/esd/atom15/dsdt.asl b/src/mainboard/esd/atom15/dsdt.asl index 2dc7139..3719154 100644 --- a/src/mainboard/esd/atom15/dsdt.asl +++ b/src/mainboard/esd/atom15/dsdt.asl @@ -38,7 +38,7 @@ // global NVS and variables #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> - #include <soc/intel/fsp_baytrail/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl index 51e1ed0..67054cc 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -25,7 +25,7 @@ // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl index 51e1ed0..67054cc 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl @@ -25,7 +25,7 @@ // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl index fc69222..6a929d0 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl @@ -29,7 +29,7 @@ #include "acpi/platform.asl" #include "acpi/superio.asl" #include "acpi/thermal.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 3534c4e..7a2aad9 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -37,7 +37,7 @@ //#include "acpi/gpe.asl" // CPU - #include <soc/intel/broadwell/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index 40f58e7..41f908f 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -34,7 +34,7 @@ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> // CPU - #include <cpu/intel/haswell/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index 8aced6e..dd18e95 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -39,7 +39,7 @@ // General Purpose Events //#include "acpi/gpe.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index 0d08cf7..2e9ce63 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -33,7 +33,7 @@ #include <soc/intel/icelake/acpi/globalnvs.asl> // CPU - #include <soc/intel/icelake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index 718ef47..a705457 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -33,7 +33,7 @@ #include <soc/intel/skylake/acpi/globalnvs.asl> /* CPU */ - #include <soc/intel/skylake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl index 50e3791..03df2b9 100644 --- a/src/mainboard/google/fizz/dsdt.asl +++ b/src/mainboard/google/fizz/dsdt.asl @@ -33,7 +33,7 @@ #include <soc/intel/skylake/acpi/globalnvs.asl> /* CPU */ - #include <soc/intel/skylake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index c1e3616..af5f99d 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -32,7 +32,7 @@ #include <soc/intel/skylake/acpi/globalnvs.asl> // CPU - #include <soc/intel/skylake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index db09dc0..e216b13 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -37,7 +37,7 @@ //#include "acpi/gpe.asl" // CPU - #include <soc/intel/broadwell/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index 5d7a28c..ce4ba91 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -40,7 +40,7 @@ //#include "acpi/gpe.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/octopus/dsdt.asl b/src/mainboard/google/octopus/dsdt.asl index 88be0a4..b434948 100644 --- a/src/mainboard/google/octopus/dsdt.asl +++ b/src/mainboard/google/octopus/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/apollolake/acpi/globalnvs.asl> /* CPU */ - #include <soc/intel/apollolake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index 1d4a4ae..e866e21 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -38,7 +38,7 @@ // General Purpose Events //#include "acpi/gpe.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 9d14298..0001867 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -33,7 +33,7 @@ #include <soc/intel/skylake/acpi/globalnvs.asl> /* CPU */ - #include <soc/intel/skylake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 5b5ea2e..8ca9dfb 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -32,7 +32,7 @@ // global NVS and variables #include <soc/intel/baytrail/acpi/globalnvs.asl> - #include <soc/intel/baytrail/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 7ee16ee..2b2f522 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/apollolake/acpi/globalnvs.asl> /* CPU */ - #include <soc/intel/apollolake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 91ba815..bed06fe 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -32,7 +32,7 @@ #include <soc/intel/cannonlake/acpi/globalnvs.asl> /* CPU */ - #include <soc/intel/cannonlake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PWRB) diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl index dcd74d8..8424c25 100644 --- a/src/mainboard/google/slippy/dsdt.asl +++ b/src/mainboard/google/slippy/dsdt.asl @@ -37,7 +37,7 @@ //#include "acpi/gpe.asl" // CPU - #include <cpu/intel/haswell/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index c9f5668..1361a51 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -40,7 +40,7 @@ // General Purpose Events //#include "acpi/gpe.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/google/zoombini/dsdt.asl b/src/mainboard/google/zoombini/dsdt.asl index 040cafc..e9988f0 100644 --- a/src/mainboard/google/zoombini/dsdt.asl +++ b/src/mainboard/google/zoombini/dsdt.asl @@ -35,7 +35,7 @@ #include <soc/intel/cannonlake/acpi/globalnvs.asl> // CPU - #include <soc/intel/cannonlake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/hp/2570p/dsdt.asl b/src/mainboard/hp/2570p/dsdt.asl index aa3050d..756516e 100644 --- a/src/mainboard/hp/2570p/dsdt.asl +++ b/src/mainboard/hp/2570p/dsdt.asl @@ -28,7 +28,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/hp/2760p/dsdt.asl b/src/mainboard/hp/2760p/dsdt.asl index aa3050d..756516e 100644 --- a/src/mainboard/hp/2760p/dsdt.asl +++ b/src/mainboard/hp/2760p/dsdt.asl @@ -28,7 +28,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/hp/8460p/dsdt.asl b/src/mainboard/hp/8460p/dsdt.asl index aa3050d..756516e 100644 --- a/src/mainboard/hp/8460p/dsdt.asl +++ b/src/mainboard/hp/8460p/dsdt.asl @@ -28,7 +28,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/hp/8470p/dsdt.asl b/src/mainboard/hp/8470p/dsdt.asl index aa3050d..756516e 100644 --- a/src/mainboard/hp/8470p/dsdt.asl +++ b/src/mainboard/hp/8470p/dsdt.asl @@ -28,7 +28,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/hp/8770w/dsdt.asl b/src/mainboard/hp/8770w/dsdt.asl index aa3050d..756516e 100644 --- a/src/mainboard/hp/8770w/dsdt.asl +++ b/src/mainboard/hp/8770w/dsdt.asl @@ -28,7 +28,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl index 305149d..ef67ee7 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl +++ b/src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl @@ -28,7 +28,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/hp/folio_9470m/dsdt.asl b/src/mainboard/hp/folio_9470m/dsdt.asl index aa3050d..756516e 100644 --- a/src/mainboard/hp/folio_9470m/dsdt.asl +++ b/src/mainboard/hp/folio_9470m/dsdt.asl @@ -28,7 +28,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/hp/revolve_810_g1/dsdt.asl b/src/mainboard/hp/revolve_810_g1/dsdt.asl index aa3050d..756516e 100644 --- a/src/mainboard/hp/revolve_810_g1/dsdt.asl +++ b/src/mainboard/hp/revolve_810_g1/dsdt.asl @@ -28,7 +28,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index 128bff6..c713330 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -37,7 +37,7 @@ #include "acpi/thermal.asl" - #include <cpu/intel/haswell/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/bayleybay_fsp/dsdt.asl b/src/mainboard/intel/bayleybay_fsp/dsdt.asl index 2dc7139..3719154 100644 --- a/src/mainboard/intel/bayleybay_fsp/dsdt.asl +++ b/src/mainboard/intel/bayleybay_fsp/dsdt.asl @@ -38,7 +38,7 @@ // global NVS and variables #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> - #include <soc/intel/fsp_baytrail/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl index d9d862c..60f4c74 100644 --- a/src/mainboard/intel/dcp847ske/dsdt.asl +++ b/src/mainboard/intel/dcp847ske/dsdt.asl @@ -26,7 +26,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index 5965acb..45968fb 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -38,7 +38,7 @@ // General Purpose Events //#include "acpi/gpe.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl index 0adc9a0..759d669 100644 --- a/src/mainboard/intel/glkrvp/dsdt.asl +++ b/src/mainboard/intel/glkrvp/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/apollolake/acpi/globalnvs.asl> /* CPU */ - #include <soc/intel/apollolake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl index d979e9b..9bc42cf 100644 --- a/src/mainboard/intel/harcuvar/dsdt.asl +++ b/src/mainboard/intel/harcuvar/dsdt.asl @@ -39,7 +39,7 @@ // global NVS and variables #include <soc/intel/denverton_ns/acpi/globalnvs.asl> - #include <soc/intel/denverton_ns/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index c15f80c..53feeb9 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -33,7 +33,7 @@ #include <soc/intel/icelake/acpi/globalnvs.asl> // CPU - #include <soc/intel/icelake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index 4ddc92a..ddb69da 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -32,7 +32,7 @@ #include <soc/intel/skylake/acpi/globalnvs.asl> // CPU - #include <soc/intel/skylake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index c1e3616..af5f99d 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -32,7 +32,7 @@ #include <soc/intel/skylake/acpi/globalnvs.asl> // CPU - #include <soc/intel/skylake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl index 3be22fe..48b24b9 100644 --- a/src/mainboard/intel/leafhill/dsdt.asl +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -27,7 +27,7 @@ #include <soc/intel/apollolake/acpi/globalnvs.asl> /* CPU */ - #include <soc/intel/apollolake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/littleplains/dsdt.asl b/src/mainboard/intel/littleplains/dsdt.asl index 8091a4e..310ad04 100644 --- a/src/mainboard/intel/littleplains/dsdt.asl +++ b/src/mainboard/intel/littleplains/dsdt.asl @@ -38,7 +38,7 @@ #include "acpi/thermal.asl" - #include <cpu/intel/fsp_model_406dx/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/minnow3/dsdt.asl b/src/mainboard/intel/minnow3/dsdt.asl index 3be22fe..48b24b9 100644 --- a/src/mainboard/intel/minnow3/dsdt.asl +++ b/src/mainboard/intel/minnow3/dsdt.asl @@ -27,7 +27,7 @@ #include <soc/intel/apollolake/acpi/globalnvs.asl> /* CPU */ - #include <soc/intel/apollolake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl index 2dc7139..3719154 100644 --- a/src/mainboard/intel/minnowmax/dsdt.asl +++ b/src/mainboard/intel/minnowmax/dsdt.asl @@ -38,7 +38,7 @@ // global NVS and variables #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> - #include <soc/intel/fsp_baytrail/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl index 8091a4e..310ad04 100644 --- a/src/mainboard/intel/mohonpeak/dsdt.asl +++ b/src/mainboard/intel/mohonpeak/dsdt.asl @@ -38,7 +38,7 @@ #include "acpi/thermal.asl" - #include <cpu/intel/fsp_model_406dx/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl index 2cb8e72..ac929a6 100644 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ b/src/mainboard/intel/saddlebrook/dsdt.asl @@ -32,7 +32,7 @@ #include <soc/intel/skylake/acpi/globalnvs.asl> // CPU - #include <soc/intel/skylake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index 48ea66b..42fd7ea 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -36,7 +36,7 @@ //#include "acpi/gpe.asl" // CPU - #include <soc/intel/broadwell/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl index 85ba20b..f0dd7ee 100644 --- a/src/mainboard/kontron/ktqm77/dsdt.asl +++ b/src/mainboard/kontron/ktqm77/dsdt.asl @@ -39,7 +39,7 @@ // General Purpose Events //#include "acpi/gpe.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl index b058657..a04f852 100644 --- a/src/mainboard/lenovo/l520/dsdt.asl +++ b/src/mainboard/lenovo/l520/dsdt.asl @@ -28,7 +28,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl index aeac7c7..0b994c8 100644 --- a/src/mainboard/lenovo/s230u/dsdt.asl +++ b/src/mainboard/lenovo/s230u/dsdt.asl @@ -28,7 +28,7 @@ { #include "acpi/platform.asl" #include "acpi/gpe.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index ba96303..1cb4add 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -39,7 +39,7 @@ // global NVS and variables #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index ba96303..1cb4add 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -39,7 +39,7 @@ // global NVS and variables #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index 3995ee3..3cdebe9 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -27,7 +27,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index ba96303..1cb4add 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -39,7 +39,7 @@ // global NVS and variables #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index ba96303..1cb4add 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -39,7 +39,7 @@ // global NVS and variables #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index ba96303..1cb4add 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -39,7 +39,7 @@ // global NVS and variables #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl index 93495bb..d128c0d 100644 --- a/src/mainboard/lenovo/x131e/dsdt.asl +++ b/src/mainboard/lenovo/x131e/dsdt.asl @@ -28,7 +28,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> // global NVS and variables diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index c406697..8c9bd5a 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -39,7 +39,7 @@ // global NVS and variables #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 8b2fb78..650a315 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -40,7 +40,7 @@ /* General Purpose Events */ #include "acpi/gpe.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index ba96303..1cb4add 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -39,7 +39,7 @@ // global NVS and variables #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index ba96303..1cb4add 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -39,7 +39,7 @@ // global NVS and variables #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/opencellular/rotundu/dsdt.asl b/src/mainboard/opencellular/rotundu/dsdt.asl index 2dc7139..3719154 100644 --- a/src/mainboard/opencellular/rotundu/dsdt.asl +++ b/src/mainboard/opencellular/rotundu/dsdt.asl @@ -38,7 +38,7 @@ // global NVS and variables #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> - #include <soc/intel/fsp_baytrail/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index ebe2917..92994c0 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -33,7 +33,7 @@ /* General Purpose Events */ #include "acpi/gpe.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 405a6b7..bd49349 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/broadwell/acpi/globalnvs.asl> /* CPU */ - #include <soc/intel/broadwell/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/purism/librem_skl/dsdt.asl b/src/mainboard/purism/librem_skl/dsdt.asl index a2397a6..1bf202e 100644 --- a/src/mainboard/purism/librem_skl/dsdt.asl +++ b/src/mainboard/purism/librem_skl/dsdt.asl @@ -32,7 +32,7 @@ #include <soc/intel/skylake/acpi/globalnvs.asl> // CPU - #include <soc/intel/skylake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/roda/rv11/dsdt.asl b/src/mainboard/roda/rv11/dsdt.asl index 4859e6b..859b4cd 100644 --- a/src/mainboard/roda/rv11/dsdt.asl +++ b/src/mainboard/roda/rv11/dsdt.asl @@ -37,7 +37,7 @@ #include "acpi/alsd.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index d9de561..c007432 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -38,7 +38,7 @@ // General Purpose Events //#include "acpi/gpe.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index ef5a273..969ef66 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -38,7 +38,7 @@ #include "acpi/thermal.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index dcec95f..60ba44b 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -29,7 +29,7 @@ { // Some generic macros #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/bd82x6x/acpi/platform.asl> /* global NVS and variables. */ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> diff --git a/src/mainboard/scaleway/tagada/dsdt.asl b/src/mainboard/scaleway/tagada/dsdt.asl index d979e9b..9bc42cf 100644 --- a/src/mainboard/scaleway/tagada/dsdt.asl +++ b/src/mainboard/scaleway/tagada/dsdt.asl @@ -39,7 +39,7 @@ // global NVS and variables #include <soc/intel/denverton_ns/acpi/globalnvs.asl> - #include <soc/intel/denverton_ns/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/siemens/mc_apl1/dsdt.asl b/src/mainboard/siemens/mc_apl1/dsdt.asl index 0eaadb4..9ce3ef8 100644 --- a/src/mainboard/siemens/mc_apl1/dsdt.asl +++ b/src/mainboard/siemens/mc_apl1/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/apollolake/acpi/globalnvs.asl> /* CPU */ - #include <soc/intel/apollolake/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/siemens/mc_tcu3/dsdt.asl b/src/mainboard/siemens/mc_tcu3/dsdt.asl index 2dc7139..3719154 100644 --- a/src/mainboard/siemens/mc_tcu3/dsdt.asl +++ b/src/mainboard/siemens/mc_tcu3/dsdt.asl @@ -38,7 +38,7 @@ // global NVS and variables #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> - #include <soc/intel/fsp_baytrail/acpi/cpu.asl> + #include <cpu/intel/common/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/soc/intel/apollolake/acpi/cpu.asl b/src/soc/intel/apollolake/acpi/cpu.asl deleted file mode 100644 index 8b2e080..0000000 --- a/src/soc/intel/apollolake/acpi/cpu.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ -Method (PPCN) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} \ No newline at end of file diff --git a/src/soc/intel/baytrail/acpi/cpu.asl b/src/soc/intel/baytrail/acpi/cpu.asl deleted file mode 100644 index 775b32f..0000000 --- a/src/soc/intel/baytrail/acpi/cpu.asl +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ -Method (PPCN) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} \ No newline at end of file diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl deleted file mode 100644 index 775b32f..0000000 --- a/src/soc/intel/braswell/acpi/cpu.asl +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ -Method (PPCN) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} \ No newline at end of file diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl deleted file mode 100644 index 9625cac..0000000 --- a/src/soc/intel/braswell/acpi/dptf/cpu.asl +++ /dev/null @@ -1,208 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef DPTF_CPU_PASSIVE -#define DPTF_CPU_PASSIVE 80 -#endif - -#ifndef DPTF_CPU_CRITICAL -#define DPTF_CPU_CRITICAL 90 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC0 -#define DPTF_CPU_ACTIVE_AC0 90 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC1 -#define DPTF_CPU_ACTIVE_AC1 80 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC2 -#define DPTF_CPU_ACTIVE_AC2 70 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC3 -#define DPTF_CPU_ACTIVE_AC3 60 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC4 -#define DPTF_CPU_ACTIVE_AC4 50 -#endif - -External (\_PR.CP00._TSS, MethodObj) -External (\_PR.CP00._TPC, MethodObj) -External (\_PR.CP00._PTC, PkgObj) -External (\_PR.CP00._TSD, PkgObj) -External (\_PR.CP00._PSS, MethodObj) - -Device (B0DB) -{ - Name (_ADR, 0x000B0000) /* Bus 0, Device B, Function 0 */ - - Method (_STA) - { - If (LEqual (\DPTE, One)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - /* - * Processor Throttling Controls - */ - - Method (_TSS) - { - If (CondRefOf (\_PR.CP00._TSS)) { - Return (\_PR.CP00._TSS) - } Else { - Return (Package () - { - Package () { 0, 0, 0, 0, 0 } - }) - } - } - - Method (_TPC) - { - If (CondRefOf (\_PR.CP00._TPC)) { - Return (\_PR.CP00._TPC) - } Else { - Return (0) - } - } - - Method (_PTC) - { - If (CondRefOf (\_PR.CP00._PTC)) { - Return (\_PR.CP00._PTC) - } Else { - Return (Package () - { - Buffer () { 0 }, - Buffer () { 0 } - }) - } - } - - Method (_TSD) - { - If (CondRefOf (\_PR.CP00._TSD)) { - Return (\_PR.CP00._TSD) - } Else { - Return (Package () - { - Package () { 5, 0, 0, 0, 0 } - }) - } - } - - Method (_TDL) - { - If (CondRefOf (\_PR.CP00._TSS)) { - Store (SizeOf (\_PR.CP00._TSS ()), Local0) - Decrement (Local0) - Return (Local0) - } Else { - Return (0) - } - } - - /* - * Processor Performance Control - */ - - Method (_PPC) - { - Return (0) - } - - Method (SPPC, 1) - { - Store (Arg0, \PPCM) - - /* Notify OS to re-read _PPC limit on each CPU */ - \PPCN () - } - - Method (_PSS) - { - If (CondRefOf (\_PR.CP00._PSS)) { - Return (\_PR.CP00._PSS) - } Else { - Return (Package () - { - Package () { 0, 0, 0, 0, 0, 0 } - }) - } - } - - Method (_PDL) - { - /* Check for mainboard specific _PDL override */ - If (CondRefOf (\_SB.MPDL)) { - Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CP00._PSS)) { - Store (SizeOf (\_PR.CP00._PSS ()), Local0) - Decrement (Local0) - Return (Local0) - } Else { - Return (0) - } - } - - /* Return PPCC table defined by mainboard */ - Method (PPCC) - { - Return (\_SB.MPPC) - } - - Method (_CRT) - { - Return (\_SB.DPTF.CTOK(DPTF_CPU_CRITICAL)) - } - - Method (_PSV) - { - Return (\_SB.DPTF.CTOK(DPTF_CPU_PASSIVE)) - } - - Method (_AC0) - { - Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC0)) - } - - Method (_AC1) - { - Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC1)) - } - - Method (_AC2) - { - Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC2)) - } - - Method (_AC3) - { - Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC3)) - } - - Method (_AC4) - { - Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC4)) - } -} diff --git a/src/soc/intel/broadwell/acpi/cpu.asl b/src/soc/intel/broadwell/acpi/cpu.asl deleted file mode 100644 index 8b2e080..0000000 --- a/src/soc/intel/broadwell/acpi/cpu.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ -Method (PPCN) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} \ No newline at end of file diff --git a/src/soc/intel/cannonlake/acpi/cpu.asl b/src/soc/intel/cannonlake/acpi/cpu.asl deleted file mode 100644 index 7c074b8..0000000 --- a/src/soc/intel/cannonlake/acpi/cpu.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ -Method (PPCN) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} \ No newline at end of file diff --git a/src/soc/intel/denverton_ns/acpi/cpu.asl b/src/soc/intel/denverton_ns/acpi/cpu.asl deleted file mode 100644 index 60ecc5c..0000000 --- a/src/soc/intel/denverton_ns/acpi/cpu.asl +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 - 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ -Method (PPCN) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} \ No newline at end of file diff --git a/src/soc/intel/fsp_baytrail/acpi/cpu.asl b/src/soc/intel/fsp_baytrail/acpi/cpu.asl deleted file mode 100644 index 775b32f..0000000 --- a/src/soc/intel/fsp_baytrail/acpi/cpu.asl +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ -Method (PPCN) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} \ No newline at end of file diff --git a/src/soc/intel/icelake/acpi/cpu.asl b/src/soc/intel/icelake/acpi/cpu.asl deleted file mode 100644 index 76d2201..0000000 --- a/src/soc/intel/icelake/acpi/cpu.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ -Method (PPCN) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} \ No newline at end of file diff --git a/src/soc/intel/skylake/acpi/cpu.asl b/src/soc/intel/skylake/acpi/cpu.asl deleted file mode 100644 index 761c435..0000000 --- a/src/soc/intel/skylake/acpi/cpu.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* These come from the dynamically created CPU SSDT */ -External (\_PR.CNOT, MethodObj) - -/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ -Method (PNOT) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ -Method (PPCN) -{ - \_PR.CNOT (0x81) -} - -/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ -Method (TNOT) -{ - \_PR.CNOT (0x82) -} -- To view, visit https://review.coreboot.org/c/coreboot/+/29894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Gerrit-Change-Number: 29894 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/fsp_baytrail: Rework acpi/cpu.asl
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29893 Change subject: soc/intel/fsp_baytrail: Rework acpi/cpu.asl ...................................................................... soc/intel/fsp_baytrail: Rework acpi/cpu.asl Change-Id: I01e4397b9a1c15eff4b856cbc697fa2b4bc9761f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/acpi/cpu.asl 2 files changed, 23 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29893/1 diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index a378f5e..c653343 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -526,6 +526,23 @@ acpigen_pop_len(); } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, pattrs->num_cpus); + + /* Add a method to notify processor nodes */ + acpigen_write_method("\\_PR.CNOT", 1); + for (core = 0; core < pattrs->num_cpus; core++) { + char buffer[DEVICE_PATH_MAX]; + snprintf(buffer, sizeof(buffer), "\\_PR.CP%c%c", + '0' + core / 10, '0' + core % 10); + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(buffer); + acpigen_emit_byte(ARG0_OP); + } + acpigen_pop_len(); + } unsigned long acpi_madt_irq_overrides(unsigned long current) diff --git a/src/soc/intel/fsp_baytrail/acpi/cpu.asl b/src/soc/intel/fsp_baytrail/acpi/cpu.asl index dc26e0a..775b32f 100644 --- a/src/soc/intel/fsp_baytrail/acpi/cpu.asl +++ b/src/soc/intel/fsp_baytrail/acpi/cpu.asl @@ -14,59 +14,23 @@ * GNU General Public License for more details. */ -/* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST - } + \_PR.CNOT (0x81) } /* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ Method (PPCN) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) // _PPC - Notify (\_PR.CP01, 0x80) // _PPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) // _PPC - Notify (\_PR.CP03, 0x80) // _PPC - } + \_PR.CNOT (0x81) } /* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ Method (TNOT) { - If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) // _TPC - Notify (\_PR.CP01, 0x82) // _TPC - } - If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) // _TPC - Notify (\_PR.CP03, 0x82) // _TPC - } -} - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) - } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CP00, \_PR.CP01}) - } Else { - Return (Package() {\_PR.CP00}) - } -} + \_PR.CNOT (0x82) +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/29893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01e4397b9a1c15eff4b856cbc697fa2b4bc9761f Gerrit-Change-Number: 29893 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2018