coreboot-gerrit November 2018

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Change in ...coreboot[master]: src/soc/intel/braswell/include/soc/iomap.h: Correct IO_BASE_SIZE and ...
by Patrick Georgi (Code Review) 28 Nov '18

28 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29392 ) Change subject: src/soc/intel/braswell/include/soc/iomap.h: Correct IO_BASE_SIZE and ILB_BASE_SIZE ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23c3fd608598c5ec2271d393168ac4bf406772b4 Gerrit-Change-Number: 29392 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 11:49:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/common: Fix style issue in spi.c
by Patrick Georgi (Code Review) 28 Nov '18

28 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29841 ) Change subject: sb/intel/common: Fix style issue in spi.c ...................................................................... sb/intel/common: Fix style issue in spi.c Change-Id: I6b9e0e0c643f9b47cfe8bdfffbe247f477ace685 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/29841 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/southbridge/intel/common/spi.c 1 file changed, 54 insertions(+), 52 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 0592379..fe3bf2a 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -196,6 +196,7 @@ static u8 readb_(const void *addr) { u8 v = read8(addr); + printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -204,6 +205,7 @@ static u16 readw_(const void *addr) { u16 v = read16(addr); + printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -212,6 +214,7 @@ static u32 readl_(const void *addr) { u32 v = read32(addr); + printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -347,7 +350,7 @@ if (cntlr->hsfs & HSFS_FDV) { writel_(4, &ich9_spi->fdoc); cntlr->flmap0 = readl_(&ich9_spi->fdod); - writel_ (0x1000, &ich9_spi->fdoc); + writel_(0x1000, &ich9_spi->fdoc); cntlr->flcomp = readl_(&ich9_spi->fdod); } } @@ -439,43 +442,43 @@ optypes = (optypes & 0xfffc) | (trans->type & 0x3); writew_(optypes, cntlr->optype); return 0; - } else { - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr->menubytes; - opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == cntlr->menubytes) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr->optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; } + + /* The lock is on. See if what we need is on the menu. */ + uint8_t optype; + uint16_t opcode_index; + + /* Write Enable is handled as atomic prefix */ + if (trans->opcode == SPI_OPCODE_WREN) + return 0; + + read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr->menubytes; + opcode_index++) { + if (opmenu[opcode_index] == trans->opcode) + break; + } + + if (opcode_index == cntlr->menubytes) { + printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", + trans->opcode); + return -1; + } + + optypes = readw_(cntlr->optype); + optype = (optypes >> (opcode_index * 2)) & 0x3; + if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && + optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && + trans->bytesout >= 3) { + /* We guessed wrong earlier. Fix it up. */ + trans->type = optype; + } + if (optype != trans->type) { + printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", + optype); + return -1; + } + return opcode_index; } static int spi_setup_offset(spi_transaction *trans) @@ -526,7 +529,7 @@ return -1; } -static int spi_is_multichip (void) +static int spi_is_multichip(void) { ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); if (!(cntlr->hsfs & HSFS_FDV)) @@ -689,6 +692,7 @@ { ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF; + writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr); } @@ -773,8 +777,7 @@ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ writew_(hsfc, &cntlr->ich9_spi->hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, len)) - { + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) { printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); ret = -1; goto out; @@ -811,7 +814,7 @@ uint8_t block_len; if (addr + len > flash->size) { - printk (BIOS_ERR, + printk(BIOS_ERR, "Attempt to read %x-%x which is out of chip\n", (unsigned) addr, (unsigned) addr+(unsigned) len); @@ -882,7 +885,7 @@ uint32_t start = addr; if (addr + len > flash->size) { - printk (BIOS_ERR, + printk(BIOS_ERR, "Attempt to write 0x%x-0x%x which is out of chip\n", (unsigned)addr, (unsigned) (addr+len)); return -1; @@ -908,9 +911,8 @@ hsfc |= HSFC_FGO; /* start */ writew_(hsfc, &cntlr->ich9_spi->hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) - { - printk (BIOS_ERR, "SF: write failure at %x\n", + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) { + printk(BIOS_ERR, "SF: write failure at %x\n", addr); return -1; } @@ -944,9 +946,8 @@ memcpy(&flash->spi, spi, sizeof(*spi)); flash->name = "Opaque HW-sequencing"; - ich_hwseq_set_addr (0); - switch ((cntlr->hsfs >> 3) & 3) - { + ich_hwseq_set_addr(0); + switch ((cntlr->hsfs >> 3) & 3) { case 0: flash->sector_size = 256; break; @@ -967,7 +968,7 @@ if ((cntlr->hsfs & HSFS_FDV) && ((cntlr->flmap0 >> 8) & 3)) flash->size += 1 << (19 + ((cntlr->flcomp >> 3) & 7)); - printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); + printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); return 0; } @@ -978,19 +979,20 @@ return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); } -#define SPI_FPR_SHIFT 12 +#define SPI_FPR_SHIFT 12 #define ICH7_SPI_FPR_MASK 0xfff #define ICH9_SPI_FPR_MASK 0x1fff -#define SPI_FPR_BASE_SHIFT 0 +#define SPI_FPR_BASE_SHIFT 0 #define ICH7_SPI_FPR_LIMIT_SHIFT 12 #define ICH9_SPI_FPR_LIMIT_SHIFT 16 #define ICH9_SPI_FPR_RPE (1 << 15) /* Read Protect */ -#define SPI_FPR_WPE (1 << 31) /* Write Protect */ +#define SPI_FPR_WPE (1 << 31) /* Write Protect */ static u32 spi_fpr(u32 base, u32 limit) { u32 ret; u32 mask, limit_shift; + if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) { mask = ICH7_SPI_FPR_MASK; limit_shift = ICH7_SPI_FPR_LIMIT_SHIFT; -- To view, visit https://review.coreboot.org/c/coreboot/+/29841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9e0e0c643f9b47cfe8bdfffbe247f477ace685 Gerrit-Change-Number: 29841 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Add camera acpi support
by Aamir Bohra (Code Review) 28 Nov '18

28 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29883 to look at the new patch set (#2). Change subject: mb/intel/icelake_rvp: Add camera acpi support ...................................................................... mb/intel/icelake_rvp: Add camera acpi support This implementation adds acpi camera support for below sensors: 1. SONY319A: User facing camera interfaced to SOC over i2c2 2. SONY355A: World facing camera interfaced to SOC over i2c3 Change-Id: Ic70cc944ebbbe7784550a643f115d39ecbf989e9 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/Kconfig A src/mainboard/intel/icelake_rvp/acpi/cam0.asl A src/mainboard/intel/icelake_rvp/acpi/cam1.asl A src/mainboard/intel/icelake_rvp/acpi/camera.asl M src/mainboard/intel/icelake_rvp/acpi/mainboard.asl M src/mainboard/intel/icelake_rvp/dsdt.asl 6 files changed, 243 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/29883/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic70cc944ebbbe7784550a643f115d39ecbf989e9 Gerrit-Change-Number: 29883 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Add camera acpi support
by Aamir Bohra (Code Review) 28 Nov '18

28 Nov '18

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29883 Change subject: mb/intel/icelake_rvp: Add camera acpi support ...................................................................... mb/intel/icelake_rvp: Add camera acpi support This implementation adds acpi camera support for below sensors: 1. SONY319A: User facing camera interfaced to SOC over i2c2 2. SONY355A: World facing camera interfaced to SOC over i2c3 Change-Id: Ic70cc944ebbbe7784550a643f115d39ecbf989e9 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/Kconfig A src/mainboard/intel/icelake_rvp/acpi/cam0.asl A src/mainboard/intel/icelake_rvp/acpi/cam1.asl A src/mainboard/intel/icelake_rvp/acpi/camera.asl M src/mainboard/intel/icelake_rvp/acpi/mainboard.asl M src/mainboard/intel/icelake_rvp/dsdt.asl 6 files changed, 243 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/29883/1 diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig index 0741bf8..bf7f855 100644 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ b/src/mainboard/intel/icelake_rvp/Kconfig @@ -7,6 +7,7 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_CAMERA_ACPI select GENERIC_SPD_BIN select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC @@ -35,6 +36,12 @@ string default "Intel_icelake_rvp" +config MAINBOARD_HAS_CAMERA_ACPI + bool + default n + help + Select this option to enable camera ACPI support. + config MAX_CPUS int default 8 diff --git a/src/mainboard/intel/icelake_rvp/acpi/cam0.asl b/src/mainboard/intel/icelake_rvp/acpi/cam0.asl new file mode 100644 index 0000000..ba0c16e --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/acpi/cam0.asl @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C3) +{ + Device (CAM0) + { + Name (_HID, "SONY355A") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "SONY IMX355A Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + I2cSerialBus (0x001A, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + /* Port0 of CAM0 is connected to port0 of CIO2 device */ + Name (_DSD, Package () { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "port0", "PRT0" }, + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 19200000 } + } + }) + + Name (PRT0, Package() { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port", 0 }, + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "endpoint0", "EP00" }, + } + }) + + Name (EP00, Package() { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "endpoint", 0 }, + Package () { "clock-lanes", 0 }, + Package () { "data-lanes", + Package () { 1, 2, 3, 4 } + }, + Package () { "link-frequencies", + Package() { 1190400000, 640000000 } + }, + } + }) + + Method (SSDB, 0, Serialized) + { + Return (Buffer (0x5E) + { + /* 0000 */ 0x00, 0x50, 0x00, 0x00, 0x00, 0x00,0x00, 0x00, + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0028 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0030 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0038 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0040 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0048 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x03, + /* 0050 */ 0x09, 0x00, 0x02, 0x01, 0x00, 0x01, 0x00, 0x36, + /* 0058 */ 0x6E, 0x01, 0x00, 0x00, 0x00, 0x00 + }) + } + } + + Device (VCM0) + { + Name (_HID, "PRP0001") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "AKM AF DAC") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C3", + 0x00, ResourceConsumer, , + ) + }) + + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "asahi-kasei,ak7375" }, + } + }) + } +} \ No newline at end of file diff --git a/src/mainboard/intel/icelake_rvp/acpi/cam1.asl b/src/mainboard/intel/icelake_rvp/acpi/cam1.asl new file mode 100644 index 0000000..d67cec9 --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/acpi/cam1.asl @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C2) +{ + Device (CAM1) + { + Name (_HID, "SONY319A") /* _HID: Hardware ID */ + Name (_UID, Zero) /* _UID: Unique ID */ + Name (_DDN, "Sony IMX319 Camera") /* _DDN: DOS Device Name */ + + Method (_STA, 0, NotSerialized) /* _STA: Status */ + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C2", + 0x00, ResourceConsumer, , + ) + }) + + + /* Port0 of CAM1 is connected to port1 of CIO2 device */ + Name (_DSD, Package () { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "port0", "PRT0" }, + }, + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "clock-frequency", 19200000 }, + } + }) + + Name (PRT0, Package() { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "port", 0 }, + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () { "endpoint0", "EP00" }, + } + }) + + Name (EP00, Package() { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "endpoint", 0 }, + Package () { "clock-lanes", 0 }, + Package () { "data-lanes", + Package () { 1, 2, 3, 4 } + }, + Package () { "link-frequencies", + Package() { 844800000 } + }, + } + }) + + Method (SSDB, 0, Serialized) + { + Return (Buffer (0x5E) + { + /* 0000 */ 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0028 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0030 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0038 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0040 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0048 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x03, + /* 0050 */ 0x09, 0x00, 0x02, 0x01, 0x00, 0x01, 0x00, 0x36, + /* 0058 */ 0x6E, 0x01, 0x00, 0x00, 0x00, 0x00 + }) + } + } +} \ No newline at end of file diff --git a/src/mainboard/intel/icelake_rvp/acpi/camera.asl b/src/mainboard/intel/icelake_rvp/acpi/camera.asl new file mode 100644 index 0000000..81d54f8 --- /dev/null +++ b/src/mainboard/intel/icelake_rvp/acpi/camera.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "cam0.asl" +#include "cam1.asl" diff --git a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl index 49ae2e6..80064b3 100644 --- a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl +++ b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl @@ -22,3 +22,7 @@ } } #endif + +#if IS_ENABLED(CONFIG_MAINBOARD_HAS_CAMERA_ACPI) + #include "camera.asl" +#endif \ No newline at end of file diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index c15f80c..85efe4d 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -40,6 +40,7 @@ { #include <soc/intel/icelake/acpi/northbridge.asl> #include <soc/intel/icelake/acpi/southbridge.asl> + #include <soc/intel/icelake/acpi/ipu.asl> } } -- To view, visit https://review.coreboot.org/c/coreboot/+/29883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic70cc944ebbbe7784550a643f115d39ecbf989e9 Gerrit-Change-Number: 29883 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 28 Nov '18

28 Nov '18

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 5: > Patch Set 5: > > (1 comment) The Intel Quark used Fsp1.1 also, but has label bootblock_pre_c_entry already defined. This will cause build conflict. -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 11:10:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common/acpi: Add common CPU methods
by Arthur Heymans (Code Review) 28 Nov '18

28 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29754 ) Change subject: soc/intel/common/acpi: Add common CPU methods ...................................................................... Patch Set 1: > Patch Set 1: > > It is a good idea, but I think it is a much larger change than just fixing the cannonlake bug where these methods don't exist, which I could do instead of refactoring it into common code if we want to instead push for a change in this direction. > > However, I think calling back into an SSDT from the DSDT is still not allowed by the linux kernel, and currently all the DPTF code is in the DSDT... calling SSDT from DSDT works just fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/29754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd467ef84a391698cd395172c3f0d4e801bdd09b Gerrit-Change-Number: 29754 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 28 Nov 2018 10:57:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: siemens/mc_apl5: Disable PCI clock outputs on XIO bridges
by Werner Zeh (Code Review) 28 Nov '18

28 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29882 ) Change subject: siemens/mc_apl5: Disable PCI clock outputs on XIO bridges ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91 Gerrit-Change-Number: 29882 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 09:49:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: siemens/mc_apl5: Set bus master bit for on-board PCI device
by Werner Zeh (Code Review) 28 Nov '18

28 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29881 ) Change subject: siemens/mc_apl5: Set bus master bit for on-board PCI device ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb Gerrit-Change-Number: 29881 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 09:46:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
by Patrick Rudolph (Code Review) 28 Nov '18

28 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/29662/5/src/soc/intel/braswell/bootblock/ca… File src/soc/intel/braswell/bootblock/cache_as_ram_cbootblock.S: https://review.coreboot.org/#/c/29662/5/src/soc/intel/braswell/bootblock/ca… PS5, Line 21: #include <device/pci_def.h> > Specific support (provide timestamp, bootblock_pre_c_entry label) for C bootblock is required. I don't see why it's specific to braswell. Can you place it in drivers/intel/fsp1_1 ? That way all FSP1.1 can share the same code and be migrated to c bootblock. -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 09:12:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: tss: implement Cr50 vendor-specific VENDOR_CC_TPM_MODE
by build bot (Jenkins) (Code Review) 28 Nov '18

28 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29648 ) Change subject: tss: implement Cr50 vendor-specific VENDOR_CC_TPM_MODE ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/29648/5/src/security/tpm/tss/tcg-2.0/tss_ma… File src/security/tpm/tss/tcg-2.0/tss_marshaling.c: https://review.coreboot.org/#/c/29648/5/src/security/tpm/tss/tcg-2.0/tss_ma… PS5, Line 482: break; break is not useful after a goto or return -- To view, visit https://review.coreboot.org/c/coreboot/+/29648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd55708797d2b17336fcbe80c0724957f7052e90 Gerrit-Change-Number: 29648 Gerrit-PatchSet: 5 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Comment-Date: Wed, 28 Nov 2018 09:00:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2018