coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 27 Nov '18

27 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 24: (2 comments) https://review.coreboot.org/#/c/29563/24/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/24/src/include/memlayout.h@168 PS24, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/24/src/include/memlayout.h@168 PS24, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 24 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 27 Nov 2018 10:41:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell/hda.c: Configure HDA codecs
by build bot (Jenkins) (Code Review) 27 Nov '18

27 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29394 ) Change subject: src/soc/intel/braswell/hda.c: Configure HDA codecs ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/29394/6/src/soc/intel/braswell/hda.c File src/soc/intel/braswell/hda.c: https://review.coreboot.org/#/c/29394/6/src/soc/intel/braswell/hda.c@37 PS6, Line 37: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/29394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63 Gerrit-Change-Number: 29394 Gerrit-PatchSet: 6 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Nov 2018 10:32:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/amd/pi/00{630F01, 730F01}: Use ARRAY_SIZE
by HAOUAS Elyes (Code Review) 27 Nov '18

27 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29860 Change subject: nb/amd/pi/00{630F01,730F01}: Use ARRAY_SIZE ...................................................................... nb/amd/pi/00{630F01,730F01}: Use ARRAY_SIZE Use already defined ARRAY_SIZE macro. Change-Id: Ie22e3557e958b562816921a985411dd55c712142 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/pi/00630F01/dimmSpd.c M src/northbridge/amd/pi/00730F01/dimmSpd.c 2 files changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/29860/1 diff --git a/src/northbridge/amd/pi/00630F01/dimmSpd.c b/src/northbridge/amd/pi/00630F01/dimmSpd.c index 28e3fe4..dcf3192 100644 --- a/src/northbridge/amd/pi/00630F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00630F01/dimmSpd.c @@ -23,8 +23,6 @@ #include <northbridge/amd/pi/dimmSpd.h> -#define DIMENSION(array)(sizeof(array)/ sizeof(array [0])) - AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) { int spdAddress; @@ -34,11 +32,11 @@ if ((dev == 0) || (config == 0)) return AGESA_ERROR; - if (info->SocketId >= DIMENSION(config->spdAddrLookup )) + if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) return AGESA_ERROR; - if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0])) + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) return AGESA_ERROR; spdAddress = config->spdAddrLookup diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c index bbcbfe9..b7ffdb0 100644 --- a/src/northbridge/amd/pi/00730F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c @@ -23,8 +23,6 @@ #include <northbridge/amd/pi/dimmSpd.h> -#define DIMENSION(array)(sizeof(array)/ sizeof(array [0])) - AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) { int spdAddress; @@ -34,11 +32,11 @@ if ((dev == 0) || (config == 0)) return AGESA_ERROR; - if (info->SocketId >= DIMENSION(config->spdAddrLookup )) + if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) + if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) return AGESA_ERROR; - if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0])) + if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) return AGESA_ERROR; spdAddress = config->spdAddrLookup -- To view, visit https://review.coreboot.org/c/coreboot/+/29860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie22e3557e958b562816921a985411dd55c712142 Gerrit-Change-Number: 29860 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/hp/compaq_8200_elite_sff: Fix SATA port map
by Felix Held (Code Review) 27 Nov '18

27 Nov '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29855 ) Change subject: mb/hp/compaq_8200_elite_sff: Fix SATA port map ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be2b4f33882f6f71213f8173cdb945fc9b7af06 Gerrit-Change-Number: 29855 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 27 Nov 2018 10:23:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation/../../kblrvp11: Add RVP11 documentation
by PraveenX Hodagatta Pranesh (Code Review) 27 Nov '18

27 Nov '18

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29859 Change subject: Documentation/../../kblrvp11: Add RVP11 documentation ...................................................................... Documentation/../../kblrvp11: Add RVP11 documentation Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> Change-Id: I01509c2fa2c127b77ae72b8b0aaac0f826b0bedd --- M Documentation/mainboard/index.md A Documentation/mainboard/intel/kblrvp11.md 2 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/29859/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 128f0c1..62fd276 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -24,6 +24,7 @@ - [DG43GT](intel/dg43gt.md) - [IceLake RVP](intel/icelake_rvp.md) +- [KBLRVP11](intel/kblrvp11.md) ## Foxconn diff --git a/Documentation/mainboard/intel/kblrvp11.md b/Documentation/mainboard/intel/kblrvp11.md new file mode 100644 index 0000000..674f5e2 --- /dev/null +++ b/Documentation/mainboard/intel/kblrvp11.md @@ -0,0 +1,67 @@ +# Intel Kaby lake RVP11 + +## Specs + +* 1 SATA cable connect +* 1 SATAe direct +* 2 USB2.0 connector +* 4 USB3.0 connector +* 1 Gigabit Ethernet +* 1 x4 PCIe slot +* 1 x1 PCIe slot +* 1 X16 PEG slot +* UART debug DB9 connector +* 4 DIMMS with DDR4 memory +* SPI flash +* Audio Jack +* PS2 Keyboard and Mouse +* Display: HDMI, DP, VGA + +## Target Audience + +* OEMs, internal only + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | W25Q128FV | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Write protection | No | ++---------------------+------------+ +| Dual BIOS feature | No | ++---------------------+------------+ +``` + +### Instruction to flash coreboot to SPI + +1. Dediprog SF600 with adapter B is used. +2. Make sure power supply is disconnected from board. +3. Connect Dediprog SF600 to header at J7H1. +4. Ensure that "currently working on" is in "application memory chip 1" +5. Go to "file" and select the .rom file (16 MB) to program chip1. +6. Execute the batch operation to erase and program the chip. + +## Technology + +```eval_rst ++------------------+---------------------------------------------------+ +| CPU | Kaby lake H (i7-7820EQ) | ++------------------+---------------------------------------------------+ +| PCH | Skylake PCH-H (called SPT-H) | ++------------------+---------------------------------------------------+ +| Coprocessor | Intel ME | ++------------------+---------------------------------------------------+ +``` + +[W25Q128FV]: https://www.winbond.com/resource-files/w25q128fv%20rev.m%2005132016%20kms.p… -- To view, visit https://review.coreboot.org/c/coreboot/+/29859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01509c2fa2c127b77ae72b8b0aaac0f826b0bedd Gerrit-Change-Number: 29859 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/siemens/mc_{apl1, tcu3}: [test] Fix sizeof on array function
by HAOUAS Elyes (Code Review) 27 Nov '18

27 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29858 Change subject: mb/siemens/mc_{apl1,tcu3}: [test] Fix sizeof on array function ...................................................................... mb/siemens/mc_{apl1,tcu3}: [test] Fix sizeof on array function Change-Id: I982a7a9baf22998503da0e94952fbb30124dfe28 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/siemens/mc_apl1/romstage.c M src/mainboard/siemens/mc_tcu3/romstage.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29858/1 diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index 1483636..5dad9d5 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -48,7 +48,7 @@ return; } - if (hwilib_get_field(SPD, spd, sizeof(spd)) != sizeof(spd)) { + if (hwilib_get_field(SPD, spd, sizeof(*spd)) != sizeof(*spd)) { printk(BIOS_ERR, "SPD not found in HWInfo, use defaults for FSP-M.\n"); return; diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c index 69e7d21..0e28821 100644 --- a/src/mainboard/siemens/mc_tcu3/romstage.c +++ b/src/mainboard/siemens/mc_tcu3/romstage.c @@ -177,7 +177,7 @@ return; } - if (hwilib_get_field(SPD, spd, sizeof(spd)) != sizeof(spd)) { + if (hwilib_get_field(SPD, spd, sizeof(*spd)) != sizeof(*spd)) { printk(BIOS_ERR, "SPD not found in HWInfo, use defaults for DDR3.\n"); return; -- To view, visit https://review.coreboot.org/c/coreboot/+/29858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I982a7a9baf22998503da0e94952fbb30124dfe28 Gerrit-Change-Number: 29858 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {broadcom/cygnus, intel/braswell}: Use DEVICE_NOOP
by HAOUAS Elyes (Code Review) 27 Nov '18

27 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29857 Change subject: {broadcom/cygnus,intel/braswell}: Use DEVICE_NOOP ...................................................................... {broadcom/cygnus,intel/braswell}: Use DEVICE_NOOP Use already defined DEVICE_NOOP instead. Change-Id: Ie6182f273cba3073c84a502c34a002dee6122c2f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/broadcom/cygnus/soc.c M src/soc/intel/braswell/chip.c 2 files changed, 6 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29857/1 diff --git a/src/soc/broadcom/cygnus/soc.c b/src/soc/broadcom/cygnus/soc.c index 090d122..1e47f69 100644 --- a/src/soc/broadcom/cygnus/soc.c +++ b/src/soc/broadcom/cygnus/soc.c @@ -26,14 +26,10 @@ usb_init(); } -static void soc_noop(struct device *dev) -{ -} - static struct device_operations soc_ops = { - .read_resources = soc_noop, - .set_resources = soc_noop, - .enable_resources = soc_noop, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, .init = soc_init, .scan_bus = 0, }; diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index ccd6c9f..6575305 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -37,12 +37,10 @@ .scan_bus = pci_domain_scan_bus, }; -static void cpu_bus_noop(struct device *dev) { } - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, .init = soc_init_cpus }; -- To view, visit https://review.coreboot.org/c/coreboot/+/29857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6182f273cba3073c84a502c34a002dee6122c2f Gerrit-Change-Number: 29857 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/{baytrail, broadwell}: Correct Chromeos RAM reservation
by Frans Hendriks (Code Review) 27 Nov '18

27 Nov '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29856 Change subject: soc/intel/{baytrail,broadwell}: Correct Chromeos RAM reservation ...................................................................... soc/intel/{baytrail,broadwell}: Correct Chromeos RAM reservation RAM is reserved for Chromeos even when Chrome is not used. Use CONFIG_CHROMEOS to determine is RAM must be reserved. BUG=N/A TEST=Intel BayTrail CRB Change-Id: Ic1f5089227f802e2b2f62dc02fa0d1648c1855b5 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/baytrail/northcluster.c M src/soc/intel/broadwell/systemagent.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/29856/1 diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 8271746..0869c7b 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -131,7 +131,8 @@ reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); - chromeos_reserve_ram_oops(dev, index++); + if (IS_ENABLED(CONFIG_CHROMEOS)) + chromeos_reserve_ram_oops(dev, index++); } static struct device_operations nc_ops = { diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 7147750..8013979 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -372,7 +372,8 @@ reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); - chromeos_reserve_ram_oops(dev, index++); + if (IS_ENABLED(CONFIG_CHROMEOS)) + chromeos_reserve_ram_oops(dev, index++); *resource_cnt = index; } -- To view, visit https://review.coreboot.org/c/coreboot/+/29856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1f5089227f802e2b2f62dc02fa0d1648c1855b5 Gerrit-Change-Number: 29856 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/hp/compaq_8200_elite_sff: Fix SATA port map
by Patrick Rudolph (Code Review) 27 Nov '18

27 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29855 Change subject: mb/hp/compaq_8200_elite_sff: Fix SATA port map ...................................................................... mb/hp/compaq_8200_elite_sff: Fix SATA port map Assign correct SATA port map. Tested on HP8200: All SATA ports are now usable in GNU/Linux. Change-Id: I5be2b4f33882f6f71213f8173cdb945fc9b7af06 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/29855/1 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index e7aecdb..61bf43c 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -52,7 +52,7 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0x13" + register "sata_port_map" = "0xf" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x0" device pci 16.0 on # Management Engine Interface 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be2b4f33882f6f71213f8173cdb945fc9b7af06 Gerrit-Change-Number: 29855 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/portwell/m107: Do initial mainboard commit
by build bot (Jenkins) (Code Review) 27 Nov '18

27 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29470 ) Change subject: src/mainboard/portwell/m107: Do initial mainboard commit ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/irqrout… File src/mainboard/portwell/m107/irqroute.h: https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/irqrout… PS8, Line 39: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/irqrout… PS8, Line 60: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/29470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Gerrit-Change-Number: 29470 Gerrit-PatchSet: 8 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 27 Nov 2018 09:33:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2018