coreboot-gerrit November 2018

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Change in ...coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Hellsenberg (Code Review) 24 Nov '18

24 Nov '18

Hellsenberg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 2: > Patch Set 2: > > > @Nico can you add the option to all remaining boards? > > Looks like a tedious job. Let's say it has rather low priority for me. > Especially as long as the MP init doesn't work with HT disabled (Arthur's > patches should help there). > > Wouldn't mind if somebody takes this over. > > Or maybe I'll just turn it into a Kconfig... Once this works, I can reflect the changes on other boards. Just bother me (Hellsenberg) on IRC, or send me an email. -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Hellsenberg <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Sat, 24 Nov 2018 07:45:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/scripts/maintainers.go: drop special case for "THE REST"
by Philipp Deppenwiese (Code Review) 24 Nov '18

24 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29658 ) Change subject: util/scripts/maintainers.go: drop special case for "THE REST" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba7f10dc87301911ff5f73c182b41c268fba310a Gerrit-Change-Number: 29658 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Hellsenberg <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 24 Nov 2018 04:42:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: MAINTAINERS: Drop "the rest" component
by Philipp Deppenwiese (Code Review) 24 Nov '18

24 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29657 ) Change subject: MAINTAINERS: Drop "the rest" component ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I220afe27e78aa5358fca61851242812f2d763992 Gerrit-Change-Number: 29657 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Hellsenberg <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 24 Nov 2018 04:42:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: payloads/external/SeaBIOS/Kconfig: fix native VGA dependency
by Marcello Sylvester Bauer (Code Review) 24 Nov '18

24 Nov '18

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29823 Change subject: payloads/external/SeaBIOS/Kconfig: fix native VGA dependency ...................................................................... payloads/external/SeaBIOS/Kconfig: fix native VGA dependency Allow the inclusion of a generated option rom despite the presence of a VGA BIOS. Change-Id: Ic3a219c2dc2133c3328192840538f0fbd1ed935a Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> --- M payloads/external/SeaBIOS/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29823/1 diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 181a9d6..a0e4671 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -54,7 +54,7 @@ config SEABIOS_VGA_COREBOOT prompt "Include generated option rom that implements legacy VGA BIOS compatibility" default y if !VENDOR_EMULATION - depends on !(VGA_BIOS || VGA_ROM_RUN) && (VGA_TEXT_FRAMEBUFFER || LINEAR_FRAMEBUFFER) + depends on VGA_ROM_RUN && (VGA_TEXT_FRAMEBUFFER || LINEAR_FRAMEBUFFER) bool help coreboot can initialize the GPU of some mainboards. -- To view, visit https://review.coreboot.org/c/coreboot/+/29823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3a219c2dc2133c3328192840538f0fbd1ed935a Gerrit-Change-Number: 29823 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/lenovo/t530/thermal.h: adjust W530 junction temperatur
by Marcello Sylvester Bauer (Code Review) 24 Nov '18

24 Nov '18

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29822 Change subject: mainboard/lenovo/t530/thermal.h: adjust W530 junction temperatur ...................................................................... mainboard/lenovo/t530/thermal.h: adjust W530 junction temperatur Change the critical temperature of W530 Thikpads to 105 degree. TODO: CPU lookup to set critical temperature. Only the following T530 CPU's need a junction temperatur of 100 degrees: - i3-2370M - i5-2520M Change-Id: Ib13d4d7c3f710b7e353bbedefd30f2ee300a01f9 Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> --- M src/mainboard/lenovo/t530/thermal.h 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/29822/1 diff --git a/src/mainboard/lenovo/t530/thermal.h b/src/mainboard/lenovo/t530/thermal.h index 0b24ea8..a48235a 100644 --- a/src/mainboard/lenovo/t530/thermal.h +++ b/src/mainboard/lenovo/t530/thermal.h @@ -17,8 +17,17 @@ #ifndef T530_THERMAL_H #define T530_THERMAL_H - /* Temperature which OS will shutdown at */ + /* Temperature which OS will shutdown at + * TODO: CPU lookup to set critical temperature. + * Only the following CPU's need a junction temperatur of 100 degrees: + - i3-2370M + - i5-2520M + */ + #if IS_ENABLED(CONFIG_BOARD_LENOVO_W530) + #define CRITICAL_TEMPERATURE 105 + #else #define CRITICAL_TEMPERATURE 100 + #endif /* Temperature which OS will throttle CPU */ #define PASSIVE_TEMPERATURE 90 -- To view, visit https://review.coreboot.org/c/coreboot/+/29822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib13d4d7c3f710b7e353bbedefd30f2ee300a01f9 Gerrit-Change-Number: 29822 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Nico Huber (Code Review) 23 Nov '18

23 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 2: > @Nico can you add the option to all remaining boards? Looks like a tedious job. Let's say it has rather low priority for me. Especially as long as the MP init doesn't work with HT disabled (Arthur's patches should help there). Wouldn't mind if somebody takes this over. Or maybe I'll just turn it into a Kconfig... -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Hellsenberg <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Fri, 23 Nov 2018 23:32:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Philipp Deppenwiese (Code Review) 23 Nov '18

23 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 2: @Nico can you add the option to all remaining boards? -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Hellsenberg <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Fri, 23 Nov 2018 22:56:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/bd82x6x/early_usb.c: Fix formatting
by Felix Held (Code Review) 23 Nov '18

23 Nov '18

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29428 ) Change subject: sb/intel/bd82x6x/early_usb.c: Fix formatting ...................................................................... sb/intel/bd82x6x/early_usb.c: Fix formatting Remove whitespace between the function name and open parenthesis, and fix 81+ characters lines. Unnecessary comment about 'include sandybridge.h'removed. Change-Id: I0db1263ec11240003fe1f7080c758994fc0224d3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/29428 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/bd82x6x/early_usb.c 1 file changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Jonathan Neuschäfer: Looks good to me, but someone else must approve diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index d4ff783..1044953 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -17,11 +17,10 @@ #include <arch/io.h> #include <device/pci_ids.h> #include <device/pci_def.h> -#include <northbridge/intel/sandybridge/sandybridge.h> /* For DEFAULT_RCBABASE. */ +#include <northbridge/intel/sandybridge/sandybridge.h> #include "pch.h" -void -early_usb_init (const struct southbridge_usb_port *portmap) +void early_usb_init(const struct southbridge_usb_port *portmap) { u32 reg32; const u32 rcba_dump[8] = { @@ -35,41 +34,42 @@ /* Activate PMBAR. */ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ + /* Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Unlock registers. */ outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN, DEFAULT_PMBASE | UPRWC); for (i = 0; i < 14; i++) - write32 (DEFAULT_RCBABASE + (0x3500 + 4 * i), + write32(DEFAULT_RCBABASE + (0x3500 + 4 * i), currents[portmap[i].current]); for (i = 0; i < 10; i++) - write32 (DEFAULT_RCBABASE + (0x3538 + 4 * i), 0); + write32(DEFAULT_RCBABASE + (0x3538 + 4 * i), 0); for (i = 0; i < 8; i++) - write32 (DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]); + write32(DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]); for (i = 0; i < 8; i++) - write32 (DEFAULT_RCBABASE + (0x3580 + 4 * i), 0); + write32(DEFAULT_RCBABASE + (0x3580 + 4 * i), 0); reg32 = 0; for (i = 0; i < 14; i++) if (!portmap[i].enabled) reg32 |= (1 << i); - write32 (DEFAULT_RCBABASE + USBPDO, reg32); + write32(DEFAULT_RCBABASE + USBPDO, reg32); reg32 = 0; for (i = 0; i < 8; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); - write32 (DEFAULT_RCBABASE + USBOCM1, reg32); + write32(DEFAULT_RCBABASE + USBOCM1, reg32); reg32 = 0; for (i = 8; i < 14; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); - write32 (DEFAULT_RCBABASE + USBOCM2, reg32); + write32(DEFAULT_RCBABASE + USBOCM2, reg32); for (i = 0; i < 22; i++) - write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); + write32(DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); - pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x14, 0), 0xe4, 0x00000000); /* Relock registers. */ outw(0, DEFAULT_PMBASE | UPRWC); -- To view, visit https://review.coreboot.org/c/coreboot/+/29428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0db1263ec11240003fe1f7080c758994fc0224d3 Gerrit-Change-Number: 29428 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Hellsenberg <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: sb/intel/bd82x6x/early_usb.c: Fix formatting
by Felix Held (Code Review) 23 Nov '18

23 Nov '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29428 ) Change subject: sb/intel/bd82x6x/early_usb.c: Fix formatting ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0db1263ec11240003fe1f7080c758994fc0224d3 Gerrit-Change-Number: 29428 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Hellsenberg <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 23 Nov 2018 21:54:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/kahlee: Enable 2T mode for liara in DVT phase
by Martin Roth (Code Review) 23 Nov '18

23 Nov '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29779 ) Change subject: mb/google/kahlee: Enable 2T mode for liara in DVT phase ...................................................................... mb/google/kahlee: Enable 2T mode for liara in DVT phase Change the board id detection to support rev5, since the 2T mode still needed in DVT build. BUG=b:116082728 TEST=verify by ODM. Change-Id: Ibb4cc1fd2bb54984cb7a8856ed7b9f49b78eddce Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29779 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/OemCustomize.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 12e5072..fc8ff32 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -58,7 +58,7 @@ void OemPostParams(AMD_POST_PARAMS *PostParams) { - if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 4)) + if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 5)) PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4LiaraMemoryConfiguration; else -- To view, visit https://review.coreboot.org/c/coreboot/+/29779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb4cc1fd2bb54984cb7a8856ed7b9f49b78eddce Gerrit-Change-Number: 29779 Gerrit-PatchSet: 2 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-MessageType: merged

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coreboot-gerrit November 2018