coreboot-gerrit November 2018

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Change in ...coreboot[master]: MAINTAINERS: Add myself as maintainer for the getac/p470
by Patrick Georgi (Code Review) 21 Nov '18

21 Nov '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29782 Change subject: MAINTAINERS: Add myself as maintainer for the getac/p470 ...................................................................... MAINTAINERS: Add myself as maintainer for the getac/p470 Change-Id: Iae87a2e6f223f1d6e39034be4c8b511187eca6f5 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M MAINTAINERS 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/29782/1 diff --git a/MAINTAINERS b/MAINTAINERS index 81ccafc..8a75bb0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -163,6 +163,11 @@ S: Maintained F: src/mainboard/lenovo/ +GETAC P470 MAINBOARD +M: Patrick Georgi <patrick(a)georgi.software> +S: Maintained +F: src/mainboard/getac/p470 + INTEL PINEVIEW CHIPSET M: Damien Zammit <damien(a)zamaudio.com> S: Odd Fixes -- To view, visit https://review.coreboot.org/c/coreboot/+/29782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae87a2e6f223f1d6e39034be4c8b511187eca6f5 Gerrit-Change-Number: 29782 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/scripts/maintainers.go: file: queries are more stable with quotes
by Patrick Georgi (Code Review) 21 Nov '18

21 Nov '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29781 Change subject: util/scripts/maintainers.go: file: queries are more stable with quotes ...................................................................... util/scripts/maintainers.go: file: queries are more stable with quotes The gerrit docs aren't very explicit about it, but file:"^foo$" is more robust than file:^foo$. Change-Id: I16c7d972d365cd04ca5fbb78012ad4eaad667be6 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/scripts/maintainers.go 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29781/1 diff --git a/util/scripts/maintainers.go b/util/scripts/maintainers.go index 76306c8..31a720c 100644 --- a/util/scripts/maintainers.go +++ b/util/scripts/maintainers.go @@ -278,7 +278,7 @@ } fmt.Println("#", subsystem.name) for _, path := range subsystem.paths { - fmt.Println("[filter \"file:" + path_to_regexstr(path) + "\"]") + fmt.Println("[filter \"file:\\\"" + path_to_regexstr(path) + "\\\"\"]") for _, maint := range subsystem.maintainer { fmt.Println(" reviewer =", extract_maintainer(maint)) } -- To view, visit https://review.coreboot.org/c/coreboot/+/29781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16c7d972d365cd04ca5fbb78012ad4eaad667be6 Gerrit-Change-Number: 29781 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratio
by Huang Jin (Code Review) 21 Nov '18

21 Nov '18

Huang Jin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29772 ) Change subject: soc/intel/apollolake: Add Kconfig switch to enable minimum clock ratio ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073 Gerrit-Change-Number: 29772 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 21 Nov 2018 20:48:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: intelblocks/cpu: Add function to set CPU clock to minimum value
by Huang Jin (Code Review) 21 Nov '18

21 Nov '18

Huang Jin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29771 ) Change subject: intelblocks/cpu: Add function to set CPU clock to minimum value ...................................................................... Patch Set 3: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/29771/3/src/soc/intel/common/block/cpu/cpul… File src/soc/intel/common/block/cpu/cpulib.c: https://review.coreboot.org/#/c/29771/3/src/soc/intel/common/block/cpu/cpul… PS3, Line 144: * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with the value nit: bit 15:8 -- To view, visit https://review.coreboot.org/c/coreboot/+/29771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Gerrit-Change-Number: 29771 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 20:23:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/octopus: Configure all debug header lines as NC
by Furquan Shaikh (Code Review) 21 Nov '18

21 Nov '18

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/29780 ) Change subject: mb/google/octopus: Configure all debug header lines as NC ...................................................................... mb/google/octopus: Configure all debug header lines as NC This change configures all the pads going to debug header as not connected. BUG=b:111569213 BRANCH=None TEST=None Change-Id: Ie3ffdbf6ad9b1682deaada91b5c225b4c8dd035b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c 1 file changed, 43 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29780/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3ffdbf6ad9b1682deaada91b5c225b4c8dd035b Gerrit-Change-Number: 29780 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/octopus: Configure all debug header lines as NC
by build bot (Jenkins) (Code Review) 21 Nov '18

21 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29780 ) Change subject: mb/google/octopus: Configure all debug header lines as NC ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/29780/1/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/29780/1/src/mainboard/google/octopus/varian… PS1, Line 52: PAD_NC(GPIO_24,UP_20K), /* TRACE_1_DATA6_VNN -- debug header NC */ space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29780/1/src/mainboard/google/octopus/varian… PS1, Line 53: PAD_NC(GPIO_25,UP_20K), /* TRACE_1_DATA7_VNN -- debug header NC */ space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/29780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3ffdbf6ad9b1682deaada91b5c225b4c8dd035b Gerrit-Change-Number: 29780 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 20:07:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/octopus: Configure all debug header lines as NC
by Furquan Shaikh (Code Review) 21 Nov '18

21 Nov '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29780 Change subject: mb/google/octopus: Configure all debug header lines as NC ...................................................................... mb/google/octopus: Configure all debug header lines as NC This change configures all the pads going to debug header as not connected. BUG=b:111569213 BRANCH=None TEST=None Change-Id: Ie3ffdbf6ad9b1682deaada91b5c225b4c8dd035b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c 1 file changed, 43 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29780/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 8af11bf..c8b36ef 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -25,50 +25,50 @@ */ static const struct pad_config gpio_table[] = { /* NORTHWEST COMMUNITY GPIOS */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_0, NONE, DEEP, NF1), /* TCK */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_1, DN_20K, DEEP, NF1), /* TRST_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_2, NONE, DEEP, NF1), /* TMS */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_3, NONE, DEEP, NF1), /* TDI */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_4, NONE, DEEP, NF1), /* TDO */ + PAD_NC(GPIO_0, DN_20K), /* TCK -- debug header NC */ + PAD_NC(GPIO_1, DN_20K), /* TRST_B -- debug header NC */ + PAD_NC(GPIO_2, UP_20K), /* TMS -- debug header NC */ + PAD_NC(GPIO_3, UP_20K), /* TDI -- debug header NC */ + PAD_NC(GPIO_4, UP_20K), /* TDO -- debug header NC */ PAD_NC(GPIO_5, UP_20K), /* JTAGX -- unused */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_6, NONE, DEEP, NF1), /* CX_PREQ_B */ - PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_7, NONE, DEEP, NF1), /* CX_PRDY_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_CLK_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA0_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA1_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA2_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA3_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA4_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA5_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA6_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_0_DATA7_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_17, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_CLK_1 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_18, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_8 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_19, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_9 */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_20, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* DBG_PTI_DATA_10 */ + PAD_NC(GPIO_6, UP_20K), /* CX_PREQ_B -- debug header NC */ + PAD_NC(GPIO_7, UP_20K), /* CX_PRDY_B -- debug header NC */ + PAD_NC(GPIO_8, DN_20K), /* TRACE_0_CLK_VNN -- debug header NC */ + PAD_NC(GPIO_9, DN_20K), /* TRACE_0_DATA0_VNN -- debug header NC */ + PAD_NC(GPIO_10, DN_20K), /* TRACE_0_DATA1_VNN -- debug header NC */ + PAD_NC(GPIO_11, DN_20K), /* TRACE_0_DATA2_VNN -- debug header NC */ + PAD_NC(GPIO_12, DN_20K), /* TRACE_0_DATA3_VNN -- debug header NC */ + PAD_NC(GPIO_13, DN_20K), /* TRACE_0_DATA4_VNN -- debug header NC */ + PAD_NC(GPIO_14, DN_20K), /* TRACE_0_DATA5_VNN -- debug header NC */ + PAD_NC(GPIO_15, DN_20K), /* TRACE_0_DATA6_VNN -- debug header NC */ + PAD_NC(GPIO_16, DN_20K), /* TRACE_0_DATA7_VNN -- debug header NC */ + PAD_NC(GPIO_17, UP_20K), /* DBG_PTI_CLK_1 -- debug header NC */ + PAD_NC(GPIO_18, UP_20K), /* DBG_PTI_DATA_8 -- debug header NC */ + PAD_NC(GPIO_19, UP_20K), /* DBG_PTI_DATA_9 -- debug header NC */ + PAD_NC(GPIO_20, UP_20K), /* DBG_PTI_DATA_10 -- debug header NC */ PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */ PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */ PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_24, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA6_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_25, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_1_DATA7_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_26, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_CLK_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_27, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA0_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_28, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA1_VNN 0*/ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_29, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA2_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_30, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA3_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_31, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA4_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_32, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA5_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_33, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA6_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_34, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_2_DATA7_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_35, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_CLK_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA0_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA1_VNN */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, DN_20K, DEEP, NF5, HIZCRx0, DISPUPD), /* TRACE_3_DATA2_VNN */ + PAD_NC(GPIO_24,UP_20K), /* TRACE_1_DATA6_VNN -- debug header NC */ + PAD_NC(GPIO_25,UP_20K), /* TRACE_1_DATA7_VNN -- debug header NC */ + PAD_NC(GPIO_26, DN_20K), /* TRACE_2_CLK_VNN -- debug header NC */ + PAD_NC(GPIO_27, DN_20K), /* TRACE_2_DATA0_VNN -- debug header NC */ + PAD_NC(GPIO_28, DN_20K), /* TRACE_2_DATA1_VNN 0-- debug header NC */ + PAD_NC(GPIO_29, DN_20K), /* TRACE_2_DATA2_VNN -- debug header NC */ + PAD_NC(GPIO_30, DN_20K), /* TRACE_2_DATA3_VNN -- debug header NC */ + PAD_NC(GPIO_31, DN_20K), /* TRACE_2_DATA4_VNN -- debug header NC */ + PAD_NC(GPIO_32, DN_20K), /* TRACE_2_DATA5_VNN -- debug header NC */ + PAD_NC(GPIO_33, DN_20K), /* TRACE_2_DATA6_VNN -- debug header NC */ + PAD_NC(GPIO_34, DN_20K), /* TRACE_2_DATA7_VNN -- debug header NC */ + PAD_NC(GPIO_35, UP_20K), /* TRACE_3_CLK_VNN -- debug header NC */ + PAD_NC(GPIO_36, UP_20K), /* TRACE_3_DATA0_VNN -- debug header NC */ + PAD_NC(GPIO_37, UP_20K), /* TRACE_3_DATA1_VNN -- debug header NC */ + PAD_NC(GPIO_38, UP_20K), /* TRACE_3_DATA2_VNN -- debug header NC */ PAD_NC(GPIO_39, UP_20K), /* TRACE_3_DATA3_VNN -- unused */ PAD_NC(GPIO_40, UP_20K), /* TRACE_3_DATA4_VNN -- unused */ PAD_NC(GPIO_41, DN_20K), /* TRACE_3_DATA5_VNN -- unused */ PAD_NC(GPIO_42, DN_20K), /* GP_INTD_DSI_TE1 -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* GP_INTD_DSI_TE2 */ + PAD_NC(GPIO_43, DN_20K), /* GP_INTD_DSI_TE2 -- debug header NC */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC0_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC1_B */ PAD_NC(GPIO_46, DN_20K), /* DSI_I2C_SDA -- unused */ @@ -83,12 +83,12 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SCL */ PAD_NC(GPIO_54, UP_20K), /* LPSS_I2C2_SDA -- unused */ PAD_NC(GPIO_55, UP_20K), /* LPSS_I2C2_SCL -- unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C3_SDA */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C2_SCL */ - PAD_NC(GPIO_58, UP_20K), /* LPSS_I2C4_SDA - unused */ - PAD_NC(GPIO_59, UP_20K), /* LPSS_I2C4_SCL - unused */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ + PAD_NC(GPIO_56, UP_20K), /* LPSS_I2C3_SDA -- debug header NC */ + PAD_NC(GPIO_57, UP_20K), /* LPSS_I2C2_SCL -- debug header NC */ + PAD_NC(GPIO_58, UP_20K), /* LPSS_I2C4_SDA -- unused */ + PAD_NC(GPIO_59, UP_20K), /* LPSS_I2C4_SCL -- unused */ + PAD_NC(GPIO_60, UP_20K), /* LPSS_UART0_RXD -- debug header NC */ + PAD_NC(GPIO_61, UP_20K), /* LPSS_UART0_TXD -- debug header NC */ PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */ PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ @@ -118,7 +118,7 @@ /* LPSS */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_79, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* H1_SLAVE_SPI_CLK_R */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_80, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* H1_SLAVE_SPI_CS_L_R */ - PAD_CFG_GPIO_HI_Z(GPIO_81, UP_20K, DEEP, HIZCRx0, DISPUPD), /* GPIO_81_DEBUG (Boot halt) -- MIPI60 DEBUG */ + PAD_NC(GPIO_81, DN_20K), /* GPIO_81_DEBUG -- debug header NC */ PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */ PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ PAD_NC(GPIO_84, DN_20K), /* LPSS_SPI_2_CLK - unused */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3ffdbf6ad9b1682deaada91b5c225b4c8dd035b Gerrit-Change-Number: 29780 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variants/nami: Enable g2touch touchscreen device
by Furquan Shaikh (Code Review) 21 Nov '18

21 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29768 ) Change subject: mb/google/poppy/variants/nami: Enable g2touch touchscreen device ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29768/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nami/devicetree.cb: https://review.coreboot.org/#/c/29768/1/src/mainboard/google/poppy/variants… PS1, Line 350: _ I don't think using '_' is valid. HID needs to be either uppercase letter (A-Z) or numeral (0-9). -- To view, visit https://review.coreboot.org/c/coreboot/+/29768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26e16b7e118121b3dd9a88c76d04898b97753df0 Gerrit-Change-Number: 29768 Gerrit-PatchSet: 1 Gerrit-Owner: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Crystal Lin <crystal_lin(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 18:49:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/fizz/variants/karma: Enable touchscreen wakeup
by Furquan Shaikh (Code Review) 21 Nov '18

21 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29769 ) Change subject: mb/google/fizz/variants/karma: Enable touchscreen wakeup ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29769/1/src/mainboard/google/fizz/variants/… File src/mainboard/google/fizz/variants/karma/gpio.c: https://review.coreboot.org/#/c/29769/1/src/mainboard/google/fizz/variants/… PS1, Line 54: PAD_CFG_GPO(GPP_B4, 1, DEEP), /* PCH_TS_EN */ I haven't looked at the schematics or the part data sheet. How does this enable work? Does it need to be set always or just before entering suspend? Does it need to be disabled when entering deeper states like S5? You can email me the datasheet if you want. -- To view, visit https://review.coreboot.org/c/coreboot/+/29769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0c9493dec367c7813047c7994cc83537aaef141 Gerrit-Change-Number: 29769 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 18:31:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 21 Nov '18

21 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 20: (2 comments) https://review.coreboot.org/#/c/29563/20/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/20/src/include/memlayout.h@168 PS20, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/20/src/include/memlayout.h@168 PS20, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 20 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 18:29:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2018