coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S
by Huang Jin (Code Review) 21 Nov '18

21 Nov '18

Huang Jin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29687 ) Change subject: drivers/intel/fsp1_1/cache_as_ram.inc: Dont include soc/car_setup.S ...................................................................... Patch Set 1: Code-Review+2 Thanks for cleaning it up. -- To view, visit https://review.coreboot.org/c/coreboot/+/29687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61 Gerrit-Change-Number: 29687 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 14:19:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: intelblocks/cpu: Add function to enable maximum efficiency
by Nico Huber (Code Review) 21 Nov '18

21 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29771 ) Change subject: intelblocks/cpu: Add function to enable maximum efficiency ...................................................................... Patch Set 1: Just learned, the BIOS Spec calls it maximum efficiency *boot* if the APs are clocked low but the BSP high. So to make this less confusing, it's probably better to call it what it does: "set the minimum clock ratio". -- To view, visit https://review.coreboot.org/c/coreboot/+/29771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Gerrit-Change-Number: 29771 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 21 Nov 2018 14:07:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: siemens/mc_apl4: Set CPU clock to maximum efficiency
by Werner Zeh (Code Review) 21 Nov '18

21 Nov '18

Hello Mario Scheithauer, Uwe Pöche, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29773 to look at the new patch set (#3). Change subject: siemens/mc_apl4: Set CPU clock to maximum efficiency ...................................................................... siemens/mc_apl4: Set CPU clock to maximum efficiency The power budget for this mainboard is very limited while the performance demand is low. Set the CPU clock to the lowest value to enable maximum efficiency and thus lowest power dissipation. Change-Id: I23c7c5393deb676b94f2b0ac25e21a7a44cd8cb3 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29773/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23c7c5393deb676b94f2b0ac25e21a7a44cd8cb3 Gerrit-Change-Number: 29773 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Pöche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/apollolake: Add Kconfig switch to enable max efficiency clock
by Werner Zeh (Code Review) 21 Nov '18

21 Nov '18

Hello Mario Scheithauer, Huang Jin, build bot (Jenkins), Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29772 to look at the new patch set (#3). Change subject: soc/intel/apollolake: Add Kconfig switch to enable max efficiency clock ...................................................................... soc/intel/apollolake: Add Kconfig switch to enable max efficiency clock Add a Kconfig switch to be able to set the CPU clock to maximum efficiency mode. If enabled the CPU will be clocked with the lowest possible frequency while consuming as little power as possible. Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/cpu.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29772/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/29772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073 Gerrit-Change-Number: 29772 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: intelblocks/cpu: Add function to enable maximum efficiency
by Werner Zeh (Code Review) 21 Nov '18

21 Nov '18

Hello Mario Scheithauer, Huang Jin, build bot (Jenkins), Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29771 to look at the new patch set (#2). Change subject: intelblocks/cpu: Add function to enable maximum efficiency ...................................................................... intelblocks/cpu: Add function to enable maximum efficiency Provide a library function to set the CPU frequency to maximum efficiency value. This will result in the lowest possible CPU clock with the lowest possible power consumption. This can be useful in mobile devices where the power dissipation is limited. This setting can be overruled by the OS if it has an p-state driver which can adjust the clock to it's need. Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/29771/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Gerrit-Change-Number: 29771 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: intelblocks/cpu: Add function to enable maximum efficiency
by Werner Zeh (Code Review) 21 Nov '18

21 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29771 ) Change subject: intelblocks/cpu: Add function to enable maximum efficiency ...................................................................... Patch Set 1: > Patch Set 1: > > That's annoying, but we'll have to live with it :-/ > > This only applies until the OS p-state driver takes over, correct? If > so, please mention that in the commit message(s). Yes, if there is a p-state driver in OS it will overrule this setting. I will add it to the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/29771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Gerrit-Change-Number: 29771 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 21 Nov 2018 14:05:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: intelblocks/cpu: Add function to enable maximum efficiency
by Nico Huber (Code Review) 21 Nov '18

21 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29771 ) Change subject: intelblocks/cpu: Add function to enable maximum efficiency ...................................................................... Patch Set 1: That's annoying, but we'll have to live with it :-/ This only applies until the OS p-state driver takes over, correct? If so, please mention that in the commit message(s). -- To view, visit https://review.coreboot.org/c/coreboot/+/29771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Gerrit-Change-Number: 29771 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 21 Nov 2018 13:54:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: intelblocks/cpu: Add function to enable maximum efficiency
by Werner Zeh (Code Review) 21 Nov '18

21 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29771 ) Change subject: intelblocks/cpu: Add function to enable maximum efficiency ...................................................................... Patch Set 1: > Patch Set 1: > > Does Intel call it "maximum efficiency" in their documentation? What > you describe would lower power not energy, which confuses me. Efficient > should be to save energy, i.e. the best performance per power. If you have a look at the MSR description (the big Intel software developer manual), you will find the following text for the bits in question: Maximum Efficiency Ratio (R/O) The is the minimum ratio (maximum efficiency) that the processor can operates, in units of 100MHz. This is the reason for the naming. -- To view, visit https://review.coreboot.org/c/coreboot/+/29771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549 Gerrit-Change-Number: 29771 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 21 Nov 2018 13:52:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: fix bug of sifive-gpt.py
by Jonathan Neuschäfer (Code Review) 21 Nov '18

21 Nov '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29767 ) Change subject: riscv: fix bug of sifive-gpt.py ...................................................................... Patch Set 3: Code-Review+2 Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/29767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib025197fc96f32823e687a89de0cee51c952b031 Gerrit-Change-Number: 29767 Gerrit-PatchSet: 3 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 13:45:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/intel/icelake_rvp: Add ICL U and Y RVP DIMM configuration
by Subrata Banik (Code Review) 21 Nov '18

21 Nov '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29770 ) Change subject: mb/intel/icelake_rvp: Add ICL U and Y RVP DIMM configuration ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7 Gerrit-Change-Number: 29770 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 13:38:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2018