coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: mb/google/dragonegg: Add initial mainboard code support
by Patrick Rudolph (Code Review) 21 Nov '18

21 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29749 ) Change subject: mb/google/dragonegg: Add initial mainboard code support ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/29749/7//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29749/7//COMMIT_MSG@9 PS7, Line 9: This patch includes support for both ICL ES0 and ES1 samples. Missing parts: What was tested ? What is the test result ? Are there open TODOs ? Which BLOBs are necessary to build it ? How to optain those BLOBs ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Gerrit-Change-Number: 29749 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 09:46:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell/include/soc/irq.h: Change PIRQ_PIC_IRQDISABLE ...
by Frans Hendriks (Code Review) 21 Nov '18

21 Nov '18

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29393 ) Change subject: src/soc/intel/braswell/include/soc/irq.h: Change PIRQ_PIC_IRQDISABLE value ...................................................................... Patch Set 4: (1 comment) Update comment https://review.coreboot.org/#/c/29393/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29393/3//COMMIT_MSG@7 PS3, Line 7: src/soc/intel/braswell/include/soc/irq.h: Change PIRQ_PIC_IRQDISABLE value > That's not what's done in the commit. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514 Gerrit-Change-Number: 29393 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 09:45:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell/include/soc/irq.h: Change PIRQ_PIC_IRQDISABLE ...
by Frans Hendriks (Code Review) 21 Nov '18

21 Nov '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29393 to look at the new patch set (#4). Change subject: src/soc/intel/braswell/include/soc/irq.h: Change PIRQ_PIC_IRQDISABLE value ...................................................................... src/soc/intel/braswell/include/soc/irq.h: Change PIRQ_PIC_IRQDISABLE value Using 0 for PIRQ_PIC_IRQDISABLE might conflict with using IRQ0 as PIRQ. Change PIRQ_PIC_IRQDISABLE value to 0x80, so value 0 is reserved for IRQ0. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/include/soc/irq.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29393/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514 Gerrit-Change-Number: 29393 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: riscv: fix bug of sifive-gpt.py
by Xiang Wang (Code Review) 21 Nov '18

21 Nov '18

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29767 ) Change subject: riscv: fix bug of sifive-gpt.py ...................................................................... Patch Set 2: > (1 comment) The struct.park format character '<' means little endian. This is what I found when comparing coreboot.rom and hifive-unleashed-a00-1.0-2018-03-20.gpt. -- To view, visit https://review.coreboot.org/c/coreboot/+/29767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib025197fc96f32823e687a89de0cee51c952b031 Gerrit-Change-Number: 29767 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 09:37:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/dragonegg: Add initial mainboard code support
by Patrick Rudolph (Code Review) 21 Nov '18

21 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29749 ) Change subject: mb/google/dragonegg: Add initial mainboard code support ...................................................................... Patch Set 7: Code-Review-1 Please add Documentation for that board. For example: How to flash, required BLOBs, pictures if possible, everything that is useful for coreboot development. -- To view, visit https://review.coreboot.org/c/coreboot/+/29749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Gerrit-Change-Number: 29749 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 09:31:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: fix bug of sifive-gpt.py
by Patrick Rudolph (Code Review) 21 Nov '18

21 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29767 ) Change subject: riscv: fix bug of sifive-gpt.py ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29767/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29767/2//COMMIT_MSG@9 PS2, Line 9: The GPT version must be "00 00 01 00" and the small end should be did you mean Little-Endian here ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib025197fc96f32823e687a89de0cee51c952b031 Gerrit-Change-Number: 29767 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 09:29:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell/include/soc/irq.h: Set bit 7 of PIRQ register ...
by Patrick Rudolph (Code Review) 21 Nov '18

21 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29393 ) Change subject: src/soc/intel/braswell/include/soc/irq.h: Set bit 7 of PIRQ register to disable ...................................................................... Patch Set 3: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/29393/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29393/3//COMMIT_MSG@7 PS3, Line 7: src/soc/intel/braswell/include/soc/irq.h: Set bit 7 of PIRQ register to disable That's not what's done in the commit. Rephrase to "fix MACRO ..." ? Same below, you don't touch any register. -- To view, visit https://review.coreboot.org/c/coreboot/+/29393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514 Gerrit-Change-Number: 29393 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 09:20:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/drivers/intel/fsp1_1/raminit.c: Make check FSP HOBs independent o...
by Patrick Rudolph (Code Review) 21 Nov '18

21 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29371 ) Change subject: src/drivers/intel/fsp1_1/raminit.c: Make check FSP HOBs independent of CONFIG_DISPLAY_HOBS ...................................................................... Patch Set 2: Code-Review+1 Please add an additonal defconfig to the configs folder, to make sure that DISPLAY_HOBS is actually build tested. -- To view, visit https://review.coreboot.org/c/coreboot/+/29371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d Gerrit-Change-Number: 29371 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 09:17:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]x86|mb/emulation/qemu-q35: 64bit ramstage support
by build bot (Jenkins) (Code Review) 21 Nov '18

21 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29667 ) Change subject: [WIP]x86|mb/emulation/qemu-q35: 64bit ramstage support ...................................................................... Patch Set 5: (27 comments) https://review.coreboot.org/#/c/29667/5/src/arch/x86/boot.c File src/arch/x86/boot.c: https://review.coreboot.org/#/c/29667/5/src/arch/x86/boot.c@36 PS5, Line 36: printk(BIOS_DEBUG, "Jumping to %p\n", (void*)prog_entry(prog)); "(foo*)" should be "(foo *)" https://review.coreboot.org/#/c/29667/5/src/arch/x86/boot.c@38 PS5, Line 38: if (ENV_RAMSTAGE && IS_ENABLED(CONFIG_ARCH_RAMSTAGE_X86_64) && IS_ENABLED(CONFIG_ARCH_PAYLOAD_X86_32)) line over 80 characters https://review.coreboot.org/#/c/29667/5/src/arch/x86/exception.c File src/arch/x86/exception.c: https://review.coreboot.org/#/c/29667/5/src/arch/x86/exception.c@513 PS5, Line 513: for (int i = 0; i < 16; i++) suspect code indent for conditional statements (8, 8) https://review.coreboot.org/#/c/29667/5/src/arch/x86/include/arch/mmu.h File src/arch/x86/include/arch/mmu.h: https://review.coreboot.org/#/c/29667/5/src/arch/x86/include/arch/mmu.h@78 PS5, Line 78: #define L0_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L0_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/5/src/arch/x86/include/arch/mmu.h@79 PS5, Line 79: #define L1_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/5/src/arch/x86/include/arch/mmu.h@80 PS5, Line 80: #define L2_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/5/src/arch/x86/include/arch/mmu.h@81 PS5, Line 81: #define L3_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/5/src/arch/x86/include/arch/registers… File src/arch/x86/include/arch/registers.h: https://review.coreboot.org/#/c/29667/5/src/arch/x86/include/arch/registers… PS5, Line 23: #define DOWNTO8(A) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29667/5/src/arch/x86/include/arch/registers… PS5, Line 41: #define DOWNTO16(A) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c File src/arch/x86/mmu.c: https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@214 PS5, Line 214: if ((size >= L1_XLAT_SIZE) && suspect code indent for conditional statements (8, 24) https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@274 PS5, Line 274: switch ((pte[index] & AVAIL_MASK) >> AVAIL_SHIFT) { switch and case should be at the same indent https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@276 PS5, Line 276: printk(BIOS_DEBUG, "INVAL ");break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@278 PS5, Line 278: printk(BIOS_DEBUG, "TABLE @ %llx\n", pte[index] & XLAT_ADDR_MASK);break; line over 80 characters https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@278 PS5, Line 278: printk(BIOS_DEBUG, "TABLE @ %llx\n", pte[index] & XLAT_ADDR_MASK);break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@280 PS5, Line 280: printk(BIOS_DEBUG, "PAGE %llx, %llx %llx\n", pte[index] & ((XLAT_ADDR_MASK<<1)), line over 80 characters https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@281 PS5, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; line over 80 characters https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@281 PS5, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; need consistent spacing around '-' (ctx:WxV) https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@281 PS5, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@281 PS5, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@284 PS5, Line 284: printk(BIOS_DEBUG, "BLOCK %llx, %llx %llx\n", pte[index] & ((XLAT_ADDR_MASK<<1)), line over 80 characters https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@285 PS5, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; line over 80 characters https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@285 PS5, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; need consistent spacing around '-' (ctx:WxV) https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@285 PS5, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@285 PS5, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@335 PS5, Line 335: * The page tables generated are ment for long mode and do not work in 'ment' may be misspelled - perhaps 'meant'? https://review.coreboot.org/#/c/29667/5/src/arch/x86/mmu.c@352 PS5, Line 352: next_free_table = cbmem_add(CBMEM_ID_TTB, CONFIG_TTB_SIZE_KB * 1024); line over 80 characters https://review.coreboot.org/#/c/29667/5/src/include/device/pci.h File src/include/device/pci.h: https://review.coreboot.org/#/c/29667/5/src/include/device/pci.h@59 PS5, Line 59: } __attribute__(( aligned(sizeof(void *) * 4))); space prohibited after that open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 21 Nov 2018 08:38:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/dragonegg: Enable trackpad
by Aamir Bohra (Code Review) 21 Nov '18

21 Nov '18

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29752 ) Change subject: mb/google/dragonegg: Enable trackpad ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86d6b7815147d558065611604363bb607119c154 Gerrit-Change-Number: 29752 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Nov 2018 08:24:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2018