Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29670 )
Change subject: util/board_status: run dmesg with sudo
......................................................................
util/board_status: run dmesg with sudo
Newer kernels only allow root to access the kernel log buffer.
In another case (cbmem) we use sudo to get past that, so we can
expect sudo to be available here, too.
Change-Id: I654422992e5ba1e98a786f65d50289efbcd46602
Signed-off-by: Patrick Georgi <patrick(a)georgi.software>
Reviewed-on: https://review.coreboot.org/29670
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M util/board_status/board_status.sh
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh
index 4acbb6c..bba3d1f 100755
--- a/util/board_status/board_status.sh
+++ b/util/board_status/board_status.sh
@@ -381,7 +381,7 @@
cmd_nonfatal $REMOTE "$cbmem_cmd -t" "${tmpdir}/${results}/coreboot_timestamps.txt"
echo "Getting remote dmesg"
- cmd $REMOTE dmesg "${tmpdir}/${results}/kernel_log.txt"
+ cmd $REMOTE sudo dmesg "${tmpdir}/${results}/kernel_log.txt"
else
echo "Verifying that CBMEM is available"
if [ $(id -u) -ne 0 ]; then
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I654422992e5ba1e98a786f65d50289efbcd46602
Gerrit-Change-Number: 29670
Gerrit-PatchSet: 2
Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/29685
Change subject: Documentation: Add W530 / T530
......................................................................
Documentation: Add W530 / T530
Change-Id: Ib253308737f8c7a497c6ca13eab88220b1ac27ad
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M Documentation/mainboard/index.md
A Documentation/mainboard/lenovo/w530-1.jpg
A Documentation/mainboard/lenovo/w530-2.jpg
A Documentation/mainboard/lenovo/w530.md
4 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/29685/1
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 5df4885..15c2ede 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -52,6 +52,8 @@
### Ivy Bridge series
- [T430](lenovo/t430.md)
+- [T530](lenovo/w530.md)
+- [W530](lenovo/w530.md)
- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md)
## SiFive
diff --git a/Documentation/mainboard/lenovo/w530-1.jpg b/Documentation/mainboard/lenovo/w530-1.jpg
new file mode 100644
index 0000000..32827a0
--- /dev/null
+++ b/Documentation/mainboard/lenovo/w530-1.jpg
Binary files differ
diff --git a/Documentation/mainboard/lenovo/w530-2.jpg b/Documentation/mainboard/lenovo/w530-2.jpg
new file mode 100644
index 0000000..dd129b9
--- /dev/null
+++ b/Documentation/mainboard/lenovo/w530-2.jpg
Binary files differ
diff --git a/Documentation/mainboard/lenovo/w530.md b/Documentation/mainboard/lenovo/w530.md
new file mode 100644
index 0000000..f91d9ce
--- /dev/null
+++ b/Documentation/mainboard/lenovo/w530.md
@@ -0,0 +1,27 @@
+# Lenovo W530 / T530
+
+## Flashing instructions
+You have to remove the keyboard and the palm rest to access one of the
+flash ICs. The second flash ICs is behind the case frame, but can be
+flashed by using a simple trick. Connect every pin of the first flash
+IC, but tie /CS to Vcc. Connect /CS of the second flash IC to the
+programmer.
+As all lines except /CS are shared between the flash ICs you can access
+both with an external programmer.
+
+For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and
+```eval_rst
+:doc:`../../flash_tutorial/ext_power`
+```
+
+### After removing the keyboard and palm rest
+![][w530-1]
+
+[w530-1]: w530-1.jpg
+
+### Closeup view of the flash ICs
+![][w530-2]
+
+[w530-2]: w530-2.jpg
+
+[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib253308737f8c7a497c6ca13eab88220b1ac27ad
Gerrit-Change-Number: 29685
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29668
to look at the new patch set (#5).
Change subject: nb/intel/sandybridge/acpi: Add RMRR entry for iGPU
......................................................................
nb/intel/sandybridge/acpi: Add RMRR entry for iGPU
The iGPU always needs access to its stolen memory. For proper IOMMU
support, we have to make the OS aware of that.
Directly below TOLUD lies the data stolen memory (BDSM) followed by
the GTT stolen memory (BGSM), the iGPU needs access to both.
Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M 3rdparty/chromeec
M src/northbridge/intel/sandybridge/acpi.c
2 files changed, 27 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29668/5
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d
Gerrit-Change-Number: 29668
Gerrit-PatchSet: 5
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29666 )
Change subject: util: Fix shebang for python2 scripts
......................................................................
util: Fix shebang for python2 scripts
Python 3 is the default Python interpreter on most modern systems.
Python 2 scripts must specify they should be run with Python 2 in their
shebang. Solves issue raised in CB:28953.
Change-Id: I9ace4afd668539c05e7ace30e255af50c7a069c2
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/29666
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
---
M util/cavium/devicetree_convert.py
M util/ipqheader/createxbl.py
M util/ipqheader/mbn_tools.py
M util/lint/checkpatch_json.py
4 files changed, 4 insertions(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Georgi: Looks good to me, approved
diff --git a/util/cavium/devicetree_convert.py b/util/cavium/devicetree_convert.py
old mode 100644
new mode 100755
index 656fdf6..827e5a7
--- a/util/cavium/devicetree_convert.py
+++ b/util/cavium/devicetree_convert.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python
+#!/usr/bin/env python2
# devicetree_convert Tool to convert a DTB to a static C file
# Copyright (C) 2018 Facebook Inc.
diff --git a/util/ipqheader/createxbl.py b/util/ipqheader/createxbl.py
index 7f2d987..1efd8ba 100755
--- a/util/ipqheader/createxbl.py
+++ b/util/ipqheader/createxbl.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python
+#!/usr/bin/env python2
#============================================================================
#
#/** @file createxbl.py
diff --git a/util/ipqheader/mbn_tools.py b/util/ipqheader/mbn_tools.py
index 8a17563..c66afda 100755
--- a/util/ipqheader/mbn_tools.py
+++ b/util/ipqheader/mbn_tools.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python
+#!/usr/bin/env python2
#===============================================================================
#
# MBN TOOLS
diff --git a/util/lint/checkpatch_json.py b/util/lint/checkpatch_json.py
index 74ad96a..c8dd36d 100755
--- a/util/lint/checkpatch_json.py
+++ b/util/lint/checkpatch_json.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python
+#!/usr/bin/env python2
# Copyright (C) 2018 Intel Corporation.
# written by Naresh G Solanki<naresh.solanki(a)intel.com> and
# Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
--
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Gerrit-Change-Id: I9ace4afd668539c05e7ace30e255af50c7a069c2
Gerrit-Change-Number: 29666
Gerrit-PatchSet: 2
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/29669 )
Change subject: cpu/intel/sandybridge: Add `hyper_threading` option
......................................................................
Patch Set 1:
I've tested this on a P8H61-M LX with an i3-2100. The sibling CPUs are
indeed disabled and `/sys/devices/system/cpu/smt/control` reports that
SMT is "notsupported".
However, coreboot still tries to initialise the sibling CPUs during
`intel_cores_init()`. The attempts fail but it increases boot time by
one second per disabled core.
Also, the ACPI Processor objects are not generated correctly when SMT is
disabled. With the current cpu init, `generate_cpu_entries()` reports 0
CPUs with 4 cores, generating nothing, but Linux seems to run fine. If
the parallel MP init patch for model_206ax is applied, it does generate
the ACPI objects, but includes the disabled cores. Linux notes "acpi
LNXCPU:02: BIOS reported wrong ACPI id 1 for the processor", "smpboot:
do_boot_cpu failed(-1) to wakeup CPU#2", and runs extremely slowly.
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993
Gerrit-Change-Number: 29669
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi>
Gerrit-Comment-Date: Sun, 18 Nov 2018 04:48:11 +0000
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