coreboot-gerrit November 2018

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Change in coreboot[master]: soc/intel/.../Kconfig: Move GPIO debug option into debug menu
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29678 Change subject: soc/intel/.../Kconfig: Move GPIO debug option into debug menu ...................................................................... soc/intel/.../Kconfig: Move GPIO debug option into debug menu Rename DEBUG_SOC_COMMON_BLOCK_GPIO to DEBUG_GPIO and move it into the Debugging menu. Change-Id: I737d0ee7fb5423b6d16d611a144d43fd3f168a2c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/Kconfig M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/denverton_ns/Kconfig 4 files changed, 11 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/29678/1 diff --git a/src/Kconfig b/src/Kconfig index 0b97125..ce584f5 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -693,6 +693,13 @@ help If enabled, coreboot will call hlt() on a BUG() or failed ASSERT(). +config HAVE_DEBUG_GPIO + bool + +config DEBUG_GPIO + bool "Output verbose GPIO debug messages" + depends on HAVE_DEBUG_GPIO + config DEBUG_CBFS bool "Output verbose CBFS debug messages" default n diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index 66cc182..bdbc323 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -1,15 +1,9 @@ config SOC_INTEL_COMMON_BLOCK_GPIO bool + select HAVE_DEBUG_GPIO help Intel Processor common GPIO support -config DEBUG_SOC_COMMON_BLOCK_GPIO - depends on SOC_INTEL_COMMON_BLOCK_GPIO - bool "Output verbose GPIO debug messages" - default n - help - This option enables GPIO debug messages - # Use to program Interrupt Polarity Control (IPCx) register # Each bit represents IRQx Active High Polarity Disable configuration: # when set to 1, the interrupt polarity associated with IRQx is inverted diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index bd12477..9b6ca7e 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -265,7 +265,7 @@ soc_pad_conf &= mask[i]; soc_pad_conf |= pad_conf & ~mask[i]; - if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO)) + if (IS_ENABLED(CONFIG_DEBUG_GPIO)) printk(BIOS_DEBUG, "gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x" " : 0x%08x]\n", @@ -533,7 +533,7 @@ MISCCFG_GPE0_DW1_MASK | MISCCFG_GPE0_DW0_MASK); - if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO)) + if (IS_ENABLED(CONFIG_DEBUG_GPIO)) printk(BIOS_DEBUG, "misccfg_mask:%x misccfg_value:%x\n", misccfg_mask, misccfg_value); comm = soc_gpio_get_community(&gpio_communities); diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index d9490cb..5b704b9 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -29,6 +29,7 @@ select BOOTBLOCK_CONSOLE select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES + select DEBUG_GPIO select POSTCAR_CONSOLE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET @@ -50,7 +51,6 @@ # select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO - select DEBUG_SOC_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER -- To view, visit https://review.coreboot.org/29678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I737d0ee7fb5423b6d16d611a144d43fd3f168a2c Gerrit-Change-Number: 29678 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: soc/intel/common/*/Kconfig: Remove redundant comments
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29677 Change subject: soc/intel/common/*/Kconfig: Remove redundant comments ...................................................................... soc/intel/common/*/Kconfig: Remove redundant comments Change-Id: Ide9608e487793fa4a8b0e291ba168126e0484355 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/Kconfig M src/soc/intel/common/pch/Kconfig 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/29677/1 diff --git a/src/soc/intel/common/block/Kconfig b/src/soc/intel/common/block/Kconfig index e5375d2..80e5c66 100644 --- a/src/soc/intel/common/block/Kconfig +++ b/src/soc/intel/common/block/Kconfig @@ -5,7 +5,6 @@ if SOC_INTEL_COMMON_BLOCK -comment "Intel SoC Common IP Code" source "src/soc/intel/common/block/*/Kconfig" endif diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 2bf6d68..f4f3ad0 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -12,7 +12,6 @@ if SOC_INTEL_COMMON_PCH_BASE -comment "Intel SoC Common PCH Code" source "src/soc/intel/common/pch/*/Kconfig" config PCH_SPECIFIC_OPTIONS -- To view, visit https://review.coreboot.org/29677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ide9608e487793fa4a8b0e291ba168126e0484355 Gerrit-Change-Number: 29677 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: (console, drivers/uart)/Kconfig: Fix dependencies
by Nico Huber (Code Review) 17 Nov '18

17 Nov '18

Hello Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29572 to look at the new patch set (#3). Change subject: (console,drivers/uart)/Kconfig: Fix dependencies ...................................................................... (console,drivers/uart)/Kconfig: Fix dependencies The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART, because it's using its interface. The individual UART drivers select DRIVERS_UART, because they implement the interface and depend on the common UART code. Some guards had to be fixed (using CONSOLE_SERIAL now instead of DRIVERS_UART). Some other guards that were only about compilation of units were removed. We want to build test as much as possible, right? Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/console/Kconfig M src/cpu/allwinner/a10/Makefile.inc M src/cpu/ti/am335x/Makefile.inc M src/drivers/uart/Kconfig M src/mainboard/google/gru/bootblock.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_rialto/bootblock.c M src/soc/broadcom/cygnus/Makefile.inc M src/soc/imgtec/pistachio/Makefile.inc M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8183/Makefile.inc M src/soc/nvidia/tegra124/Makefile.inc M src/soc/nvidia/tegra210/Makefile.inc M src/soc/qualcomm/ipq40xx/Makefile.inc M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq806x/Makefile.inc M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/sdm845/Makefile.inc M src/soc/rockchip/rk3288/Makefile.inc M src/soc/rockchip/rk3399/Makefile.inc M src/soc/samsung/exynos5250/Makefile.inc 22 files changed, 58 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29572/3 -- To view, visit https://review.coreboot.org/29572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Gerrit-Change-Number: 29572 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: drivers/nvidia: Add PCI mapped option rom driver
by Marcello Sylvester Bauer (Code Review) 17 Nov '18

17 Nov '18

Marcello Sylvester Bauer has posted comments on this change. ( https://review.coreboot.org/29676 ) Change subject: drivers/nvidia: Add PCI mapped option rom driver ...................................................................... Patch Set 2: Code-Review+1 works on my Thinkpad W530 [Quadro K2000M] -- To view, visit https://review.coreboot.org/29676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idd85ed1fe9b5ffe4c9b7944d5360a2898dbb07f8 Gerrit-Change-Number: 29676 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Nov 2018 22:31:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/nvidia: Add PCI mapped option rom driver
by Patrick Rudolph (Code Review) 17 Nov '18

17 Nov '18

Patrick Rudolph has uploaded a new patch set (#2) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/29676 ) Change subject: drivers/nvidia: Add PCI mapped option rom driver ...................................................................... drivers/nvidia: Add PCI mapped option rom driver Map the Nvidia PCI ids for easy PCI option rom integration. Change-Id: Idd85ed1fe9b5ffe4c9b7944d5360a2898dbb07f8 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/pci_rom.c A src/drivers/nvidia/Kconfig A src/drivers/nvidia/Makefile.inc A src/drivers/nvidia/nvidia.c M src/include/device/pci_rom.h M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig 10 files changed, 50 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/29676/2 -- To view, visit https://review.coreboot.org/29676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idd85ed1fe9b5ffe4c9b7944d5360a2898dbb07f8 Gerrit-Change-Number: 29676 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: drivers/nvidia: Add PCI mapped option rom driver
by Patrick Rudolph (Code Review) 17 Nov '18

17 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/29676 Change subject: drivers/nvidia: Add PCI mapped option rom driver ...................................................................... drivers/nvidia: Add PCI mapped option rom driver Map the Nvidia PCI ids for easy PCI option rom integration. Change-Id: Idd85ed1fe9b5ffe4c9b7944d5360a2898dbb07f8 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/pci_rom.c A src/drivers/nvidia/Kconfig A src/drivers/nvidia/Makefile.inc A src/drivers/nvidia/nvidia.c M src/include/device/pci_rom.h M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig 10 files changed, 51 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/29676/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 65989d4..ecbe340 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -30,6 +30,7 @@ /* Rmodules don't like weak symbols. */ u32 __weak map_oprom_vendev(u32 vendev) { return vendev; } +u32 __weak map_oprom_vendev_nvidia(u32 vendev) { return vendev; } struct rom_header *pci_rom_probe(struct device *dev) { @@ -43,6 +44,7 @@ u32 mapped_vendev; mapped_vendev = map_oprom_vendev(vendev); + mapped_vendev = map_oprom_vendev_nvidia(mapped_vendev); if (!rom_header) { if (vendev != mapped_vendev) { diff --git a/src/drivers/nvidia/Kconfig b/src/drivers/nvidia/Kconfig new file mode 100644 index 0000000..7e49473 --- /dev/null +++ b/src/drivers/nvidia/Kconfig @@ -0,0 +1,4 @@ +config DRIVERS_NVIDIA + bool + help + Select this driver when using Nvidia graphics cards. diff --git a/src/drivers/nvidia/Makefile.inc b/src/drivers/nvidia/Makefile.inc new file mode 100644 index 0000000..59bb61b --- /dev/null +++ b/src/drivers/nvidia/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_NVIDIA) += nvidia.c diff --git a/src/drivers/nvidia/nvidia.c b/src/drivers/nvidia/nvidia.c new file mode 100644 index 0000000..f43a18e --- /dev/null +++ b/src/drivers/nvidia/nvidia.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Chromium OS Authors + * Copyright (C) 2018 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_rom.h> + +/** + * Some vga option roms are used for several chipsets but they only have one + * PCI ID in their header. If we encounter such an option rom, we need to do + * the mapping ourselves + */ +u32 map_oprom_vendev_nvidia(u32 vendev) +{ + u32 new_vendev = vendev; + + switch (vendev) { + case 0x10de0ffb: /* Nvidia Quadro K2000M */ + case 0x10de0ffc: /* Nvidia Quadro K1000M */ + new_vendev = 0x10de0ffc; /* Nvidia Quadro K1000M */ + break; + } + + return new_vendev; +} + diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index a4aa52a..f84e888 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -46,5 +46,5 @@ void pci_rom_ssdt(struct device *device); u32 map_oprom_vendev(u32 vendev); - +u32 map_oprom_vendev_nvidia(u32 vendev); #endif diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 41c0d37..52e1d9f 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -25,6 +25,7 @@ select GFX_GMA_INTERNAL_IS_LVDS select DRIVERS_LENOVO_HYBRID_GRAPHICS select INTEL_GMA_HAVE_VBT + select DRIVERS_NVIDIA # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 8eb241a..753032a 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -21,6 +21,7 @@ select MAINBOARD_HAS_TPM1 select DRIVERS_LENOVO_HYBRID_GRAPHICS select INTEL_GMA_HAVE_VBT + select DRIVERS_NVIDIA # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 242412f..57d0614 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -26,6 +26,8 @@ select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS select INTEL_GMA_HAVE_VBT + select DRIVERS_NVIDIA + config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 79455e2..80976db 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -20,6 +20,7 @@ select MAINBOARD_HAS_TPM1 select DRIVERS_LENOVO_HYBRID_GRAPHICS select INTEL_GMA_HAVE_VBT if BOARD_LENOVO_T520 + select DRIVERS_NVIDIA # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index d107504..e394fd0 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -22,6 +22,7 @@ select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS select INTEL_GMA_HAVE_VBT + select DRIVERS_NVIDIA # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE -- To view, visit https://review.coreboot.org/29676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idd85ed1fe9b5ffe4c9b7944d5360a2898dbb07f8 Gerrit-Change-Number: 29676 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: [WIP]x86|mb/emulation/qemu-q35: 64bit ramstage support
by build bot (Jenkins) (Code Review) 17 Nov '18

17 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29667 ) Change subject: [WIP]x86|mb/emulation/qemu-q35: 64bit ramstage support ...................................................................... Patch Set 3: (26 comments) https://review.coreboot.org/#/c/29667/3/src/arch/x86/boot.c File src/arch/x86/boot.c: https://review.coreboot.org/#/c/29667/3/src/arch/x86/boot.c@36 PS3, Line 36: printk(BIOS_DEBUG, "Jumping to %p\n", (void*)prog_entry(prog)); "(foo*)" should be "(foo *)" https://review.coreboot.org/#/c/29667/3/src/arch/x86/exception.c File src/arch/x86/exception.c: https://review.coreboot.org/#/c/29667/3/src/arch/x86/exception.c@513 PS3, Line 513: for (int i = 0; i < 16; i++) suspect code indent for conditional statements (8, 8) https://review.coreboot.org/#/c/29667/3/src/arch/x86/include/arch/mmu.h File src/arch/x86/include/arch/mmu.h: https://review.coreboot.org/#/c/29667/3/src/arch/x86/include/arch/mmu.h@78 PS3, Line 78: #define L0_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L0_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/3/src/arch/x86/include/arch/mmu.h@79 PS3, Line 79: #define L1_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L1_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/3/src/arch/x86/include/arch/mmu.h@80 PS3, Line 80: #define L2_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L2_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/3/src/arch/x86/include/arch/mmu.h@81 PS3, Line 81: #define L3_ADDR_MASK (((1ULL << BITS_RESOLVED_PER_LVL) - 1) << L3_ADDR_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29667/3/src/arch/x86/include/arch/registers… File src/arch/x86/include/arch/registers.h: https://review.coreboot.org/#/c/29667/3/src/arch/x86/include/arch/registers… PS3, Line 23: #define DOWNTO8(A) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29667/3/src/arch/x86/include/arch/registers… PS3, Line 41: #define DOWNTO16(A) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c File src/arch/x86/mmu.c: https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@214 PS3, Line 214: if ((size >= L1_XLAT_SIZE) && suspect code indent for conditional statements (8, 24) https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@274 PS3, Line 274: switch ((pte[index] & AVAIL_MASK) >> AVAIL_SHIFT) { switch and case should be at the same indent https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@276 PS3, Line 276: printk(BIOS_DEBUG, "INVAL ");break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@278 PS3, Line 278: printk(BIOS_DEBUG, "TABLE @ %llx\n", pte[index] & XLAT_ADDR_MASK);break; line over 80 characters https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@278 PS3, Line 278: printk(BIOS_DEBUG, "TABLE @ %llx\n", pte[index] & XLAT_ADDR_MASK);break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@280 PS3, Line 280: printk(BIOS_DEBUG, "PAGE %llx, %llx %llx\n", pte[index] & ((XLAT_ADDR_MASK<<1)), line over 80 characters https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@281 PS3, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; line over 80 characters https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@281 PS3, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; need consistent spacing around '-' (ctx:WxV) https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@281 PS3, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@281 PS3, Line 281: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@284 PS3, Line 284: printk(BIOS_DEBUG, "BLOCK %llx, %llx %llx\n", pte[index] & ((XLAT_ADDR_MASK<<1)), line over 80 characters https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@285 PS3, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; line over 80 characters https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@285 PS3, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; need consistent spacing around '-' (ctx:WxV) https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@285 PS3, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@285 PS3, Line 285: (pte[index] & ((XLAT_ADDR_MASK<<1))) + (1ULL << shift) -1,pte[index] & 0xfff);break; space required after that ';' (ctx:VxV) https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@340 PS3, Line 340: next_free_table = cbmem_add(CBMEM_ID_TTB, CONFIG_TTB_SIZE_KB * 1024); line over 80 characters https://review.coreboot.org/#/c/29667/3/src/arch/x86/mmu.c@390 PS3, Line 390: #define MSR_EFER 0xc0000080 /* extended feature register */ line over 80 characters https://review.coreboot.org/#/c/29667/3/src/mainboard/emulation/qemu-q35/ro… File src/mainboard/emulation/qemu-q35/romstage.c: https://review.coreboot.org/#/c/29667/3/src/mainboard/emulation/qemu-q35/ro… PS3, Line 43: mmu_config_range(0x100000000ULL, (uint64_t)qemu_get_high_memory_size() * 1024ULL, PAT_WB); line over 80 characters -- To view, visit https://review.coreboot.org/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Nov 2018 21:10:28 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/qemu-x86: Fix CPU driver
by Patrick Rudolph (Code Review) 17 Nov '18

17 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/29675 Change subject: cpu/qemu-x86: Fix CPU driver ...................................................................... cpu/qemu-x86: Fix CPU driver There's a typo in the cpu driver causing it to always use the weak implementation defined in the devicetree instead of the real implementation. Tested on qemu-q35, the CPU driver contains valid values. Change-Id: I4a6bb447bfdb3df6053c0df8be9d7c6aa8f689be Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/qemu-x86/qemu.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/29675/1 diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c index c005bf7..f250698 100644 --- a/src/cpu/qemu-x86/qemu.c +++ b/src/cpu/qemu-x86/qemu.c @@ -35,6 +35,6 @@ .id_table = cpu_table, }; -struct chip_operations cpu_x86_qemu_ops = { +struct chip_operations cpu_qemu_x86_ops = { CHIP_NAME("QEMU x86 CPU") }; -- To view, visit https://review.coreboot.org/29675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4a6bb447bfdb3df6053c0df8be9d7c6aa8f689be Gerrit-Change-Number: 29675 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: ec/google/wilco: Fix extended event handling
by Duncan Laurie (Code Review) 17 Nov '18

17 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29674 Change subject: ec/google/wilco: Fix extended event handling ...................................................................... ec/google/wilco: Fix extended event handling Extended events will be handled by the OS kernel driver, but that driver needs a method exposed by ACPI to read the event data from the EC and into a buffer. Tested by generating a hotkey event and reading the buffer from the Linux kernel driver with acpi_evaluate_object(). Change-Id: Ic8510e38d777a5dd31a5237867313efefeb2b48e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/acpi/ec_ram.asl M src/ec/google/wilco/acpi/event.asl 2 files changed, 20 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29674/1 diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index ffa0c9f..e2b6a93 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -67,7 +67,7 @@ Name (EVT2, Package () { 0x08, 0xff, RD }) /* Event 2 */ Name (E2BS, Package () { 0x08, 0x02, RD }) /* BSS */ Name (E2OR, Package () { 0x08, 0x04, RD }) /* Orientation */ -Name (E2QS, Package () { 0x08, 0x08, RD }) /* Quickset */ +Name (E2QS, Package () { 0x08, 0x08, RD }) /* QS Event */ Name (E2PN, Package () { 0x08, 0x20, RD }) /* Panel */ Name (E2DP, Package () { 0x08, 0x40, RD }) /* Display Port */ Name (E2VT, Package () { 0x08, 0x80, RD }) /* Video Throttle */ @@ -100,8 +100,8 @@ Name (BSDC, Package () { 0x29, 0xff, RD }) /* BSTATIC: Device Chemistry */ Name (BSBS, Package () { 0x2a, 0xff, RD }) /* BSTATIC: Battery String */ -Name (QSEC, Package () { 0x2b, 0xff, RD }) /* QuickSet Event Count */ -Name (QSEB, Package () { 0x2c, 0xff, RD }) /* QuickSet Event Byte */ +Name (QSEC, Package () { 0x2b, 0xff, RD }) /* QS Event Count */ +Name (QSEB, Package () { 0x2c, 0xff, RD }) /* QS Event Byte */ Name (ORST, Package () { 0x39, 0xff, RD }) /* Orientation State */ Name (OREV, Package () { 0x3a, 0xff, RD }) /* Orientation Events */ diff --git a/src/ec/google/wilco/acpi/event.asl b/src/ec/google/wilco/acpi/event.asl index b43086c..4d796b5 100644 --- a/src/ec/google/wilco/acpi/event.asl +++ b/src/ec/google/wilco/acpi/event.asl @@ -76,6 +76,11 @@ Method (ECQ2, 1, Serialized) { Printf ("EVT2: %o", Arg0) + + If (EBIT (E2QS, Arg0)) { + Printf ("QS EVENT") + Notify (^WLCO, 0x90) + } } /* Handle events in PmEv3 */ @@ -90,12 +95,6 @@ Printf ("EVT4: %o", Arg0) } -/* Handle QuickSet events */ -Method (ECQS, 1, Serialized) -{ - Printf ("QS EVENT %o", Arg0) -} - /* Process all events */ Method (_Q66, 0, Serialized) { @@ -118,9 +117,20 @@ If (Local0) { ECQ4 (Local0) } +} +/* Get Event Buffer */ +Method (QSET, 0, Serialized) +{ + /* Get count of event bytes */ Local0 = R (QSEC) + Name (QBUF, Buffer (Local0) {}) + + /* Fill QS event buffer with Local0 bytes */ For (Local1 = 0, Local1 < Local0, Local1++) { - ECQS (R (QSEB)) + QBUF[Local1] = R (QSEB) } + + Printf ("QS = %o", QBUF) + Return (QBUF) } -- To view, visit https://review.coreboot.org/29674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic8510e38d777a5dd31a5237867313efefeb2b48e Gerrit-Change-Number: 29674 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: ec/google/wilco: Enable WiFi radio
by Duncan Laurie (Code Review) 17 Nov '18

17 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29673 Change subject: ec/google/wilco: Enable WiFi radio ...................................................................... ec/google/wilco: Enable WiFi radio Add EC command to enable WiFi radio and send that command at startup. Tested to ensure WiFi is functional on a sarien board. Change-Id: Iac46895c7118567e1eb55ea33051a1662103b563 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/chip.c M src/ec/google/wilco/commands.c M src/ec/google/wilco/commands.h 3 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29673/1 diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 0cd0048..e1f468d 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -66,6 +66,9 @@ /* Unmute speakers */ wilco_ec_send(KB_HW_MUTE_CONTROL, AUDIO_UNMUTE_125MS); + + /* Enable WiFi radio */ + wilco_ec_radio_control(RADIO_WIFI, 1); } static void wilco_ec_resource(struct device *dev, int index, diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c index 1767a01..c42699d 100644 --- a/src/ec/google/wilco/commands.c +++ b/src/ec/google/wilco/commands.c @@ -149,3 +149,12 @@ KB_POWER_OFF, &reason, 1, NULL, 0) < 0) printk(BIOS_ERR, "%s: command failed\n", __func__); } + +int wilco_ec_radio_control(enum ec_radio radio, uint8_t state) +{ + uint8_t radio_control[3] = { 0, radio, state }; + + return wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_RADIO_CONTROL, + radio_control, ARRAY_SIZE(radio_control), + NULL, 0); +} diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 4a19030..0989b20 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -26,6 +26,8 @@ KB_POWER_STATUS = 0x05, /* Inform the EC aboout the reason host is turning off */ KB_POWER_OFF = 0x08, + /* Control wireless radios */ + KB_RADIO_CONTROL = 0x2b, /* Save PS/2 data before S3 suspend */ KB_SAVE = 0x2f, /* Restore PS/2 data after S3 resume */ @@ -61,6 +63,18 @@ AUDIO_UNMUTE_125MS, /* Unmute in 125ms */ }; +enum ec_radio { + RADIO_WIFI = 0x02, +}; + +/** + * wilco_ec_radio_control() - Control wireless radios. + * @ec_radio: Wireless radio type. + * @state: Turn radio on or off. + * Return: 0 if successful or negative error code on failure. + */ +int wilco_ec_radio_control(enum ec_radio radio, uint8_t state); + /* * EC Information */ -- To view, visit https://review.coreboot.org/29673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iac46895c7118567e1eb55ea33051a1662103b563 Gerrit-Change-Number: 29673 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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coreboot-gerrit November 2018