coreboot-gerrit November 2018

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Change in coreboot[master]: soc/intel/common/Kconfig: Remove unused SOC_INTEL_COMMON_SMI
by Elyes HAOUAS (Code Review) 13 Nov '18

13 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29621 Change subject: soc/intel/common/Kconfig: Remove unused SOC_INTEL_COMMON_SMI ...................................................................... soc/intel/common/Kconfig: Remove unused SOC_INTEL_COMMON_SMI Change-Id: Ic4ea1d681d2677880b155713c34152ac0861146b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/common/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/29621/1 diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 44d9f23..27d3f59 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -50,10 +50,6 @@ default "3rdparty/blobs/soc/intel/kabylake/mma-blobs" if SOC_INTEL_KABYLAKE default "3rdparty/blobs/soc/intel/skylake/mma-blobs" if SOC_INTEL_SKYLAKE -config SOC_INTEL_COMMON_SMI - bool - default n - config SOC_INTEL_COMMON_ACPI bool default n -- To view, visit https://review.coreboot.org/29621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic4ea1d681d2677880b155713c34152ac0861146b Gerrit-Change-Number: 29621 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: {soc, sb}/amd: Remove unused SOUTHBRIDGE_AMD_*_SKIP_ISA_DMA_INIT
by Elyes HAOUAS (Code Review) 13 Nov '18

13 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29620 Change subject: {soc,sb}/amd: Remove unused SOUTHBRIDGE_AMD_*_SKIP_ISA_DMA_INIT ...................................................................... {soc,sb}/amd: Remove unused SOUTHBRIDGE_AMD_*_SKIP_ISA_DMA_INIT Change-Id: Ic9bca9a56663926a153b93c298f69ba7d26f6e5e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/Kconfig M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/sb800/Kconfig 4 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/29620/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 4411984..6255cfc 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -147,10 +147,6 @@ hex default 0xc0000 -config SOUTHBRIDGE_AMD_STONEYRIDGE_SKIP_ISA_DMA_INIT - bool - default n - config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 4f769fb..65831b0 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -35,10 +35,6 @@ string default "southbridge/amd/agesa/hudson/bootblock.c" -config SOUTHBRIDGE_AMD_HUDSON_SKIP_ISA_DMA_INIT - bool - default n - config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 9d803be..a30dacd 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -38,10 +38,6 @@ string default "southbridge/amd/pi/hudson/bootblock.c" -config SOUTHBRIDGE_AMD_HUDSON_SKIP_ISA_DMA_INIT - bool - default n - config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig index d66469a..245a9f2 100644 --- a/src/southbridge/amd/sb800/Kconfig +++ b/src/southbridge/amd/sb800/Kconfig @@ -24,10 +24,6 @@ string default "southbridge/amd/sb800/bootblock.c" -config SOUTHBRIDGE_AMD_SB800_SKIP_ISA_DMA_INIT - bool - default n - config EHCI_BAR hex default 0xfef00000 -- To view, visit https://review.coreboot.org/29620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic9bca9a56663926a153b93c298f69ba7d26f6e5e Gerrit-Change-Number: 29620 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/intel/cougar_canyon2: Fix SMBIOS_ENCLOSURE_TYPE symbol
by Elyes HAOUAS (Code Review) 13 Nov '18

13 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29619 Change subject: mb/intel/cougar_canyon2: Fix SMBIOS_ENCLOSURE_TYPE symbol ...................................................................... mb/intel/cougar_canyon2: Fix SMBIOS_ENCLOSURE_TYPE symbol Change-Id: I9f4640ef040dc6a1d39ecb8b3378266e4dd5cec9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/cougar_canyon2/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/29619/1 diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig index 00db10e..f67f9b0 100644 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ b/src/mainboard/intel/cougar_canyon2/Kconfig @@ -29,7 +29,7 @@ int default 16 -config SMBIOS_SYSTEM_ENCLOSURE_TYPE +config SMBIOS_ENCLOSURE_TYPE hex default 0x09 # This is a mobile platform -- To view, visit https://review.coreboot.org/29619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9f4640ef040dc6a1d39ecb8b3378266e4dd5cec9 Gerrit-Change-Number: 29619 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: cpu/intel/fsp_model_406dx: Remove unused FSP_MODEL_406DX_{A1, B0}
by Elyes HAOUAS (Code Review) 13 Nov '18

13 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29618 Change subject: cpu/intel/fsp_model_406dx: Remove unused FSP_MODEL_406DX_{A1,B0} ...................................................................... cpu/intel/fsp_model_406dx: Remove unused FSP_MODEL_406DX_{A1,B0} Change-Id: I12ca33756c7d197de22d307448e27a504678537c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_406dx/Kconfig 1 file changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/29618/1 diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 4c79b23..bbca22f 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -37,18 +37,6 @@ # Microcode header files are delivered in FSP package select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN -choice - prompt "Rangeley CPU Stepping" - default FSP_MODEL_406DX_B0 - -config FSP_MODEL_406DX_A1 - bool "A1" - -config FSP_MODEL_406DX_B0 - bool "B0" - -endchoice - config BOOTBLOCK_CPU_INIT string default "cpu/intel/fsp_model_406dx/bootblock.c" -- To view, visit https://review.coreboot.org/29618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I12ca33756c7d197de22d307448e27a504678537c Gerrit-Change-Number: 29618 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: drivers/intel/fsp1_1: Remove unused DISPLAY_FAST_BOOT_DATA
by Elyes HAOUAS (Code Review) 13 Nov '18

13 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29617 Change subject: drivers/intel/fsp1_1: Remove unused DISPLAY_FAST_BOOT_DATA ...................................................................... drivers/intel/fsp1_1: Remove unused DISPLAY_FAST_BOOT_DATA Change-Id: I405b79ee192317c86725f9bf0b1d166c045d30e2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/fsp1_1/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29617/1 diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index a70f00d..13de66c 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -59,10 +59,6 @@ value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool). -config DISPLAY_FAST_BOOT_DATA - bool "Display fast boot data" - default n - config DISPLAY_HOBS bool "Display hand-off-blocks (HOBs)" default n -- To view, visit https://review.coreboot.org/29617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I405b79ee192317c86725f9bf0b1d166c045d30e2 Gerrit-Change-Number: 29617 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: cbfstool: add unprocessed flag for file exporting
by Joel Kitching (Code Review) 13 Nov '18

13 Nov '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/29616 Change subject: cbfstool: add unprocessed flag for file exporting ...................................................................... cbfstool: add unprocessed flag for file exporting Add an unprocessed flag (-U) which modifies how files are exported. In the case of a compressed raw file, extract without decompressing. In the case of a stage or payload, extract without decompressing or converting to an ELF. This can be useful for verifying the integrity of a stage or payload, since converting to an ELF may not be a deterministic process on different platforms or coreboot versions. BUG=b:111577108 TEST=USE=cb_legacy_tianocore emerge-eve edk2 coreboot-utils chromeos-bootimage cd /build/eve/firmware /build/eve/usr/bin/cbfstool image.bin extract -r RW_LEGACY \ -n payload -f /tmp/payload_1 -U START=$((16#`xxd -s 20 -l 4 -p tianocore.cbfs`)) SIZE=$((16#`xxd -s 8 -l 4 -p tianocore.cbfs`)) dd if=tianocore.cbfs skip=$START count=$SIZE bs=1 > /tmp/payload_2 diff /tmp/payload_1 /tmp/payload_2 rm /tmp/payload_1 /tmp/payload_2 Change-Id: I351d471d699daedd51adf4a860661877f25607e6 Signed-off-by: Joel Kitching <kitching(a)chromium.org> --- M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h M util/cbfstool/cbfstool.c 3 files changed, 42 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/29616/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 74572a9..d50ebbb 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -1283,7 +1283,7 @@ } int cbfs_export_entry(struct cbfs_image *image, const char *entry_name, - const char *filename, uint32_t arch) + const char *filename, uint32_t arch, bool do_processing) { struct cbfs_file *entry = cbfs_get_entry(image, entry_name); struct buffer buffer; @@ -1292,26 +1292,33 @@ return -1; } + unsigned int compressed_size = ntohl(entry->len); unsigned int decompressed_size = 0; unsigned int compression = cbfs_file_get_compression_info(entry, &decompressed_size); - - decomp_func_ptr decompress = decompression_function(compression); - if (!decompress) { - ERROR("looking up decompression routine failed\n"); - return -1; + /* Force nop decompression */ + decomp_func_ptr decompress = decompression_function(CBFS_COMPRESS_NONE); + if (do_processing) { + decompress = decompression_function(compression); + if (!decompress) { + ERROR("looking up decompression routine failed\n"); + return -1; + } } - LOG("Found file %.30s at 0x%x, type %.12s, size %d\n", + LOG("Found file %.30s at 0x%x, type %.12s, compressed %d, size %d\n", entry_name, cbfs_get_entry_addr(image, entry), - get_cbfs_entry_type_name(ntohl(entry->type)), decompressed_size); + get_cbfs_entry_type_name(ntohl(entry->type)), compressed_size, + decompressed_size); + unsigned int buffer_size = + do_processing ? decompressed_size : compressed_size; buffer_init(&buffer, strdup("(cbfs_export_entry)"), NULL, 0); + buffer.data = malloc(buffer_size); + buffer.size = buffer_size; - buffer.data = malloc(decompressed_size); - buffer.size = decompressed_size; - if (decompress(CBFS_SUBHEADER(entry), ntohl(entry->len), - buffer.data, buffer.size, NULL)) { + if (decompress(CBFS_SUBHEADER(entry), compressed_size, + buffer.data, buffer.size, NULL)) { ERROR("decompression failed for %s\n", entry_name); buffer_delete(&buffer); return -1; @@ -1323,13 +1330,19 @@ * one has to do a second pass for stages to potentially decompress * the stage data to make it more meaningful. */ - if (ntohl(entry->type) == CBFS_COMPONENT_STAGE) { - if (cbfs_stage_make_elf(&buffer, arch)) { - buffer_delete(&buffer); - return -1; + if (do_processing) { + int (*make_elf)(struct buffer *, uint32_t) = NULL; + switch (ntohl(entry->type)) { + case CBFS_COMPONENT_STAGE: + make_elf = cbfs_stage_make_elf; + break; + case CBFS_COMPONENT_SELF: + make_elf = cbfs_payload_make_elf; + break; } - } else if (ntohl(entry->type) == CBFS_COMPONENT_SELF) { - if (cbfs_payload_make_elf(&buffer, arch)) { + if (make_elf && make_elf(&buffer, arch)) { + ERROR("Failed to write %s into %s.\n", + entry_name, filename); buffer_delete(&buffer); return -1; } diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 5772b1b..0cffb9c 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -98,7 +98,7 @@ /* Exports an entry to external file. * Returns 0 on success, otherwise (ex, not found) non-zero. */ int cbfs_export_entry(struct cbfs_image *image, const char *entry_name, - const char *filename, uint32_t arch); + const char *filename, uint32_t arch, bool do_processing); /* Adds an entry to CBFS image by given name and type. If content_offset is * non-zero, try to align "content" (CBFS_SUBHEADER(p)) at content_offset. diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 28e0e5d..f0fbf5a 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -83,6 +83,7 @@ bool stage_xip; bool autogen_attr; bool machine_parseable; + bool unprocessed; int fit_empty_entries; enum comp_algo compression; int precompression; @@ -1095,7 +1096,7 @@ return 1; return cbfs_export_entry(&image, param.name, param.filename, - param.arch); + param.arch, !param.unprocessed); } static int cbfs_write(void) @@ -1314,7 +1315,7 @@ {"compact", "r:h?", cbfs_compact, true, true}, {"copy", "r:R:h?", cbfs_copy, true, true}, {"create", "M:r:s:B:b:H:o:m:vh?", cbfs_create, true, true}, - {"extract", "H:r:m:n:f:vh?", cbfs_extract, true, false}, + {"extract", "H:r:m:n:f:Uvh?", cbfs_extract, true, false}, {"layout", "wvh?", cbfs_layout, false, false}, {"print", "H:r:vkh?", cbfs_print, true, false}, {"read", "r:f:vh?", cbfs_read, true, false}, @@ -1362,6 +1363,7 @@ {"xip", no_argument, 0, 'y' }, {"gen-attribute", no_argument, 0, 'g' }, {"mach-parseable",no_argument, 0, 'k' }, + {"unprocessed", no_argument, 0, 'U' }, {NULL, 0, 0, 0 } }; @@ -1428,6 +1430,7 @@ " -d Accept short data; fill downward/from top\n" " -F Force action\n" " -g Generate position and alignment arguments\n" + " -U Unprocessed; don't decompress or make ELF\n" " -v Provide verbose output\n" " -h Display this help message\n\n" "COMMANDs:\n" @@ -1473,8 +1476,8 @@ "List mutable (or, with -w, readable) image regions\n" " print [-r image,regions] " "Show the contents of the ROM\n" - " extract [-r image,regions] [-m ARCH] -n NAME -f FILE " - "Extracts a raw payload from ROM\n" + " extract [-r image,regions] [-m ARCH] -n NAME -f FILE [-U] " + "Extracts a file from ROM\n" " write [-F] -r image,regions -f file [-u | -d] [-i int] " "Write file into same-size [or larger] raw region\n" " read [-r fmap-region] -f file " @@ -1770,6 +1773,9 @@ case 'k': param.machine_parseable = true; break; + case 'U': + param.unprocessed = true; + break; case 'h': case '?': usage(argv[0]); -- To view, visit https://review.coreboot.org/29616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I351d471d699daedd51adf4a860661877f25607e6 Gerrit-Change-Number: 29616 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com>

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Change in coreboot[master]: mb/google/sarien: Enable EC _PTS/_WAK methods
by Duncan Laurie (Code Review) 13 Nov '18

13 Nov '18

Duncan Laurie has removed a vote on this change. Change subject: mb/google/sarien: Enable EC _PTS/_WAK methods ...................................................................... Removed Verified-1 by build bot (Jenkins) <no-reply(a)coreboot.org> -- To view, visit https://review.coreboot.org/29614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: deleteVote Gerrit-Change-Id: I52be1c1cd7adae9ad317a51868735eb87a410549 Gerrit-Change-Number: 29614 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common: Add option to call EC _PTS/_WAK methods
by Duncan Laurie (Code Review) 13 Nov '18

13 Nov '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/29487 ) Change subject: soc/intel/common: Add option to call EC _PTS/_WAK methods ...................................................................... soc/intel/common: Add option to call EC _PTS/_WAK methods Some embedded controllers expect to be sent a command when the OS calls the ACPI \_PTS and \_WAK methods. For example see the code in ec/google/wilco/acpi/platform.asl that tells the EC when the methods have been executed by the OS. Not all ECs may define these methods so this change requires also setting a Kconfig option to enable it. Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/29487 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/Kconfig M src/soc/intel/common/acpi/platform.asl 2 files changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 42043d7..44d9f23 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -58,6 +58,13 @@ bool default n +config SOC_INTEL_COMMON_ACPI_EC_PTS_WAK + bool + default n + help + Set this option to have the platform level _PTS/_WAK methods call + methods provided by the Embedded Controller. + config SOC_INTEL_COMMON_NHLT bool default n diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index 1d0294b..01913b5 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -33,6 +33,11 @@ Method (_PTS, 1) { Store (POST_OS_ENTER_PTS, DBG0) + +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) + /* Call EC _PTS handler */ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) +#endif } /* The _WAK method is called on system wakeup */ @@ -40,5 +45,11 @@ Method (_WAK, 1) { Store (POST_OS_ENTER_WAKE, DBG0) + +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) + /* Call EC _WAK handler */ + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +#endif + Return (Package(){0,0}) } -- To view, visit https://review.coreboot.org/29487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10 Gerrit-Change-Number: 29487 Gerrit-PatchSet: 6 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: google/grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number
by Kevin Chiu (Code Review) 13 Nov '18

13 Nov '18

Hello build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29557 to look at the new patch set (#3). Change subject: google/grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number ...................................................................... google/grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number Correct SPD Module Part Number to "K4A8G165WC-BCTD" from "M471A5244CB0-CTD". BUG=b:119400832 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage mosys memory spd print all 0 | DDR4 | SO-DIMM 0 | 1-78: Samsung | 00000000 | K4A8G165WC-BCTD 0 | 4096 | 1 | 64 0 | DDR4-1333, DDR4-1600, DDR4-2400 Change-Id: I29505d3eece2283579499a0afc424c4a28017fa5 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29557/3 -- To view, visit https://review.coreboot.org/29557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I29505d3eece2283579499a0afc424c4a28017fa5 Gerrit-Change-Number: 29557 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/sarien: Enable EC _PTS/_WAK methods
by Furquan Shaikh (Code Review) 12 Nov '18

12 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29614 ) Change subject: mb/google/sarien: Enable EC _PTS/_WAK methods ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/29614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I52be1c1cd7adae9ad317a51868735eb87a410549 Gerrit-Change-Number: 29614 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 12 Nov 2018 22:15:35 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit November 2018