coreboot-gerrit November 2018

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Change in coreboot[master]: mb/google/sarien: Add sku_id function
by Patrick Georgi (Code Review) 07 Nov '18

07 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29486 ) Change subject: mb/google/sarien: Add sku_id function ...................................................................... mb/google/sarien: Add sku_id function This change adds a sku_id() function that returns a static value to differentiate the sarien and arcada boards. Change-Id: I1fecc675573a6aece7188aae9370733068d45dbf Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/29486 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/sarien/Makefile.inc A src/mainboard/google/sarien/sku.c A src/mainboard/google/sarien/variants/arcada/include/variant/variant.h A src/mainboard/google/sarien/variants/sarien/include/variant/variant.h 4 files changed, 67 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/sarien/Makefile.inc b/src/mainboard/google/sarien/Makefile.inc index 3370900..085fee6 100644 --- a/src/mainboard/google/sarien/Makefile.inc +++ b/src/mainboard/google/sarien/Makefile.inc @@ -16,6 +16,7 @@ bootblock-y += bootblock.c ramstage-y += ramstage.c +ramstage-y += sku.c romstage-y += romstage.c diff --git a/src/mainboard/google/sarien/sku.c b/src/mainboard/google/sarien/sku.c new file mode 100644 index 0000000..9fc61a3 --- /dev/null +++ b/src/mainboard/google/sarien/sku.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <variant/variant.h> + +uint32_t sku_id(void) +{ + return VARIANT_SKU_ID; +} diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h b/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h new file mode 100644 index 0000000..f1e551a --- /dev/null +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/variant.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* Arcada is SKU ID 2 */ +#define VARIANT_SKU_ID 2 + +#endif diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h b/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h new file mode 100644 index 0000000..d0be7fc --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/variant.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +/* Sarien is SKU ID 1 */ +#define VARIANT_SKU_ID 1 + +#endif -- To view, visit https://review.coreboot.org/29486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I1fecc675573a6aece7188aae9370733068d45dbf Gerrit-Change-Number: 29486 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/fizz: Comment variant names in Kconfig
by Patrick Georgi (Code Review) 07 Nov '18

07 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29464 ) Change subject: mb/google/fizz: Comment variant names in Kconfig ...................................................................... mb/google/fizz: Comment variant names in Kconfig Refer to CL:1043916 BUG=none BRANCH=none TEST=none Change-Id: I3fbbbcac334646f68b8b9fd38fbb529d9e833581 Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29464 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/fizz/Kconfig.name 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/fizz/Kconfig.name b/src/mainboard/google/fizz/Kconfig.name index d7343f9..608a58d 100644 --- a/src/mainboard/google/fizz/Kconfig.name +++ b/src/mainboard/google/fizz/Kconfig.name @@ -1,7 +1,9 @@ +comment "Fizz" + config BOARD_GOOGLE_FIZZ - bool "Fizz" + bool "-> Fizz" select BOARD_GOOGLE_BASEBOARD_FIZZ config BOARD_GOOGLE_KARMA - bool "Karma" + bool "-> Karma" select BOARD_GOOGLE_BASEBOARD_FIZZ -- To view, visit https://review.coreboot.org/29464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I3fbbbcac334646f68b8b9fd38fbb529d9e833581 Gerrit-Change-Number: 29464 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: drivers/spi: Return error in failure case
by Philipp Deppenwiese (Code Review) 07 Nov '18

07 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29531 ) Change subject: drivers/spi: Return error in failure case ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9de300f651ac93889dafa7377c876bf5ae2c50cc Gerrit-Change-Number: 29531 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Nov 2018 16:29:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: add the hynix memory parts
by Furquan Shaikh (Code Review) 07 Nov '18

07 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29524 ) Change subject: mb/google/poppy/variants/nami: add the hynix memory parts ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I137259b88f39779768a58959a2dcc565645eee6d Gerrit-Change-Number: 29524 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Nov 2018 16:19:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86/smbios: [WIP] Add CPU SOCKET TYPE
by Elyes HAOUAS (Code Review) 07 Nov '18

07 Nov '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/29529 ) Change subject: arch/x86/smbios: [WIP] Add CPU_SOCKET_TYPE ...................................................................... Patch Set 7: > Over all looks ok, but I would like analysis on the impact on > SMBIOS tools. I've used bits-2079 (BIOS Implementation Test Suite) on LGA775, it displays the right socket. (still missing, the voltage, frequency, ... , but this is not related to current topic) -- To view, visit https://review.coreboot.org/29529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0 Gerrit-Change-Number: 29529 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Nov 2018 16:17:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Drop FSP_CAR options
by Nico Huber (Code Review) 07 Nov '18

07 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29533 Change subject: soc/intel/skylake: Drop FSP_CAR options ...................................................................... soc/intel/skylake: Drop FSP_CAR options It's not implemented for Skylake, all combinations that try to enable it either result in Kconfig or linker errors. Move `config SKIP_FSP_CAR` into drivers/intel/fsp1_1 where it's effective. TEST=Built Intel/Kunimitsu (FSP1.1) and Intel/KBLRVP8 (FSP2.0) default configs with and without this patch: binaries stay the same. Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/drivers/intel/fsp1_1/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/romstage/romstage.c 3 files changed, 10 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/29533/1 diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index a70f00d..8054021 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -104,4 +104,9 @@ bool "Reset the system on S3 wake when ramstage cache invalid." default n +config SKIP_FSP_CAR + def_bool n + help + Selected by platforms that implement their own CAR setup. + endif #PLATFORM_USES_FSP1_1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 1449d3d..e5a60f6 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -34,6 +34,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select IOAPIC select MRC_SETTINGS_PROTECT @@ -54,6 +55,7 @@ select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -100,6 +102,7 @@ depends on !MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP1_1 select DISPLAY_FSP_ENTRY_POINTS + select SKIP_FSP_CAR config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -276,32 +279,6 @@ help Include DSP firmware settings for DA7219 headset codec. -choice - prompt "Cache-as-ram implementation" - default USE_SKYLAKE_CAR_NEM_ENHANCED - help - This option allows you to select how cache-as-ram (CAR) is set up. - -config USE_SKYLAKE_CAR_NEM_ENHANCED - bool "Enhanced Non-evict mode" - select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED - help - A current limitation of NEM (Non-Evict mode) is that code and data - sizes are derived from the requirement to not write out any modified - cache line. With NEM, if there is no physical memory behind the - cached area, the modified data will be lost and NEM results will be - inconsistent. ENHANCED NEM guarantees that modified data is always - kept in cache while clean data is replaced. - -config USE_SKYLAKE_FSP_CAR - bool "Use FSP CAR" - select FSP_CAR - help - Use FSP APIs to initialize and tear down the Cache-As-Ram. - -endchoice - config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 @@ -316,12 +293,6 @@ default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_KABYLAKE -config SKIP_FSP_CAR - bool "Skip cache as RAM setup in FSP" - default y - help - Skip Cache as RAM setup in FSP. - config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 215b07c..4eedb96 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -85,10 +85,8 @@ upd->SaGv = config->SaGv; upd->RMT = config->Rmt; upd->DdrFreqLimit = config->DdrFreqLimit; - if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) { - upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; - upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE; - } + upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; + upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE; } void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, -- To view, visit https://review.coreboot.org/29533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28 Gerrit-Change-Number: 29533 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: arch/x86/smbios: [WIP] Add CPU SOCKET TYPE
by Elyes HAOUAS (Code Review) 07 Nov '18

07 Nov '18

Hello Richard Spiegel, build bot (Jenkins), Raul Rangel, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29529 to look at the new patch set (#7). Change subject: arch/x86/smbios: [WIP] Add CPU_SOCKET_TYPE ...................................................................... arch/x86/smbios: [WIP] Add CPU_SOCKET_TYPE CPU_SOCKET_TYPE values added in accordance with SMBIOS Reference Specification Version: 3.2.0 AMD's have CPU_SOCKET_TYPE but are not a same as SMBIOS spec. Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/smbios.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/socket_AM2r2/Kconfig M src/cpu/amd/socket_AM3/Kconfig M src/cpu/amd/socket_ASB2/Kconfig M src/cpu/amd/socket_C32/Kconfig M src/cpu/amd/socket_FM2/Kconfig M src/cpu/amd/socket_F_1207/Kconfig M src/cpu/amd/socket_G34/Kconfig M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_BGA1284/Kconfig M src/cpu/intel/socket_BGA956/Kconfig M src/cpu/intel/socket_FCBGA1023/Kconfig M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_LGA1155/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_mFCPGA478/Kconfig M src/cpu/intel/socket_mPGA478MN/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/intel/socket_rPGA988B/Kconfig M src/cpu/intel/socket_rPGA989/Kconfig M src/northbridge/amd/amdfam10/raminit_amdmct.c M src/northbridge/amd/amdmct/mct/Makefile.inc M src/northbridge/amd/amdmct/mct_ddr3/Makefile.inc M src/northbridge/amd/amdmct/wrappers/mcti_d.c 25 files changed, 83 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/29529/7 -- To view, visit https://review.coreboot.org/29529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0 Gerrit-Change-Number: 29529 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: arch/x86/smbios: [WIP] Add CPU SOCKET TYPE
by Richard Spiegel (Code Review) 07 Nov '18

07 Nov '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29529 ) Change subject: arch/x86/smbios: [WIP] Add CPU_SOCKET_TYPE ...................................................................... Patch Set 6: Over all looks ok, but I would like analysis on the impact on SMBIOS tools. -- To view, visit https://review.coreboot.org/29529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0 Gerrit-Change-Number: 29529 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Nov 2018 14:42:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: arch/x86/smbios: [WIP] Add CPU SOCKET TYPE
by Richard Spiegel (Code Review) 07 Nov '18

07 Nov '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29529 ) Change subject: arch/x86/smbios: [WIP] Add CPU_SOCKET_TYPE ...................................................................... Patch Set 6: Raul, could you check impact to Mosys? -- To view, visit https://review.coreboot.org/29529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0 Gerrit-Change-Number: 29529 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Nov 2018 14:40:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP]mb/opencellular/elgon: Enable write protection
by Patrick Rudolph (Code Review) 07 Nov '18

07 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/29532 Change subject: [WIP]mb/opencellular/elgon: Enable write protection ...................................................................... [WIP]mb/opencellular/elgon: Enable write protection * Verify the flash write protection on each boot * Program non-volatile write protection on first boot Change-Id: I6a940c69ecb1dfd9704b2101c263570bebc5540e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/opencellular/elgon/bootblock.c 1 file changed, 44 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/29532/1 diff --git a/src/mainboard/opencellular/elgon/bootblock.c b/src/mainboard/opencellular/elgon/bootblock.c index e6109f1..9dfd1b8 100644 --- a/src/mainboard/opencellular/elgon/bootblock.c +++ b/src/mainboard/opencellular/elgon/bootblock.c @@ -18,6 +18,9 @@ #include <soc/spi.h> #include <soc/uart.h> #include <soc/gpio.h> +#include <spi_flash.h> +#include <console/console.h> +#include <fmap.h> #include "mainboard.h" void bootblock_mainboard_early_init(void) @@ -49,8 +52,48 @@ gpio_output(ELGON_GPIO_SPI_MUX, 1); } +/** + * Handle flash write protection. + * This code verifies the write-protection on each boot. + * Enabling the write protection does only run on the first boot. + * An error is fatal as it breaks the Chain Of Trust. + */ +static void protect_ro_rgn_spi_flash(void) +{ + const struct spi_flash *flash = boot_device_spi_flash(); + const char *fmapname = "WP_RO"; + struct region ro_rgn; + + if (fmap_locate_area(fmapname, &ro_rgn)) { + printk(BIOS_ERR, "%s: No %s FMAP section.\n", __func__, + fmapname); + die("Can't verify flash protections!"); + } + + u8 reg8 = 0; + spi_flash_status(flash, &reg8); + + /* Check if SRP0 is set and RO region is protected */ + if (!(reg8 & 0x80) || + spi_flash_is_write_protected(flash, &ro_rgn) != 1) { + printk(BIOS_WARNING, "%s: FMAP section %s is not write-protected\n", + __func__, fmapname); + + /* + * Need to protect flash region : + * WP_RO read only and use /WP pin + * non-volatile programming + */ + if (spi_flash_set_write_protected(flash, &ro_rgn, 1, + SPI_WRITE_PROTECTION_PIN) != 0) + die("Failed to write-protect WP_RO region!"); + } + printk(BIOS_INFO, "%s: FMAP section %s is write-protected\n", + __func__, fmapname); +} + void bootblock_mainboard_init(void) { configure_spi_flash(); - // FIXME: Check SPI flash WP bits + protect_ro_rgn_spi_flash(); } -- To view, visit https://review.coreboot.org/29532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6a940c69ecb1dfd9704b2101c263570bebc5540e Gerrit-Change-Number: 29532 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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coreboot-gerrit November 2018