coreboot-gerrit November 2018

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST
by Nick Vaccaro (Code Review) 07 Nov '18

07 Nov '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/29538 Change subject: mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST ...................................................................... mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ strom after S3 resume and hence configuring GPP_D9 and GPP_D10 to use PLTRST. BUG=b:119202293 TEST=none Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/29538/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 9aa7706..70b748b 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -180,9 +180,9 @@ /* D8 : ISH_I2C1_SCL ==> NC */ PAD_CFG_NC(GPP_D8), /* D9 : ISH_SPI_CS# ==> PCH_SR1_INT_L */ - PAD_CFG_GPI_APIC(GPP_D9, NONE, DEEP), + PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> PCH_SR0_INT_L */ - PAD_CFG_GPI_APIC(GPP_D10, NONE, DEEP), + PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST), /* D11 : ISH_SPI_MISO ==> NC */ PAD_CFG_NC(GPP_D11), /* D12 : ISH_SPI_MOSI ==> NC */ -- To view, visit https://review.coreboot.org/29538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43 Gerrit-Change-Number: 29538 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: soc/intel/common: Call EC _PTS/_WAK methods if defined
by Duncan Laurie (Code Review) 07 Nov '18

07 Nov '18

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Change in coreboot[master]: soc/intel/common: Call EC _PTS/_WAK methods if defined
by Duncan Laurie (Code Review) 07 Nov '18

07 Nov '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/29487 ) Change subject: soc/intel/common: Call EC _PTS/_WAK methods if defined ...................................................................... Patch Set 2: Actually the iasl version is slightly newer in crossgcc: ASL+ Optimizing Compiler/Disassembler version 20180810 The jenkins builder is using: ASL+ Optimizing Compiler/Disassembler version 20180531 -- To view, visit https://review.coreboot.org/29487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10 Gerrit-Change-Number: 29487 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Nov 2018 20:33:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common: Call EC _PTS/_WAK methods if defined
by Duncan Laurie (Code Review) 07 Nov '18

07 Nov '18

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Change in coreboot[master]: soc/intel/common: Call EC _PTS/_WAK methods if defined
by Duncan Laurie (Code Review) 07 Nov '18

07 Nov '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/29487 ) Change subject: soc/intel/common: Call EC _PTS/_WAK methods if defined ...................................................................... Patch Set 2: > Patch Set 2: > > > Patch Set 1: > > > > > Patch Set 1: > > > > > > Looks like condrefof only works for the If statement and trying to actually call the method, even if it will not reach that code, causes the ASL compiler to fail. > > > > > > I guess I will need to guard with a Kconfig option. > > > > Aah yes. Does adding an External help: > > External (\_SB.PCI0.LPCB.EC0.WAK, MethodObj) > > External (\_SB.PCI0.LPCB.EC0.PTS, MethodObj) > > Yeah this works, but I was concerned it would have issues at the OS level if these methods didn't actually exist. I did some testing and it seems to be ok. Of course I tested the case that was failing before and did not actually re-compile for the sarien/arcada boards. It seems a kconfig option is the only safe path forward here. -- To view, visit https://review.coreboot.org/29487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10 Gerrit-Change-Number: 29487 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Nov 2018 20:28:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/{lenovo, roda}: Remove DISPLAY_DEVICE_2_IS_LCD_SCREEN macro
by Peter Lemenkov (Code Review) 07 Nov '18

07 Nov '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29537 Change subject: mb/{lenovo,roda}: Remove DISPLAY_DEVICE_2_IS_LCD_SCREEN macro ...................................................................... mb/{lenovo,roda}: Remove DISPLAY_DEVICE_2_IS_LCD_SCREEN macro This macro is no longer used since commit dd2bc3f8 with Change-Id I556769e5e28b83e7465e3db689e26c8c0ab44757 ("igd.asl rewrite"). Change-Id: Iabf927d8462673cb96851c01318d826d4c422e0d Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t400/dsdt.asl M src/mainboard/lenovo/x200/dsdt.asl M src/mainboard/roda/rk9/dsdt.asl 3 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/29537/1 diff --git a/src/mainboard/lenovo/t400/dsdt.asl b/src/mainboard/lenovo/t400/dsdt.asl index 6ba4774..c9f4c08 100644 --- a/src/mainboard/lenovo/t400/dsdt.asl +++ b/src/mainboard/lenovo/t400/dsdt.asl @@ -18,7 +18,6 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define DISPLAY_DEVICE_2_IS_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index 5452fe3..42fcab3 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -18,7 +18,6 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define DISPLAY_DEVICE_2_IS_LCD_SCREEN 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/roda/rk9/dsdt.asl b/src/mainboard/roda/rk9/dsdt.asl index 5c5ca2f..dee3cf4 100644 --- a/src/mainboard/roda/rk9/dsdt.asl +++ b/src/mainboard/roda/rk9/dsdt.asl @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#define DISPLAY_DEVICE_2_IS_LCD_SCREEN 1 - DefinitionBlock( "dsdt.aml", "DSDT", -- To view, visit https://review.coreboot.org/29537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iabf927d8462673cb96851c01318d826d4c422e0d Gerrit-Change-Number: 29537 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

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Change in coreboot[master]: mb/google/sarien: Disable eSPI when ACPI is enabled
by Duncan Laurie (Code Review) 07 Nov '18

07 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29536 Change subject: mb/google/sarien: Disable eSPI when ACPI is enabled ...................................................................... mb/google/sarien: Disable eSPI when ACPI is enabled Select the option to disable eSPI when ACPI is enabled so the EC is unable to assert an SMI when booted into the OS. There is a kernel driver that implements the same mailbox interface so it cannot also be used by the SMI handler. Change-Id: I8bafc749f22aed5595e19e773762ee8b038950b9 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29536/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index fcf9f44..e571be2 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_HAS_TPM2 select SOC_INTEL_COFFEELAKE select SOC_INTEL_CANNONLAKE_MEMCFG_INIT + select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP select TPM2 -- To view, visit https://review.coreboot.org/29536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8bafc749f22aed5595e19e773762ee8b038950b9 Gerrit-Change-Number: 29536 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: soc/intel/common: Add option to disable eSPI SMI at runtime
by Duncan Laurie (Code Review) 07 Nov '18

07 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29535 Change subject: soc/intel/common: Add option to disable eSPI SMI at runtime ...................................................................... soc/intel/common: Add option to disable eSPI SMI at runtime Add an option that will disable eSPI SMI when ACPI mode is enabled, and re-enable eSPI SMI when ACPI mode is disabled. Additionally it ensures eSPI SMI is disabled on the ACPI OS resume path. This allows a mainboard to ensure that the Embedded Controller will not be able to assert SMI at runtime when booted into an ACPI aware operating system. This was tested on a Sarien board with the Wilco EC to ensure that the eSPI SMI enable bit is clear when booted into the OS, and remains clear after resume. Change-Id: Ic305c3498dfa4b8166cfdb070fc404dd4618ba3c Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/common/block/smm/Kconfig M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smm.c 3 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29535/1 diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index 909382e..cc6bc44 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -8,6 +8,14 @@ help Intel Processor trap flag if it is supported +config SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS + bool + default n + help + Disable eSPI SMI when ACPI mode is enabled. This will + prevent the embedded controller from asserting SMI when + booted into an ACPI aware OS. + config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS int default 100 if CHROMEOS diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 9e8d346..0832bb5 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -362,10 +362,14 @@ break; case APM_CNT_ACPI_DISABLE: pmc_disable_pm1_control(SCI_EN); + if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)) + pmc_enable_smi(ESPI_SMI_EN); printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case APM_CNT_ACPI_ENABLE: pmc_enable_pm1_control(SCI_EN); + if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS)) + pmc_disable_smi(ESPI_SMI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case APM_CNT_GNVS_UPDATE: diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 6059995..d929975 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <bootstate.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <intelblocks/pmclib.h> @@ -93,3 +94,11 @@ *start = (void *)sa_get_tseg_base(); *size = sa_get_tseg_size(); } + +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS) +static void smm_disable_espi(void *dest) +{ + pmc_disable_smi(ESPI_SMI_EN); +} +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, smm_disable_espi, NULL); +#endif -- To view, visit https://review.coreboot.org/29535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic305c3498dfa4b8166cfdb070fc404dd4618ba3c Gerrit-Change-Number: 29535 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: soc/intel/common: Call EC _PTS/_WAK methods if defined
by Duncan Laurie (Code Review) 07 Nov '18

07 Nov '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/29487 ) Change subject: soc/intel/common: Call EC _PTS/_WAK methods if defined ...................................................................... Patch Set 2: > Patch Set 1: > > > Patch Set 1: > > > > Looks like condrefof only works for the If statement and trying to actually call the method, even if it will not reach that code, causes the ASL compiler to fail. > > > > I guess I will need to guard with a Kconfig option. > > Aah yes. Does adding an External help: > External (\_SB.PCI0.LPCB.EC0.WAK, MethodObj) > External (\_SB.PCI0.LPCB.EC0.PTS, MethodObj) Yeah this works, but I was concerned it would have issues at the OS level if these methods didn't actually exist. I did some testing and it seems to be ok. -- To view, visit https://review.coreboot.org/29487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10 Gerrit-Change-Number: 29487 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Nov 2018 18:21:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common: Call EC _PTS/_WAK methods if defined
by Duncan Laurie (Code Review) 07 Nov '18

07 Nov '18

Hello build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29487 to look at the new patch set (#2). Change subject: soc/intel/common: Call EC _PTS/_WAK methods if defined ...................................................................... soc/intel/common: Call EC _PTS/_WAK methods if defined Some embedded controllers expect to be sent a command when the OS calls the ACPI \_PTS and \_WAK methods. For example see the code in ec/google/wilco/acpi/platform.asl that tells the EC when the methods have been executed by the OS. Not all ECs may define these methods so this change uses CondRefOf to check if the EC method exists, and if so will call it, providing the same argument that was passed to the system level methods. Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/common/acpi/platform.asl 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/29487/2 -- To view, visit https://review.coreboot.org/29487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10 Gerrit-Change-Number: 29487 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit November 2018