coreboot-gerrit November 2018

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Change in coreboot[master]: drivers/elog: Add Ramstage helper to add boot count
by Karthik Ramasubramanian (Code Review) 08 Nov '18

08 Nov '18

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/29542 Change subject: drivers/elog: Add Ramstage helper to add boot count ...................................................................... drivers/elog: Add Ramstage helper to add boot count Add a helper function specific to ramstage to add the boot count information into event log at ramstage. BUG=b:117884485 BRANCH=None TEST=Add an event log from romstage, boot to ChromeOS Change-Id: Ic79f1a702548d8a2cd5c13175a9b2d718527953f Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/drivers/elog/elog.c 1 file changed, 15 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/29542/1 diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index d1a9f4f..7c650a1 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -793,6 +793,19 @@ #endif } +static void ramstage_elog_add_boot_count(void) +{ + if (elog_do_add_boot_count()) { + elog_add_event_dword(ELOG_TYPE_BOOT, boot_count_read()); + +#if IS_ENABLED(CONFIG_ARCH_X86) + /* Check and log POST codes from previous boot */ + if (IS_ENABLED(CONFIG_CMOS_POST)) + cmos_post_log(); +#endif + } +} + /* * Event log main entry point */ @@ -843,15 +856,8 @@ " shrink size %d\n", region_device_sz(&g_elog_statep->nv_dev), g_elog_statep->full_threshold, g_elog_statep->shrink_size); - if (elog_do_add_boot_count()) { - elog_add_event_dword(ELOG_TYPE_BOOT, boot_count_read()); - -#if IS_ENABLED(CONFIG_ARCH_X86) - /* Check and log POST codes from previous boot */ - if (IS_ENABLED(CONFIG_CMOS_POST)) - cmos_post_log(); -#endif - } + if (ENV_RAMSTAGE) + ramstage_elog_add_boot_count(); return 0; } -- To view, visit https://review.coreboot.org/29542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic79f1a702548d8a2cd5c13175a9b2d718527953f Gerrit-Change-Number: 29542 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org>

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Change in coreboot[master]: drivers/elog: Group event log state information
by Karthik Ramasubramanian (Code Review) 08 Nov '18

08 Nov '18

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/29541 Change subject: drivers/elog: Group event log state information ...................................................................... drivers/elog: Group event log state information Group event log state information together to manage them better during different stages of coreboot. BUG=b:117884485 BRANCH=None TEST=Add an event log from romstage, boot to ChromeOS Change-Id: I62792c0f5063c89ad11b512f1777c7ab8a2c13e5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/drivers/elog/elog.c 1 file changed, 102 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/29541/1 diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index d3c01c2..d1a9f4f 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -16,6 +16,7 @@ #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) #include <arch/acpi.h> #endif +#include <arch/early_variables.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -42,33 +43,38 @@ #endif #define NV_NEEDS_ERASE (~(size_t)0) -/* - * Static variables for ELOG state - */ -static u16 full_threshold; -static u16 shrink_size; - -/* - * The non-volatile storage chases the mirrored copy. When nv_last_write - * is less than the mirrored last write the non-volatile storage needs - * to be updated. - */ -static size_t mirror_last_write; -static size_t nv_last_write; - -static struct region_device nv_dev; -/* Device that mirrors the eventlog in memory. */ -static struct mem_region_device mirror_dev; - -static enum { +enum elog_init_state { ELOG_UNINITIALIZED = 0, ELOG_INITIALIZED, ELOG_BROKEN, -} elog_initialized = ELOG_UNINITIALIZED; +}; + +struct elog_state { + u16 full_threshold; + u16 shrink_size; + + /* + * The non-volatile storage chases the mirrored copy. When nv_last_write + * is less than the mirrored last write the non-volatile storage needs + * to be updated. + */ + size_t mirror_last_write; + size_t nv_last_write; + + struct region_device nv_dev; + /* Device that mirrors the eventlog in memory. */ + struct mem_region_device mirror_dev; + + enum elog_init_state elog_initialized; +}; + +static struct elog_state g_elog_state CAR_GLOBAL; static inline struct region_device *mirror_dev_get(void) { - return &mirror_dev.rdev; + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + + return &g_elog_statep->mirror_dev.rdev; } static size_t elog_events_start(void) @@ -79,7 +85,9 @@ static size_t elog_events_total_space(void) { - return region_device_sz(&nv_dev) - elog_events_start(); + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + + return region_device_sz(&g_elog_statep->nv_dev) - elog_events_start(); } static struct event_header *elog_get_event_buffer(size_t offset, size_t size) @@ -89,8 +97,11 @@ static struct event_header *elog_get_next_event_buffer(size_t size) { - elog_debug("ELOG: new event at offset 0x%zx\n", mirror_last_write); - return elog_get_event_buffer(mirror_last_write, size); + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + + elog_debug("ELOG: new event at offset 0x%zx\n", + g_elog_statep->mirror_last_write); + return elog_get_event_buffer(g_elog_statep->mirror_last_write, size); } static void elog_put_event_buffer(struct event_header *event) @@ -100,53 +111,72 @@ static size_t elog_mirror_reset_last_write(void) { + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); /* Return previous write value. */ - size_t prev = mirror_last_write; - mirror_last_write = 0; + size_t prev = g_elog_statep->mirror_last_write; + + g_elog_statep->mirror_last_write = 0; return prev; } static void elog_mirror_increment_last_write(size_t size) { - mirror_last_write += size; + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + + g_elog_statep->mirror_last_write += size; } static void elog_nv_reset_last_write(void) { - nv_last_write = 0; + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + + g_elog_statep->nv_last_write = 0; } static void elog_nv_increment_last_write(size_t size) { - nv_last_write += size; + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + + g_elog_statep->nv_last_write += size; } static void elog_nv_needs_possible_erase(void) { + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + /* If last write is 0 it means it is already erased. */ - if (nv_last_write != 0) - nv_last_write = NV_NEEDS_ERASE; + if (g_elog_statep->nv_last_write != 0) + g_elog_statep->nv_last_write = NV_NEEDS_ERASE; } static bool elog_should_shrink(void) { - return mirror_last_write >= full_threshold; + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + + return g_elog_statep->mirror_last_write >= + g_elog_statep->full_threshold; } static bool elog_nv_needs_erase(void) { - return nv_last_write == NV_NEEDS_ERASE; + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + + return g_elog_statep->nv_last_write == NV_NEEDS_ERASE; } static bool elog_nv_needs_update(void) { - return nv_last_write != mirror_last_write; + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + + return g_elog_statep->nv_last_write != g_elog_statep->mirror_last_write; } static size_t elog_nv_region_to_update(size_t *offset) { - *offset = nv_last_write; - return mirror_last_write - nv_last_write; + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + + *offset = g_elog_statep->nv_last_write; + return g_elog_statep->mirror_last_write - g_elog_statep->nv_last_write; } /* @@ -318,6 +348,7 @@ { void *address; const struct region_device *rdev = mirror_dev_get(); + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); if (!size) return; @@ -331,7 +362,7 @@ return; /* Write the data to flash */ - if (rdev_writeat(&nv_dev, address, offset, size) != size) + if (rdev_writeat(&g_elog_statep->nv_dev, address, offset, size) != size) printk(BIOS_ERR, "ELOG: NV Write failed at 0x%zx, size 0x%zx\n", offset, size); @@ -344,11 +375,12 @@ */ static void elog_nv_erase(void) { - size_t size = region_device_sz(&nv_dev); + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + size_t size = region_device_sz(&g_elog_statep->nv_dev); elog_debug("%s()\n", __func__); /* Erase the sectors in this region */ - if (rdev_eraseat(&nv_dev, 0, size) != size) + if (rdev_eraseat(&g_elog_statep->nv_dev, 0, size) != size) printk(BIOS_ERR, "ELOG: erase failure.\n"); } @@ -406,11 +438,13 @@ elog_debug("elog_scan_flash()\n"); void *mirror_buffer; const struct region_device *rdev = mirror_dev_get(); - size_t size = region_device_sz(&nv_dev); + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + size_t size = region_device_sz(&g_elog_statep->nv_dev); /* Fill memory buffer by reading from SPI */ mirror_buffer = rdev_mmap_full(rdev); - if (rdev_readat(&nv_dev, mirror_buffer, 0, size) != size) { + if (rdev_readat(&g_elog_statep->nv_dev, mirror_buffer, 0, size) != + size) { rdev_munmap(rdev, mirror_buffer); printk(BIOS_ERR, "ELOG: NV read failure.\n"); return -1; @@ -574,8 +608,10 @@ static int elog_shrink(void) { + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + if (elog_should_shrink()) - return elog_shrink_by_size(shrink_size); + return elog_shrink_by_size(g_elog_statep->shrink_size); return 0; } @@ -584,16 +620,19 @@ */ static inline u8 *elog_flash_offset_to_address(void) { + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + /* Only support memory-mapped devices. */ if (!IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) return NULL; - if (!region_device_sz(&nv_dev)) + if (!region_device_sz(&g_elog_statep->nv_dev)) return NULL; /* Get a view into the read-only boot device. */ - return rdev_mmap(boot_device_ro(), region_device_offset(&nv_dev), - region_device_sz(&nv_dev)); + return rdev_mmap(boot_device_ro(), + region_device_offset(&g_elog_statep->nv_dev), + region_device_sz(&g_elog_statep->nv_dev)); } /* @@ -605,7 +644,8 @@ struct smbios_type15 *t = (struct smbios_type15 *)*current; int len = sizeof(struct smbios_type15); uintptr_t log_address; - size_t elog_size = region_device_sz(&nv_dev); + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + size_t elog_size = region_device_sz(&g_elog_statep->nv_dev); if (IS_ENABLED(CONFIG_ELOG_CBMEM)) { /* Save event log buffer into CBMEM for the OS to read */ @@ -659,7 +699,8 @@ { size_t total_size; size_t reserved_space = ELOG_MIN_AVAILABLE_ENTRIES * MAX_EVENT_SIZE; - struct region_device *rdev = &nv_dev; + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); + struct region_device *rdev = &g_elog_statep->nv_dev; elog_debug("%s()\n", __func__); @@ -682,10 +723,10 @@ total_size = MIN(4*KiB, region_device_sz(rdev)); rdev_chain(rdev, rdev, 0, total_size); - full_threshold = total_size - reserved_space; - shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100; + g_elog_statep->full_threshold = total_size - reserved_space; + g_elog_statep->shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100; - if (reserved_space > shrink_size) { + if (reserved_space > g_elog_statep->shrink_size) { printk(BIOS_ERR, "ELOG: SHRINK_PERCENTAGE too small\n"); return -1; } @@ -698,6 +739,7 @@ size_t offset; size_t size; bool erase_needed; + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); /* Determine if any updates are required. */ if (!elog_nv_needs_update()) @@ -729,7 +771,7 @@ if (elog_scan_flash() < 0) { printk(BIOS_ERR, "ELOG: Sync back from NV storage failed.\n"); elog_debug_dump_buffer("ELOG: Buffer from NV:\n"); - elog_initialized = ELOG_BROKEN; + g_elog_statep->elog_initialized = ELOG_BROKEN; return -1; } @@ -758,8 +800,9 @@ { void *mirror_buffer; size_t elog_size; + struct elog_state *g_elog_statep = car_get_var_ptr(&g_elog_state); - switch (elog_initialized) { + switch (g_elog_statep->elog_initialized) { case ELOG_UNINITIALIZED: break; case ELOG_INITIALIZED: @@ -767,7 +810,7 @@ case ELOG_BROKEN: return -1; } - elog_initialized = ELOG_BROKEN; + g_elog_statep->elog_initialized = ELOG_BROKEN; elog_debug("elog_init()\n"); @@ -775,19 +818,20 @@ if (elog_find_flash() < 0) return -1; - elog_size = region_device_sz(&nv_dev); + elog_size = region_device_sz(&g_elog_statep->nv_dev); mirror_buffer = malloc(elog_size); if (!mirror_buffer) { printk(BIOS_ERR, "ELOG: Unable to allocate backing store\n"); return -1; } - mem_region_device_rw_init(&mirror_dev, mirror_buffer, elog_size); + mem_region_device_rw_init(&g_elog_statep->mirror_dev, mirror_buffer, + elog_size); /* * Mark as initialized to allow elog_init() to be called and deemed * successful in the prepare/shrink path which adds events. */ - elog_initialized = ELOG_INITIALIZED; + g_elog_statep->elog_initialized = ELOG_INITIALIZED; /* Load the log from flash and prepare the flash if necessary. */ if (elog_scan_flash() < 0 && elog_prepare_empty() < 0) { @@ -796,8 +840,8 @@ } printk(BIOS_INFO, "ELOG: area is %zu bytes, full threshold %d," - " shrink size %d\n", region_device_sz(&nv_dev), - full_threshold, shrink_size); + " shrink size %d\n", region_device_sz(&g_elog_statep->nv_dev), + g_elog_statep->full_threshold, g_elog_statep->shrink_size); if (elog_do_add_boot_count()) { elog_add_event_dword(ELOG_TYPE_BOOT, boot_count_read()); -- To view, visit https://review.coreboot.org/29541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I62792c0f5063c89ad11b512f1777c7ab8a2c13e5 Gerrit-Change-Number: 29541 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org>

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Change in coreboot[master]: soc/intel/common: Call EC _PTS/_WAK methods if defined
by Patrick Georgi (Code Review) 07 Nov '18

07 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/29487 ) Change subject: soc/intel/common: Call EC _PTS/_WAK methods if defined ...................................................................... Patch Set 2: > Patch Set 2: > > That seems to be the difference. How do we get the jenkins builders to run "make iasl"? Ordinarily by pinging Martin and Philip so they update the containers on the build machines that they maintain. -- To view, visit https://review.coreboot.org/29487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10 Gerrit-Change-Number: 29487 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Wed, 07 Nov 2018 22:02:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST
by Nick Vaccaro (Code Review) 07 Nov '18

07 Nov '18

Hello Caveh Jalali, Duncan Laurie, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29538 to look at the new patch set (#2). Change subject: mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST ...................................................................... mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ storm after S3 resume and hence configuring GPP_D9 and GPP_D10 to use PLTRST. BUG=b:119202293 TEST=none Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/29538/2 -- To view, visit https://review.coreboot.org/29538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43 Gerrit-Change-Number: 29538 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variant/atlas: config GPP_F10 to use PLTRST
by Furquan Shaikh (Code Review) 07 Nov '18

07 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29540 ) Change subject: mb/google/poppy/variant/atlas: config GPP_F10 to use PLTRST ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idc6c42cb4dc6e8eb368d605c83f584f4c69077dc Gerrit-Change-Number: 29540 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 07 Nov 2018 21:22:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variant/atlas: config GPP_F10 to use PLTRST
by Nick Vaccaro (Code Review) 07 Nov '18

07 Nov '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/29540 Change subject: mb/google/poppy/variant/atlas: config GPP_F10 to use PLTRST ...................................................................... mb/google/poppy/variant/atlas: config GPP_F10 to use PLTRST GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ storm after S3 resume and hence configuring GPP_F10 (HP_IRQ_GPIO) to use PLTRST. BUG=none TEST=none Change-Id: Idc6c42cb4dc6e8eb368d605c83f584f4c69077dc Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/atlas/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29540/1 diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index 58f7fc5..02c145c 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -273,7 +273,7 @@ /* F9 : I2C4_SCL ==> PCH_I2C4_AUDIO_1V8_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* F10 : I2C5_SDA ==> HP_IRQ_GPIO */ - PAD_CFG_GPI_APIC(GPP_F10, 20K_PU, DEEP), + PAD_CFG_GPI_APIC(GPP_F10, 20K_PU, PLTRST), /* F11 : I2C5_SCL ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_F11, 1, RSMRST), /* F12 : EMMC_CMD */ -- To view, visit https://review.coreboot.org/29540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idc6c42cb4dc6e8eb368d605c83f584f4c69077dc Gerrit-Change-Number: 29540 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: mb/google/sarien: Set runtime IRQs to reset on PLTRST
by Furquan Shaikh (Code Review) 07 Nov '18

07 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29539 ) Change subject: mb/google/sarien: Set runtime IRQs to reset on PLTRST ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f Gerrit-Change-Number: 29539 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 07 Nov 2018 21:00:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/sarien: Set runtime IRQs to reset on PLTRST
by Duncan Laurie (Code Review) 07 Nov '18

07 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29539 Change subject: mb/google/sarien: Set runtime IRQs to reset on PLTRST ...................................................................... mb/google/sarien: Set runtime IRQs to reset on PLTRST GPIOs that use GPI_APIC setting with DEEP can cause an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ strom after S3 resume. For sarien/arcada these are all runtime IRQs only, not wake capable. Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 2 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/29539/1 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index eb4ee76..91ff089 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -46,7 +46,7 @@ /* CORE_VID0 */ /* CORE_VID1 */ /* VRALERT# */ PAD_NC(GPP_B2, NONE), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP, +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), @@ -93,10 +93,10 @@ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* UART2_RTS# */ PAD_NC(GPP_C22, NONE), -/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, +/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TS_INT# */ -/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, DEEP, +/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ /* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */ @@ -117,7 +117,7 @@ /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ /* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ -/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP, +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ /* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), /* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), @@ -232,7 +232,7 @@ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ -/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP, +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 690af1f..31b42ef 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -46,7 +46,7 @@ /* CORE_VID0 */ /* CORE_VID1 */ /* VRALERT# */ PAD_NC(GPP_B2, NONE), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP, +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */ /* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), @@ -63,7 +63,7 @@ /* GSPI0_CLK */ PAD_NC(GPP_B16, NONE), /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), -/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, DEEP, +/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, PLTRST, EDGE_SINGLE, INVERT), /* HDD_FALL_INT */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ @@ -94,10 +94,10 @@ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* UART2_RTS# */ PAD_NC(GPP_C22, NONE), -/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, +/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, EDGE_SINGLE, INVERT), /* TS_INT# */ -/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, DEEP, +/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ /* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* SPI1_MISO */ PAD_NC(GPP_D2, NONE), @@ -116,7 +116,7 @@ /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */ /* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */ -/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP, +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ /* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), /* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), @@ -143,7 +143,7 @@ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, DEEP, +/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT), /* FFS_INT2 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), @@ -232,7 +232,7 @@ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ -/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP, +/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ -- To view, visit https://review.coreboot.org/29539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f Gerrit-Change-Number: 29539 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: drivers/intel/fsp2_0: Run SplitFspBin with python2
by Nico Huber (Code Review) 07 Nov '18

07 Nov '18

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/29519 ) Change subject: drivers/intel/fsp2_0: Run SplitFspBin with python2 ...................................................................... drivers/intel/fsp2_0: Run SplitFspBin with python2 It's not Python 3 compatible. Change-Id: Ibaad2c31bb6494652ce650ab7c1064728ec5fe80 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/29519 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/drivers/intel/fsp2_0/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 0bfe90d..79fe5f8 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -69,7 +69,7 @@ ifeq ($(CONFIG_FSP_USE_REPO),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) - python 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" + python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" $(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd true -- To view, visit https://review.coreboot.org/29519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ibaad2c31bb6494652ce650ab7c1064728ec5fe80 Gerrit-Change-Number: 29519 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST
by Furquan Shaikh (Code Review) 07 Nov '18

07 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29538 ) Change subject: mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43 Gerrit-Change-Number: 29538 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 07 Nov 2018 20:40:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit November 2018