coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

1 participants
1699 discussions

Change in coreboot[master]: drivers/*/tpm: Add postcar target
by Philipp Deppenwiese (Code Review) 08 Nov '18

08 Nov '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29546 Change subject: drivers/*/tpm: Add postcar target ...................................................................... drivers/*/tpm: Add postcar target Now postcar is a standalone stage, add it as target to all TPM bus drivers. This is a required for a measured boot. Change-Id: I758185daf3941a29883c2256b900360e112275e1 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/drivers/i2c/tpm/Makefile.inc M src/drivers/pc80/tpm/Makefile.inc M src/drivers/spi/tpm/Makefile.inc 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/29546/1 diff --git a/src/drivers/i2c/tpm/Makefile.inc b/src/drivers/i2c/tpm/Makefile.inc index e24a66d..51856fa 100644 --- a/src/drivers/i2c/tpm/Makefile.inc +++ b/src/drivers/i2c/tpm/Makefile.inc @@ -2,20 +2,24 @@ romstage-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c verstage-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c bootblock-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c +postcar-$(CONFIG_DRIVER_TIS_DEFAULT) += tis.c ramstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL) += tis_atmel.c romstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL) += tis_atmel.c verstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL) += tis_atmel.c bootblock-$(CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL) += tis_atmel.c +postcar-$(CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL) += tis_atmel.c ramstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC) += tpm.c romstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC) += tpm.c verstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC) += tpm.c bootblock-$(CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC) += tpm.c +postcar-$(CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC) += tpm.c ramstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c romstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c verstage-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c bootblock-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c +postcar-$(CONFIG_MAINBOARD_HAS_I2C_TPM_CR50) += cr50.c ramstage-$(CONFIG_DRIVER_I2C_TPM_ACPI) += chip.c diff --git a/src/drivers/pc80/tpm/Makefile.inc b/src/drivers/pc80/tpm/Makefile.inc index 8747374..0de1b76 100644 --- a/src/drivers/pc80/tpm/Makefile.inc +++ b/src/drivers/pc80/tpm/Makefile.inc @@ -1,3 +1,4 @@ verstage-$(CONFIG_LPC_TPM) += tis.c romstage-$(CONFIG_LPC_TPM) += tis.c ramstage-$(CONFIG_LPC_TPM) += tis.c +postcar-$(CONFIG_LPC_TPM) += tis.c diff --git a/src/drivers/spi/tpm/Makefile.inc b/src/drivers/spi/tpm/Makefile.inc index fd214c6..01d3b66 100644 --- a/src/drivers/spi/tpm/Makefile.inc +++ b/src/drivers/spi/tpm/Makefile.inc @@ -2,3 +2,4 @@ verstage-$(CONFIG_SPI_TPM) += tis.c tpm.c romstage-$(CONFIG_SPI_TPM) += tis.c tpm.c ramstage-$(CONFIG_SPI_TPM) += tis.c tpm.c +postcar-$(CONFIG_SPI_TPM) += tis.c tpm.c -- To view, visit https://review.coreboot.org/29546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I758185daf3941a29883c2256b900360e112275e1 Gerrit-Change-Number: 29546 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

1 0

Change in coreboot[master]: include/program_loading: Add POSTCAR prog type
by Philipp Deppenwiese (Code Review) 08 Nov '18

08 Nov '18

Philipp Deppenwiese has removed Rizwan Qureshi from this change. ( https://review.coreboot.org/29545 ) Change subject: include/program_loading: Add POSTCAR prog type ...................................................................... Removed reviewer Rizwan Qureshi. -- To view, visit https://review.coreboot.org/29545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: deleteReviewer Gerrit-Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Gerrit-Change-Number: 29545 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: include/program_loading: Add POSTCAR prog type
by Philipp Deppenwiese (Code Review) 08 Nov '18

08 Nov '18

Philipp Deppenwiese has uploaded a new patch set (#2). ( https://review.coreboot.org/29545 ) Change subject: include/program_loading: Add POSTCAR prog type ...................................................................... include/program_loading: Add POSTCAR prog type Now postcar is a standalone stage give it a proper type. Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/arch/x86/postcar_loader.c M src/include/program_loading.h 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29545/2 -- To view, visit https://review.coreboot.org/29545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Gerrit-Change-Number: 29545 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

1 0

Change in coreboot[master]: include/program_loading: Add POSTCAR prog type
by Philipp Deppenwiese (Code Review) 08 Nov '18

08 Nov '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29545 Change subject: include/program_loading: Add POSTCAR prog type ...................................................................... include/program_loading: Add POSTCAR prog type Now postcar is a standalone stage give it a proper type Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Signed-off-by: zaolin <zaolin.daisuki(a)gmail.com> --- M src/arch/x86/postcar_loader.c M src/include/program_loading.h 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29545/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 1877108..2342fb9 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -167,7 +167,7 @@ void run_postcar_phase(struct postcar_frame *pcf) { struct prog prog = - PROG_INIT(PROG_UNKNOWN, CONFIG_CBFS_PREFIX "/postcar"); + PROG_INIT(PROG_POSTCAR, CONFIG_CBFS_PREFIX "/postcar"); postcar_commit_mtrrs(pcf); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index e185b92..26d0295 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -32,6 +32,7 @@ PROG_VERSTAGE, PROG_ROMSTAGE, PROG_RAMSTAGE, + PROG_POSTCAR, PROG_REFCODE, PROG_PAYLOAD, PROG_BL31, -- To view, visit https://review.coreboot.org/29545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Gerrit-Change-Number: 29545 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

1 0

Change in coreboot[master]: soc/intel/skylake: Drop FSP_CAR options
by Arthur Heymans (Code Review) 08 Nov '18

08 Nov '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/29533 ) Change subject: soc/intel/skylake: Drop FSP_CAR options ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28 Gerrit-Change-Number: 29533 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 09:17:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: security/vboot: Add VB2_LIB to postcar stage if available
by Philipp Deppenwiese (Code Review) 08 Nov '18

08 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29465 ) Change subject: security/vboot: Add VB2_LIB to postcar stage if available ...................................................................... security/vboot: Add VB2_LIB to postcar stage if available VB2_LIB will be used across all stages to hash data. Add it to postcar stage sources so that it is compiled if postcar exists. In this way the new function tpm_measure_region() introduced in commit 61322d7 (security/tpm: Add function to measure a region device) can be used in every stage. Change-Id: I933d33b0188d1b123bb4735722b6086e7786624f Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/29465 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/security/vboot/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Julius Werner: Looks good to me, approved diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 704b6c9..f51db80 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -112,6 +112,7 @@ $(eval $(call vboot-for-stage,verstage)) $(eval $(call vboot-for-stage,bootblock)) $(eval $(call vboot-for-stage,ramstage)) +$(eval $(call vboot-for-stage,postcar)) ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y) -- To view, visit https://review.coreboot.org/29465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I933d33b0188d1b123bb4735722b6086e7786624f Gerrit-Change-Number: 29465 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: toolchain: Add POSTCAR as a stage we have a toolchain for
by Philipp Deppenwiese (Code Review) 08 Nov '18

08 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29395 ) Change subject: toolchain: Add POSTCAR as a stage we have a toolchain for ...................................................................... toolchain: Add POSTCAR as a stage we have a toolchain for Fixes building vb2lib for postcar. Since postcar is an x86ism, add the Kconfig options only for x86. Change-Id: Ib92436bc7270c24689dcf01a47f0c6fe7661814b Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/29395 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Julius Werner: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index ff26a15..7c8371e 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -35,6 +35,10 @@ bool default n +config ARCH_POSTCAR_X86_32 + bool + default ARCH_ROMSTAGE_X86_32 && POSTCAR_STAGE + config ARCH_RAMSTAGE_X86_32 bool default n @@ -55,6 +59,10 @@ bool default n +config ARCH_POSTCAR_X86_64 + bool + default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE + config ARCH_RAMSTAGE_X86_64 bool default n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 730bc83..fcc57c5 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -16,6 +16,10 @@ ## GNU General Public License for more details. ## +ifeq ($(CONFIG_POSTCAR_STAGE),y) +$(eval $(call init_standard_toolchain,postcar)) +endif + ################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool -- To view, visit https://review.coreboot.org/29395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ib92436bc7270c24689dcf01a47f0c6fe7661814b Gerrit-Change-Number: 29395 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org>

1 0

Change in coreboot[master]: security/vboot: Add VB2_LIB to postcar stage if available
by Philipp Deppenwiese (Code Review) 08 Nov '18

08 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29465 ) Change subject: security/vboot: Add VB2_LIB to postcar stage if available ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/29465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I933d33b0188d1b123bb4735722b6086e7786624f Gerrit-Change-Number: 29465 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 07:41:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/poppy/variant/atlas: config GPP_F10 to use PLTRST
by caveh jalali (Code Review) 08 Nov '18

08 Nov '18

caveh jalali has posted comments on this change. ( https://review.coreboot.org/29540 ) Change subject: mb/google/poppy/variant/atlas: config GPP_F10 to use PLTRST ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/29540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idc6c42cb4dc6e8eb368d605c83f584f4c69077dc Gerrit-Change-Number: 29540 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 07:36:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/lenovo/*/dsdt: Rearrange defines
by Peter Lemenkov (Code Review) 08 Nov '18

08 Nov '18

Peter Lemenkov has uploaded a new patch set (#2). ( https://review.coreboot.org/29544 ) Change subject: mb/lenovo/*/dsdt: Rearrange defines ...................................................................... mb/lenovo/*/dsdt: Rearrange defines Sort mainboard-specific defines in the same order as in all other Lenovo boards. This is a purely cosmetic change which just makes diff between boards smaller. Change-Id: I4e379bb727b356fc6010e93de492f6d73f97a750 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/l520/dsdt.asl M src/mainboard/lenovo/s230u/dsdt.asl 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/29544/2 -- To view, visit https://review.coreboot.org/29544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4e379bb727b356fc6010e93de492f6d73f97a750 Gerrit-Change-Number: 29544 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2018