coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: security/vboot: Add selection for firmware slots used by VBOOT
by Philipp Deppenwiese (Code Review) 08 Nov '18

08 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/27714 ) Change subject: security/vboot: Add selection for firmware slots used by VBOOT ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/27714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I278fc060522b13048b00090b8e5261c14496f56e Gerrit-Change-Number: 27714 Gerrit-PatchSet: 8 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 08 Nov 2018 16:16:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
by Mario Scheithauer (Code Review) 08 Nov '18

08 Nov '18

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/29549 ) Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29549/4/src/mainboard/siemens/mc_apl1/varia… File src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c: https://review.coreboot.org/#/c/29549/4/src/mainboard/siemens/mc_apl1/varia… PS4, Line 73: dev->bus->dev->device > So do you need dev->bus->dev->device or dev->device which is used in the upper case? In the above case, I set the parent device before the if instruction to dev object (line 64). Because of the 80 character rule, the if instruction is then better readable. In the second case, I don't take the intermediate step. -- To view, visit https://review.coreboot.org/29549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Gerrit-Change-Number: 29549 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 15:40:50 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
by Werner Zeh (Code Review) 08 Nov '18

08 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29549 ) Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29549/4/src/mainboard/siemens/mc_apl1/varia… File src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c: https://review.coreboot.org/#/c/29549/4/src/mainboard/siemens/mc_apl1/varia… PS4, Line 73: dev->bus->dev->device So do you need dev->bus->dev->device or dev->device which is used in the upper case? -- To view, visit https://review.coreboot.org/29549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Gerrit-Change-Number: 29549 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 15:18:28 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: include/program_loading: Add POSTCAR prog type
by Werner Zeh (Code Review) 08 Nov '18

08 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29545 ) Change subject: include/program_loading: Add POSTCAR prog type ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/29545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Gerrit-Change-Number: 29545 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 14:00:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/*/tpm: Add postcar target
by Werner Zeh (Code Review) 08 Nov '18

08 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29546 ) Change subject: drivers/*/tpm: Add postcar target ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/29546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I758185daf3941a29883c2256b900360e112275e1 Gerrit-Change-Number: 29546 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 13:59:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/vboot: Add measured boot mode
by Werner Zeh (Code Review) 08 Nov '18

08 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29547 ) Change subject: security/vboot: Add measured boot mode ...................................................................... Patch Set 3: (7 comments) https://review.coreboot.org/#/c/29547/3/src/security/vboot/vboot_crtm.c File src/security/vboot/vboot_crtm.c: https://review.coreboot.org/#/c/29547/3/src/security/vboot/vboot_crtm.c@33 PS3, Line 33: if (cbfs_boot_locate(&bootblock_data, : prog_name(&bootblock), : NULL) : == 0) { That formating looks weird...Either move "==0" to the prior line or use: if (!cbfs_boot_locate(&bootblock_data, prog_name(&bootblock), NULL)) { https://review.coreboot.org/#/c/29547/3/src/security/vboot/vboot_crtm.c@41 PS3, Line 41: "bootblock" Use prog_name(&bootblock) here, too? https://review.coreboot.org/#/c/29547/3/src/security/vboot/vboot_crtm.c@45 PS3, Line 45: fmap This is still the bootblock, right? call it bb_fmap or so for better readability? https://review.coreboot.org/#/c/29547/3/src/security/vboot/vboot_crtm.c@52 PS3, Line 52: printk(BIOS_INFO, : "VBOOT: Couldn't measure %s into CRTM!", : "bootblock"); Do we need this printk for struct prog bootblock, too? We will have an error print friven from tpm_measure_region(), maybe this is already sufficient? https://review.coreboot.org/#/c/29547/3/src/security/vboot/vboot_crtm.c@69 PS3, Line 69: / Why the slash here? https://review.coreboot.org/#/c/29547/3/src/security/vboot/vboot_crtm.c@83 PS3, Line 83: if (cbfs_boot_locate(&verstage_data, prog_name(&verstage), : NULL) : == 0) { Formating again. https://review.coreboot.org/#/c/29547/3/src/security/vboot/vboot_crtm.c@91 PS3, Line 91: / Why the slash here? -- To view, visit https://review.coreboot.org/29547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Gerrit-Change-Number: 29547 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 13:57:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
by Mario Scheithauer (Code Review) 08 Nov '18

08 Nov '18

Hello Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29549 to look at the new patch set (#4). Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges ...................................................................... siemens/mc_apl3: Disable PCI clock outputs on XIO bridges On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c 1 file changed, 14 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29549/4 -- To view, visit https://review.coreboot.org/29549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Gerrit-Change-Number: 29549 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
by Mario Scheithauer (Code Review) 08 Nov '18

08 Nov '18

Hello Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29549 to look at the new patch set (#3). Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges ...................................................................... siemens/mc_apl3: Disable PCI clock outputs on XIO bridges On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c 1 file changed, 14 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29549/3 -- To view, visit https://review.coreboot.org/29549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Gerrit-Change-Number: 29549 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
by Mario Scheithauer (Code Review) 08 Nov '18

08 Nov '18

Hello Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29549 to look at the new patch set (#2). Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges ...................................................................... siemens/mc_apl3: Disable PCI clock outputs on XIO bridges On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c 1 file changed, 13 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29549/2 -- To view, visit https://review.coreboot.org/29549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Gerrit-Change-Number: 29549 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
by Mario Scheithauer (Code Review) 08 Nov '18

08 Nov '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29549 Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges ...................................................................... siemens/mc_apl3: Disable PCI clock outputs on XIO bridges On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c 1 file changed, 13 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29549/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index 3a87a4f..a271620 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -40,11 +40,6 @@ */ pcr_write16(PID_ITSS, 0x314c, 0x2103); - /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ - dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); - if (dev) - pci_write_config8(dev, 0xd8, 0x3e); - /* Enable CLKRUN_EN for power gating LPC */ lpc_enable_pci_clk_cntl(); @@ -62,8 +57,21 @@ cmd = pci_read_config16(dev, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); + + /* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream + * XIO2001 PCIe to PCI Bridge. + */ + if (dev->bus->dev) + pci_write_config8(dev->bus->dev, 0xd8, 0x1d); } + /* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI + * Bridge on this mainboard. + */ + dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); + if (dev->bus->dev) + pci_write_config8(dev->bus->dev, 0xd8, 0x3c); + /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). * When Bit 3 is set to 1 and then the reset button is pressed the PCH * will drive SLP_S3 active (low). SLP_S3 is then used on the mainboard -- To view, visit https://review.coreboot.org/29549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Gerrit-Change-Number: 29549 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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coreboot-gerrit November 2018