coreboot-gerrit November 2018

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Change in coreboot[master]: azalia: Add Azalia Reset macro
by build bot (Jenkins) (Code Review) 09 Nov '18

09 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29554 ) Change subject: azalia: Add Azalia Reset macro ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/29554/5/src/include/device/azalia_device.h File src/include/device/azalia_device.h: https://review.coreboot.org/#/c/29554/5/src/include/device/azalia_device.h@… PS5, Line 50: #define AZALIA_RESET(pin) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/29554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Gerrit-Change-Number: 29554 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Nov 2018 02:57:36 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: azalia: Add Azalia Reset macro
by Lijian Zhao (Code Review) 09 Nov '18

09 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29554 to look at the new patch set (#5). Change subject: azalia: Add Azalia Reset macro ...................................................................... azalia: Add Azalia Reset macro Provide an reset macro that will use Verb ID 0x7ff and Payload 0 to execute function reset. Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/include/device/azalia_device.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29554/5 -- To view, visit https://review.coreboot.org/29554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Gerrit-Change-Number: 29554 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: azalia: Add Azalia Reset macro
by Lijian Zhao (Code Review) 09 Nov '18

09 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29554 to look at the new patch set (#4). Change subject: azalia: Add Azalia Reset macro ...................................................................... azalia: Add Azalia Reset macro Provide an reset macro that will use Verb ID 0x7ff and Payload 0 to execute function reset. Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/include/device/azalia_device.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29554/4 -- To view, visit https://review.coreboot.org/29554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Gerrit-Change-Number: 29554 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: azalia: Add Azalia Reset macro
by Lijian Zhao (Code Review) 09 Nov '18

09 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29554 to look at the new patch set (#3). Change subject: azalia: Add Azalia Reset macro ...................................................................... azalia: Add Azalia Reset macro Provide an reset macro that will use Verb ID 0x7ff and Payload 0 to execute function reset. Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/include/device/azalia_device.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29554/3 -- To view, visit https://review.coreboot.org/29554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Gerrit-Change-Number: 29554 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: azalia: Add Azalia reset macro
by Lijian Zhao (Code Review) 09 Nov '18

09 Nov '18

Lijian Zhao has uploaded a new patch set (#2). ( https://review.coreboot.org/29554 ) Change subject: azalia: Add Azalia reset macro ...................................................................... azalia: Add Azalia reset macro Provide an reset macro that will use Verb ID 0x7ff and Payload 0 to execute function reset. Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/include/device/azalia_device.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29554/2 -- To view, visit https://review.coreboot.org/29554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Gerrit-Change-Number: 29554 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: azalia: Add Azalia reset macro
by Lijian Zhao (Code Review) 09 Nov '18

09 Nov '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/29554 Change subject: azalia: Add Azalia reset macro ...................................................................... azalia: Add Azalia reset macro Provide an reset macro that will use Verb ID 0x7ff and Payload 0 to execute function reset. Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/include/device/azalia_device.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29554/1 diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 53aad97..a6fb089 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -47,6 +47,10 @@ (((codec) << 28) | ((pin) << 20) | (0x71f << 8) \ | (((val) >> 24) & 0xff)) +#define AZALIA_RESET(codec) \ + ((((codec) << 28) | 0x017ff00), (((codec) << 28) | 0x017ff00), \ + (((codec) << 28) | 0x017ff00), (((codec) << 28) | 0x017ff00)) + #define AZALIA_SUBVENDOR(codec, val) \ (((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)), \ (((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff)), \ -- To view, visit https://review.coreboot.org/29554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36 Gerrit-Change-Number: 29554 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz
by Caveh Jalali (Code Review) 09 Nov '18

09 Nov '18

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/29553 ) Change subject: mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/29553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38 Gerrit-Change-Number: 29553 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Fri, 09 Nov 2018 01:54:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/sarien: Program HD Audio SVID/SSID
by build bot (Jenkins) (Code Review) 08 Nov '18

08 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29492 ) Change subject: mb/google/sarien: Program HD Audio SVID/SSID ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/#/c/29492/6/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h: https://review.coreboot.org/#/c/29492/6/src/mainboard/google/sarien/variant… PS6, Line 25: {{{PCI_SUBSYSTEM_VENDOR_ID, HDA_FUNC, PCH_DEV_SLOT_LPC, 0, 0, 0, 0 }}, space required after that close brace '}' https://review.coreboot.org/#/c/29492/6/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h: https://review.coreboot.org/#/c/29492/6/src/mainboard/google/sarien/variant… PS6, Line 25: {{{PCI_SUBSYSTEM_VENDOR_ID, HDA_FUNC, PCH_DEV_SLOT_LPC, 0, 0, 0, 0 }}, space required after that close brace '}' -- To view, visit https://review.coreboot.org/29492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3c08da2daf8539864ea3f9aa04ccf488e2844da5 Gerrit-Change-Number: 29492 Gerrit-PatchSet: 6 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 23:39:01 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/sarien: Program HD Audio SVID/SSID
by build bot (Jenkins) (Code Review) 08 Nov '18

08 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29492 ) Change subject: mb/google/sarien: Program HD Audio SVID/SSID ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/29492/5/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h: https://review.coreboot.org/#/c/29492/5/src/mainboard/google/sarien/variant… PS5, Line 25: {{{PCI_SUBSYSTEM_VENDOR_ID, HDA_FUNC, PCH_DEV_SLOT_LPC, 0, 0, 0, 0 }}, space required after that close brace '}' https://review.coreboot.org/#/c/29492/5/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h: https://review.coreboot.org/#/c/29492/5/src/mainboard/google/sarien/variant… PS5, Line 25: {{{PCI_SUBSYSTEM_VENDOR_ID, HDA_FUNC, PCH_DEV_SLOT_LPC, 0, 0, 0, 0 }}, space required after that close brace '}' -- To view, visit https://review.coreboot.org/29492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3c08da2daf8539864ea3f9aa04ccf488e2844da5 Gerrit-Change-Number: 29492 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 23:22:21 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/cannonlake: Remove SmbusEnable
by Duncan Laurie (Code Review) 08 Nov '18

08 Nov '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29552 Change subject: soc/intel/cannonlake: Remove SmbusEnable ...................................................................... soc/intel/cannonlake: Remove SmbusEnable Remove the SmbusEnable config option from devicetree and instead use the state of the PCI device to determine if it should be enabled or disabled. Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29552/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 2deb35f..015133e 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -166,9 +166,6 @@ * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; - /* SMBus */ - uint8_t SmbusEnable; - /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; /* Need to update DLL setting to get Emmc running at HS400 speed */ diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 8506214..8f6fa2f 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -66,6 +66,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS); assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; @@ -73,7 +74,10 @@ soc_memory_init_params(m_cfg, config); /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; + if (!smbus) + m_cfg->SmbusEnable = 0; + else + m_cfg->SmbusEnable = smbus->enabled; /* Set debug probe type */ m_cfg->PlatformDebugConsent = config->DebugConsent; -- To view, visit https://review.coreboot.org/29552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a Gerrit-Change-Number: 29552 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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coreboot-gerrit November 2018