coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

1 participants
1699 discussions

Change in coreboot[master]: include/program_loading: Add POSTCAR prog type
by Philipp Deppenwiese (Code Review) 09 Nov '18

09 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29545 ) Change subject: include/program_loading: Add POSTCAR prog type ...................................................................... include/program_loading: Add POSTCAR prog type Now postcar is a standalone stage give it a proper type. Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-on: https://review.coreboot.org/29545 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/arch/x86/postcar_loader.c M src/include/program_loading.h 2 files changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 1877108..2342fb9 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -167,7 +167,7 @@ void run_postcar_phase(struct postcar_frame *pcf) { struct prog prog = - PROG_INIT(PROG_UNKNOWN, CONFIG_CBFS_PREFIX "/postcar"); + PROG_INIT(PROG_POSTCAR, CONFIG_CBFS_PREFIX "/postcar"); postcar_commit_mtrrs(pcf); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index e185b92..468f0b3 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -36,6 +36,7 @@ PROG_PAYLOAD, PROG_BL31, PROG_BL32, + PROG_POSTCAR, }; /* -- To view, visit https://review.coreboot.org/29545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Gerrit-Change-Number: 29545 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: cpu/intel/speedstep: Add Netburst CPUs
by build bot (Jenkins) (Code Review) 09 Nov '18

09 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22604 ) Change subject: cpu/intel/speedstep: Add Netburst CPUs ...................................................................... Patch Set 30: (1 comment) https://review.coreboot.org/#/c/22604/30/src/cpu/intel/speedstep/speedstep.c File src/cpu/intel/speedstep/speedstep.c: https://review.coreboot.org/#/c/22604/30/src/cpu/intel/speedstep/speedstep.… PS30, Line 43: if (cpu_id >= 0x60 && cpu_id < 0xf0) Statements should start on a tabstop -- To view, visit https://review.coreboot.org/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 30 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Fri, 09 Nov 2018 10:28:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: siemens/mc_apl4: Enable SDCARD
by Mario Scheithauer (Code Review) 09 Nov '18

09 Nov '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29561 Change subject: siemens/mc_apl4: Enable SDCARD ...................................................................... siemens/mc_apl4: Enable SDCARD This mainboard also has a SD slot. Change-Id: Id56bc1be60ec8c2be0e5543d1d8851610b7248e0 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/29561/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index d03623a..2562bf6 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -84,7 +84,7 @@ device pci 19.1 off end # - SPI 1 device pci 19.2 off end # - SPI 2 device pci 1a.0 off end # - PWM - device pci 1b.0 off end # - SDCARD + device pci 1b.0 on end # - SDCARD device pci 1c.0 on end # - eMMC device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO -- To view, visit https://review.coreboot.org/29561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id56bc1be60ec8c2be0e5543d1d8851610b7248e0 Gerrit-Change-Number: 29561 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

1 0

Change in coreboot[master]: siemens/mc_apl4: Remove external RTC from I2C0
by Mario Scheithauer (Code Review) 09 Nov '18

09 Nov '18

Hello Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29560 to look at the new patch set (#2). Change subject: siemens/mc_apl4: Remove external RTC from I2C0 ...................................................................... siemens/mc_apl4: Remove external RTC from I2C0 This mainboard also has an external RTC chip, but not on this bus. The topic is currently in clarification and will be published with a later patch. In a first step we enable all I2C busses. Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb 1 file changed, 7 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/29560/2 -- To view, visit https://review.coreboot.org/29560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00 Gerrit-Change-Number: 29560 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: siemens/mc_apl4: Enable all PCIe root ports
by Werner Zeh (Code Review) 09 Nov '18

09 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29559 ) Change subject: siemens/mc_apl4: Enable all PCIe root ports ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7f6feb2f0d4c45f32d9454838e67e1a244b2712b Gerrit-Change-Number: 29559 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Nov 2018 09:45:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: siemens/mc_apl4: Remove reduced clock rate for I2C0
by Werner Zeh (Code Review) 09 Nov '18

09 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29558 ) Change subject: siemens/mc_apl4: Remove reduced clock rate for I2C0 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib7c4e3251545b2d32368dd56206e3b4844a24800 Gerrit-Change-Number: 29558 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Nov 2018 09:42:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: siemens/mc_apl4: Remove external RTC from I2C0
by Mario Scheithauer (Code Review) 09 Nov '18

09 Nov '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29560 Change subject: siemens/mc_apl4: Remove external RTC from I2C0 ...................................................................... siemens/mc_apl4: Remove external RTC from I2C0 This mainboard also has an external RTC chip, but not on this bus. The topic is currently in clarification and will be published with a later patch. Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb 1 file changed, 1 insertion(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/29560/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 61e8c71..1b50150 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -68,21 +68,7 @@ device pci 14.1 on end # - RP 1 - PCIe-B 1 device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI - device pci 16.0 on # - I2C 0 - # Enable external RTC chip - chip drivers/i2c/rx6110sa - register "pmon_sampling" = "PMON_SAMPL_256_MS" - register "bks_on" = "0" - register "bks_off" = "1" - register "iocut_en" = "1" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" - register "user_weekday" = "4" - device i2c 0x32 on end # RTC RX6110 SA - end - end + device pci 16.0 off end # - I2C 0 device pci 16.1 off end # - I2C 1 device pci 16.2 off end # - I2C 2 device pci 16.3 off end # - I2C 3 -- To view, visit https://review.coreboot.org/29560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00 Gerrit-Change-Number: 29560 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

1 0

Change in coreboot[master]: siemens/mc_apl4: Enable all PCIe root ports
by Mario Scheithauer (Code Review) 09 Nov '18

09 Nov '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29559 Change subject: siemens/mc_apl4: Enable all PCIe root ports ...................................................................... siemens/mc_apl4: Enable all PCIe root ports Enable all PCIe root ports for this mainboard. Change-Id: I7f6feb2f0d4c45f32d9454838e67e1a244b2712b Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/29559/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 8c219af..61e8c71 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -60,12 +60,12 @@ device pci 0e.0 off end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA - device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY - device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY - device pci 13.2 off end # - RP 4 - PCIe-A 2 - device pci 13.3 off end # - RP 5 - PCIe-A 3 - device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge - device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA + device pci 13.0 on end # - RP 2 - PCIe A 0 + device pci 13.1 on end # - RP 3 - PCIe A 1 + device pci 13.2 on end # - RP 4 - PCIe-A 2 + device pci 13.3 on end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 + device pci 14.1 on end # - RP 1 - PCIe-B 1 device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on # - I2C 0 -- To view, visit https://review.coreboot.org/29559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7f6feb2f0d4c45f32d9454838e67e1a244b2712b Gerrit-Change-Number: 29559 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

1 0

Change in coreboot[master]: siemens/mc_apl4: Remove reduced clock rate for I2C0
by Mario Scheithauer (Code Review) 09 Nov '18

09 Nov '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29558 Change subject: siemens/mc_apl4: Remove reduced clock rate for I2C0 ...................................................................... siemens/mc_apl4: Remove reduced clock rate for I2C0 There is no device on I2C0 which requires a lower clock rate. Change-Id: Ib7c4e3251545b2d32368dd56206e3b4844a24800 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb 1 file changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29558/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index a2a2ba1..8c219af 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -47,18 +47,6 @@ # 0:HS400(Default), 1:HS200, 2:DDR50 register "emmc_host_max_speed" = "2" - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| I2C0 | Proximity Sensor | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .i2c[0] = { - .speed = I2C_SPEED_STANDARD - }, - }" - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 off end # - DPTF -- To view, visit https://review.coreboot.org/29558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib7c4e3251545b2d32368dd56206e3b4844a24800 Gerrit-Change-Number: 29558 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

1 0

Change in coreboot[master]: google/grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number
by Kevin Chiu (Code Review) 09 Nov '18

09 Nov '18

Hello Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29557 to look at the new patch set (#2). Change subject: google/grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number ...................................................................... google/grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number Correct SPD Module Part Number to "K4A8G165WC-BCTD" from "M471A5244CB0-CTD". BUG=none BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage mosys memory spd print all 0 | DDR4 | SO-DIMM 0 | 1-78: Samsung | 00000000 | K4A8G165WC-BCTD 0 | 4096 | 1 | 64 0 | DDR4-1333, DDR4-1600, DDR4-2400 Change-Id: I29505d3eece2283579499a0afc424c4a28017fa5 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29557/2 -- To view, visit https://review.coreboot.org/29557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I29505d3eece2283579499a0afc424c4a28017fa5 Gerrit-Change-Number: 29557 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2018