Hello Gaggery Tsai, caveh jalali, Duncan Laurie, Gaggery Tsai, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29553
to look at the new patch set (#2).
Change subject: mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz
......................................................................
mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz
With this change, coreboot thinks we're running at 1MHz:
DW I2C bus 2 at 0xd1133000 (1000 KHz)
Elan eKT3644 IC Specification (trackpad) requires:
Low Time larger than 500ns (61 * 8.3ns = 506ns).
High Time larger than 260ns (32 * 8.3ns = 265ns),
Data Hold_time larger than 0ns (32 * 8.3ns = 265ns).
Start Condition Hold time larger than 250ns.
Rise/Fall time of less than 120ns.
HCNT controls both High Time and Start Condition Hold time.
LCNT controls Low Time.
SDA_HOLD controls Data Hold Time.
P2 Atlas "Rise time" is 90ns and "Fall time" is 32ns and tuned
using resistors on the board and must be considered when
adjusting any of the parameters since these times are all measured
at 30 or 70% of base and peak voltages (0v/1.8v).
The eKT3644 requirements are met with LCNT=69, HCNT=33, SDA_HOLD=20
which yields the SCL at around 950KHz - suboptimal but compliant.
Lower LCNT or HCNT results in "lost arbitration" errors or not complying
with eKT3644 requirements.
Verified by gaggery.tsai(a)intel.corp-partner.google.com.
Scope shots posted here:
https://b.corp.google.com/issues/78601949#comment177
BUG=b:78601949
BRANCH=none
TEST=Farzam provided test points on track pad for SCL/SDA/GND.
Waveforms measured with oscilloscope and screen shots attached
to bug (comment #177, #155, #100).
Operate trackpad/touchscreen
Review dmesg (kernel) output for correct speed, parameters, and
no errors (e.g. "lost arbitration" or "host controller timeout")
Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38
Signed-off-by: Caveh Jalali <caveh(a)chromium.org>
Signed-off-by: Grant Grundler <grundler(a)chromium.org>
Tested-by: gaggery.tsai(a)intel.corp-partner.google.com
Tested-by: grundler(a)chromium.org
---
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
1 file changed, 8 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29553/2
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Gerrit-Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38
Gerrit-Change-Number: 29553
Gerrit-PatchSet: 2
Gerrit-Owner: Caveh Jalali <caveh(a)google.com>
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29554 )
Change subject: azalia: Add Azalia Reset macro
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/29554/6/src/include/device/azalia_device.h
File src/include/device/azalia_device.h:
https://review.coreboot.org/#/c/29554/6/src/include/device/azalia_device.h@…
PS6, Line 50: #define AZALIA_RESET(pin) \
Macros with complex values should be enclosed in parentheses
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Gerrit-Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36
Gerrit-Change-Number: 29554
Gerrit-PatchSet: 6
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Hello Bora Guvendik, build bot (Jenkins), Krzysztof M Sywula,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29554
to look at the new patch set (#6).
Change subject: azalia: Add Azalia Reset macro
......................................................................
azalia: Add Azalia Reset macro
Provide an reset macro that will use Verb ID 0x7ff and Payload 0 to
execute function reset.
Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
---
M src/include/device/azalia_device.h
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29554/6
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/29533 )
Change subject: soc/intel/skylake: Drop FSP_CAR options
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/29533/1/src/soc/intel/skylake/Kconfig
File src/soc/intel/skylake/Kconfig:
https://review.coreboot.org/#/c/29533/1/src/soc/intel/skylake/Kconfig@105
PS1, Line 105: select SKIP_FSP_CAR
> If we want to use FSP_CAR, what is the right config how to set? […]
It's not as easy as toggling a Kconfig. And it's different for FSP1.1
(where we have SKIP_FSP_CAR with the inverse logic) and FSP2.0 (where
we have FSP_CAR).
IIRC, for FSP1.1 the linker gives an error about a conflict with code
from soc/intel/common/. That would have to be fixed, and then we'd
have to remove the `select SKIP_FSP_CAR` here (because you can't over-
ride a select at the mainboard level) and find a better solution.
For FSP2.0 there are symbols missing when FSP_CAR is selected. When
you provide the missing symbols you could `select FSP_CAR` at the
mainboard level.
I'm not a friend of the idea to "select" it at the mainboard level,
though. It would take away the option to use the open-source version
from the person that configures/compiles coreboot. And that seems to
be questionable for an open-source project (what coreboot is about).
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22604 )
Change subject: cpu/intel/speedstep: Add Netburst CPUs
......................................................................
Patch Set 36:
(2 comments)
https://review.coreboot.org/#/c/22604/36/src/cpu/intel/common/fsb.c
File src/cpu/intel/common/fsb.c:
https://review.coreboot.org/#/c/22604/36/src/cpu/intel/common/fsb.c@48
PS36, Line 48: case 0xf: /* Netburst */
Possible switch case/default not preceded by break or fallthrough comment
https://review.coreboot.org/#/c/22604/36/src/cpu/intel/common/fsb.c@62
PS36, Line 62: default:
Possible switch case/default not preceded by break or fallthrough comment
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Change subject: cpu/intel/speedstep: Add Netburst CPUs
......................................................................
Patch Set 35:
(2 comments)
https://review.coreboot.org/#/c/22604/35/src/cpu/intel/common/fsb.c
File src/cpu/intel/common/fsb.c:
https://review.coreboot.org/#/c/22604/35/src/cpu/intel/common/fsb.c@48
PS35, Line 48: case 0xf: /* Netburst */
Possible switch case/default not preceded by break or fallthrough comment
https://review.coreboot.org/#/c/22604/35/src/cpu/intel/common/fsb.c@62
PS35, Line 62: default:
Possible switch case/default not preceded by break or fallthrough comment
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Change subject: cpu/intel/speedstep: Add Netburst CPUs
......................................................................
Patch Set 34:
(2 comments)
https://review.coreboot.org/#/c/22604/34/src/cpu/intel/common/fsb.c
File src/cpu/intel/common/fsb.c:
https://review.coreboot.org/#/c/22604/34/src/cpu/intel/common/fsb.c@48
PS34, Line 48: case 0xf: /* Netburst */
Possible switch case/default not preceded by break or fallthrough comment
https://review.coreboot.org/#/c/22604/34/src/cpu/intel/common/fsb.c@62
PS34, Line 62: default:
Possible switch case/default not preceded by break or fallthrough comment
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Change subject: cpu/intel/speedstep: Add Netburst CPUs
......................................................................
Patch Set 33:
(2 comments)
https://review.coreboot.org/#/c/22604/33/src/cpu/intel/common/fsb.c
File src/cpu/intel/common/fsb.c:
https://review.coreboot.org/#/c/22604/33/src/cpu/intel/common/fsb.c@48
PS33, Line 48: case 0xf: /* Netburst */
Possible switch case/default not preceded by break or fallthrough comment
https://review.coreboot.org/#/c/22604/33/src/cpu/intel/common/fsb.c@62
PS33, Line 62: default:
Possible switch case/default not preceded by break or fallthrough comment
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Hello build bot (Jenkins), Hannah Williams,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29423
to look at the new patch set (#5).
Change subject: soc/intel/braswell: Configure IO APIC
......................................................................
soc/intel/braswell: Configure IO APIC
IO APIC is not configured.
Add sc_enable_ioapic() copied from fsp_baytrail Soc.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/soc/intel/braswell/Kconfig
M src/soc/intel/braswell/include/soc/lpc.h
M src/soc/intel/braswell/southcluster.c
3 files changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29423/5
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/29456 )
Change subject: util/docker: Unify local build targets
......................................................................
Patch Set 1: Code-Review+2
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