coreboot-gerrit November 2018

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Change in coreboot[master]: (console, drivers/uart)/Kconfig: Fix dependencies
by Nico Huber (Code Review) 11 Nov '18

11 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29572 Change subject: (console,drivers/uart)/Kconfig: Fix dependencies ...................................................................... (console,drivers/uart)/Kconfig: Fix dependencies The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART, because it's using its interface. The individual UART drivers select DRIVERS_UART, because they implement the interface and depend on the common UART code. Some guards had to be fixed (using CONSOLE_SERIAL now instead of DRIVERS_UART). Some other guards that were only about compilation of units were removed. We want to build test as much as possible, right? Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/console/Kconfig M src/cpu/allwinner/a10/Makefile.inc M src/cpu/ti/am335x/Makefile.inc M src/drivers/uart/Kconfig M src/mainboard/google/gru/bootblock.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_rialto/bootblock.c M src/soc/broadcom/cygnus/Makefile.inc M src/soc/imgtec/pistachio/Makefile.inc M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8183/Makefile.inc M src/soc/nvidia/tegra124/Makefile.inc M src/soc/nvidia/tegra210/Makefile.inc M src/soc/qualcomm/ipq40xx/Makefile.inc M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq806x/Makefile.inc M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/sdm845/Kconfig M src/soc/qualcomm/sdm845/Makefile.inc M src/soc/rockchip/rk3288/Makefile.inc M src/soc/rockchip/rk3399/Makefile.inc M src/soc/samsung/exynos5250/Makefile.inc 23 files changed, 59 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29572/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index 318ca18..e7e3298 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -29,7 +29,7 @@ config CONSOLE_SERIAL bool "Serial port console output" default y - depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL + depends on DRIVERS_UART help Send coreboot debug output to a serial port. diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 152d765..a6cd4b4 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -21,11 +21,9 @@ ramstage-y += timer.c ramstage-y += twi.c -ifeq ($(CONFIG_DRIVERS_UART),y) -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c uart_console.c +bootblock-y += uart.c uart_console.c romstage-y += uart.c uart_console.c ramstage-y += uart.c uart_console.c -endif real-target: $(obj)/BOOT0 diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index 5b91981..24a79dd 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -12,11 +12,9 @@ ramstage-y += nand.c ramstage-y += cbmem.c -ifeq ($(CONFIG_DRIVERS_UART),y) -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +bootblock-y += uart.c romstage-y += uart.c ramstage-y += uart.c -endif $(call add-class,omap-header) $(eval $(call create_class_compiler,omap-header,arm)) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 1130aeb..1f23a19 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -1,7 +1,5 @@ config DRIVERS_UART bool - default y if CONSOLE_SERIAL - default n config DRIVERS_UART_8250IO # FIXME: Shouldn't have a prompt, should default to n, and @@ -11,6 +9,7 @@ default n if DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL default n if NO_UART_ON_SUPERIO default y + select DRIVERS_UART config DRIVERS_UART_8250IO_SKIP_INIT def_bool n @@ -37,6 +36,7 @@ config DRIVERS_UART_8250MEM bool default n + select DRIVERS_UART config DRIVERS_UART_8250MEM_32 bool @@ -46,6 +46,7 @@ config HAVE_UART_SPECIAL bool default n + select DRIVERS_UART config DRIVERS_UART_OXPCIE bool "Oxford OXPCIe952" diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 0013414..b2f7d57 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -49,16 +49,16 @@ if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) gpio_output(GPIO_P15V_EN, 1); /* Scarlet: EC-controlled */ -#if IS_ENABLED(CONFIG_DRIVERS_UART) - _Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE, - "CONSOLE_SERIAL_UART should be UART2"); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + _Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE, + "CONSOLE_SERIAL_UART should be UART2"); - /* iomux: select gpio4c[4:3] as uart2 dbg port */ - write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C); + /* iomux: select gpio4c[4:3] as uart2 dbg port */ + write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C); - /* grf soc_con7[11:10] use for uart2 select */ - write32(&rk3399_grf->soc_con7, UART2C_SEL); -#endif + /* grf soc_con7[11:10] use for uart2 select */ + write32(&rk3399_grf->soc_con7, UART2C_SEL); + } } static void configure_spi_flash(void) diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c index 5126ce5..8648a3c 100644 --- a/src/mainboard/google/veyron/bootblock.c +++ b/src/mainboard/google/veyron/bootblock.c @@ -31,11 +31,10 @@ void bootblock_mainboard_early_init() { - if (IS_ENABLED(CONFIG_DRIVERS_UART)) { + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); write32(&rk3288_grf->iomux_uart2, IOMUX_UART2); } - } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index 1110a0b..28f6b14 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -31,11 +31,10 @@ void bootblock_mainboard_early_init() { - if (IS_ENABLED(CONFIG_DRIVERS_UART)) { + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); write32(&rk3288_grf->iomux_uart2, IOMUX_UART2); } - } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index 1ba01fb..626d987 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -31,11 +31,10 @@ void bootblock_mainboard_early_init() { - if (IS_ENABLED(CONFIG_DRIVERS_UART)) { + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); write32(&rk3288_grf->iomux_uart2, IOMUX_UART2); } - } void bootblock_mainboard_init(void) diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc index cfbaaa7..21c5806 100644 --- a/src/soc/broadcom/cygnus/Makefile.inc +++ b/src/soc/broadcom/cygnus/Makefile.inc @@ -23,13 +23,13 @@ bootblock-y += hw_init.c bootblock-$(CONFIG_SPI_FLASH) += spi.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += ns16550.c +bootblock-y += ns16550.c endif verstage-y += i2c.c verstage-y += timer.c verstage-$(CONFIG_SPI_FLASH) += spi.c -verstage-$(CONFIG_DRIVERS_UART) += ns16550.c +verstage-y += ns16550.c romstage-y += cbmem.c romstage-y += i2c.c @@ -37,7 +37,7 @@ romstage-y += romstage.c romstage-y += sdram.c romstage-$(CONFIG_SPI_FLASH) += spi.c -romstage-$(CONFIG_DRIVERS_UART) += ns16550.c +romstage-y += ns16550.c romstage-y += ddr_init.c romstage-y += ddr_init_table.c romstage-y += shmoo_and28.c @@ -53,7 +53,7 @@ ramstage-y += soc.c ramstage-y += timer.c ramstage-$(CONFIG_SPI_FLASH) += spi.c -ramstage-$(CONFIG_DRIVERS_UART) += ns16550.c +ramstage-y += ns16550.c ramstage-y += usb.c CPPFLAGS_common += -Isrc/soc/broadcom/cygnus/include/ diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc index 78e7789..6e8d539 100644 --- a/src/soc/imgtec/pistachio/Makefile.inc +++ b/src/soc/imgtec/pistachio/Makefile.inc @@ -22,11 +22,9 @@ romstage-y += spi.c ramstage-y += spi.c -ifeq ($(CONFIG_DRIVERS_UART),y) -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +bootblock-y += uart.c romstage-y += uart.c ramstage-y += uart.c -endif bootblock-y += monotonic_timer.c diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index e125e03..9c7acf9 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -23,9 +23,7 @@ bootblock-y += ../common/timer.c bootblock-y += timer.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c -endif +bootblock-y += ../common/uart.c bootblock-y += ../common/gpio.c gpio.c gpio_init.c pmic_wrap.c mt6391.c bootblock-y += ../common/wdt.c @@ -36,7 +34,7 @@ verstage-y += i2c.c verstage-y += ../common/spi.c spi.c -verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +verstage-y += ../common/uart.c verstage-y += ../common/timer.c verstage-y += timer.c @@ -52,7 +50,7 @@ romstage-y += timer.c romstage-y += i2c.c -romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +romstage-y += ../common/uart.c romstage-y += ../common/cbmem.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/spi.c spi.c @@ -71,7 +69,7 @@ ramstage-y += soc.c ../common/mtcmos.c ramstage-y += ../common/timer.c ramstage-y += timer.c -ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +ramstage-y += ../common/uart.c ramstage-y += pmic_wrap.c mt6391.c i2c.c ramstage-y += mt6311.c ramstage-y += da9212.c diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index bd81258..9fff52f 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -6,9 +6,7 @@ bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c -endif +bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c decompressor-y += decompressor.c @@ -19,7 +17,7 @@ verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c -verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +verstage-y += ../common/uart.c verstage-y += ../common/wdt.c romstage-y += auxadc.c @@ -32,7 +30,7 @@ romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c -romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +romstage-y += ../common/uart.c romstage-y += ../common/wdt.c ramstage-y += auxadc.c @@ -43,7 +41,7 @@ ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += ../common/timer.c -ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 2f0f470..fb5389f 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -16,15 +16,13 @@ bootblock-y += ../tegra/pingroup.c bootblock-y += ../tegra/pinmux.c bootblock-y += ../tegra/apbmisc.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += uart.c -endif +bootblock-y += uart.c verstage-y += verstage.c verstage-y += dma.c verstage-y += monotonic_timer.c verstage-y += spi.c -verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-y += uart.c verstage-y += ../tegra/gpio.c verstage-y += ../tegra/i2c.c verstage-y += ../tegra/pinmux.c @@ -46,7 +44,7 @@ romstage-$(CONFIG_SOFTWARE_I2C) += ../tegra/software_i2c.c romstage-y += ../tegra/pinmux.c romstage-y += cache.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += uart.c ramstage-y += cbmem.c ramstage-y += clock.c @@ -65,7 +63,7 @@ ramstage-$(CONFIG_SOFTWARE_I2C) += ../tegra/software_i2c.c ramstage-y += ../tegra/pinmux.c ramstage-y += ../tegra/usb.c -ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += uart.c rmodules_$(ARCH-romstage-y)-y += monotonic_timer.c diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index a2b50c9..e213751 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -18,16 +18,14 @@ bootblock-y += ../tegra/pinmux.c bootblock-y += ../tegra/apbmisc.c bootblock-y += ../tegra/usb.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += uart.c -endif +bootblock-y += uart.c verstage-y += dma.c verstage-y += monotonic_timer.c verstage-y += spi.c verstage-y += padconfig.c verstage-y += funitcfg.c -verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-y += uart.c verstage-y += ../tegra/gpio.c verstage-y += ../tegra/i2c.c verstage-y += ../tegra/pinmux.c @@ -57,7 +55,7 @@ romstage-y += ../tegra/i2c.c romstage-y += ../tegra/pinmux.c romstage-y += ../tegra/usb.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += uart.c ramstage-y += addressmap.c ramstage-y += cbmem.c @@ -92,7 +90,7 @@ ramstage-y += ../tegra/pinmux.c ramstage-y += ramstage.c ramstage-y += mmu_operations.c -ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += uart.c ramstage-y += ../tegra/usb.c ramstage-$(CONFIG_HAVE_MTC) += mtc.c ramstage-y += stage_entry.S diff --git a/src/soc/qualcomm/ipq40xx/Makefile.inc b/src/soc/qualcomm/ipq40xx/Makefile.inc index d66a3d8..6447acf 100644 --- a/src/soc/qualcomm/ipq40xx/Makefile.inc +++ b/src/soc/qualcomm/ipq40xx/Makefile.inc @@ -20,7 +20,7 @@ bootblock-y += gpio.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += timer.c -bootblock-$(CONFIG_DRIVERS_UART) += uart.c +bootblock-y += uart.c verstage-y += clock.c verstage-y += gpio.c @@ -29,14 +29,14 @@ verstage-y += qup.c verstage-y += spi.c verstage-y += timer.c -verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-y += uart.c romstage-y += clock.c romstage-y += blobs_init.c romstage-y += gpio.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += timer.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += uart.c romstage-y += cbmem.c romstage-y += i2c.c romstage-y += blsp.c diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index 4b0bffd..d819c1c 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -108,7 +108,6 @@ return MSM_BOOT_UART_DM_E_SUCCESS; } -#if IS_ENABLED(CONFIG_DRIVERS_UART) static unsigned int msm_boot_uart_dm_init(void *uart_dm_base); /* Received data is valid or not */ @@ -117,7 +116,6 @@ /* Received data */ static unsigned int word = 0; - void uart_tx_byte(int idx, unsigned char data) { int num_of_chars = 1; @@ -136,7 +134,6 @@ /* And now write the character(s) */ write32(MSM_BOOT_UART_DM_TF(base, 0), data); } -#endif /* CONFIG_SERIAL_UART */ /** * @brief msm_boot_uart_dm_reset - resets UART controller @@ -271,7 +268,6 @@ ; } -#if IS_ENABLED(CONFIG_DRIVERS_UART) /** * ipq40xx_serial_getc - reads a character * @@ -287,7 +283,6 @@ return byte; } -#endif #ifndef __PRE_RAM__ /* TODO: Implement function */ diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index b14db03..8a428b2 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -19,7 +19,7 @@ bootblock-y += gpio.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += timer.c -bootblock-$(CONFIG_DRIVERS_UART) += uart.c +bootblock-y += uart.c verstage-y += clock.c verstage-y += gpio.c @@ -28,14 +28,14 @@ verstage-y += qup.c verstage-y += spi.c verstage-y += timer.c -verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-y += uart.c romstage-y += clock.c romstage-y += blobs_init.c romstage-y += gpio.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += timer.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += uart.c romstage-y += cbmem.c romstage-y += i2c.c romstage-y += gsbi.c diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 3af7958..3805c87 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -109,7 +109,6 @@ return MSM_BOOT_UART_DM_E_SUCCESS; } -#if IS_ENABLED(CONFIG_DRIVERS_UART) static unsigned int msm_boot_uart_dm_init(void *uart_dm_base); /* Received data is valid or not */ @@ -212,7 +211,6 @@ /* And now write the character(s) */ write32(MSM_BOOT_UART_DM_TF(base, 0), tx_data); } -#endif /* CONFIG_SERIAL_UART */ /* * msm_boot_uart_dm_reset - resets UART controller @@ -380,7 +378,6 @@ } #endif -#if IS_ENABLED(CONFIG_DRIVERS_UART) /** * ipq806x_serial_getc - reads a character * @@ -401,7 +398,6 @@ return byte; } -#endif #ifndef __PRE_RAM__ /* TODO: Implement fuction */ diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index 6399ad1..c5d8009 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -11,6 +11,7 @@ select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select ARM64_USE_ARCH_TIMER + select HAVE_UART_SPECIAL if SOC_QUALCOMM_SDM845 diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index e603177..507d913 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -7,7 +7,7 @@ bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += gpio.c -bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +bootblock-y += uart_bitbang.c ################################################################################ verstage-y += spi.c diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 100c00e..7e4c5b4 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -19,9 +19,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/cbmem.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c -endif +bootblock-y += ../common/uart.c bootblock-y += timer.c bootblock-y += clock.c bootblock-y += ../common/spi.c @@ -33,7 +31,7 @@ verstage-y += ../common/spi.c verstage-y += timer.c -verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +verstage-y += ../common/uart.c verstage-y += ../common/gpio.c verstage-y += gpio.c verstage-y += clock.c @@ -43,7 +41,7 @@ romstage-y += ../common/cbmem.c romstage-y += timer.c -romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +romstage-y += ../common/uart.c romstage-y += ../common/i2c.c romstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c romstage-y += clock.c @@ -72,7 +70,7 @@ ramstage-y += ../common/edp.c ramstage-y += hdmi.c ramstage-y += display.c -ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +ramstage-y += ../common/uart.c CPPFLAGS_common += -Isrc/soc/rockchip/rk3288/include CPPFLAGS_common += -Isrc/soc/rockchip/common/include diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 83936e8..854eb84 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -22,9 +22,7 @@ bootblock-y += ../common/i2c.c bootblock-y += ../common/spi.c -ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) -bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c -endif +bootblock-y += ../common/uart.c bootblock-y += ../common/gpio.c bootblock-y += ../common/pwm.c bootblock-y += bootblock.c @@ -39,7 +37,7 @@ verstage-y += sdram.c verstage-y += ../common/i2c.c verstage-y += ../common/spi.c -verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +verstage-y += ../common/uart.c verstage-y += clock.c verstage-y += timer.c @@ -48,7 +46,7 @@ romstage-y += ../common/cbmem.c romstage-y += sdram.c romstage-y += ../common/spi.c -romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +romstage-y += ../common/uart.c romstage-y += clock.c romstage-y += ../common/pwm.c romstage-y += timer.c @@ -64,7 +62,7 @@ ramstage-y += ../common/cbmem.c ramstage-y += sdram.c ramstage-y += ../common/spi.c -ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c +ramstage-y += ../common/uart.c ramstage-y += clock.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/edp.c diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc index 2731f17..a6eb9ee 100644 --- a/src/soc/samsung/exynos5250/Makefile.inc +++ b/src/soc/samsung/exynos5250/Makefile.inc @@ -4,11 +4,9 @@ bootblock-y += bootblock.c bootblock-y += pinmux.c timer.c power.c # Clock is required for UART -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c -ifeq ($(CONFIG_DRIVERS_UART),y) -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c -endif +bootblock-y += clock_init.c +bootblock-y += clock.c +bootblock-y += uart.c bootblock-y += wakeup.c bootblock-y += gpio.c @@ -20,7 +18,7 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += timer.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += uart.c romstage-y += wakeup.c romstage-y += gpio.c romstage-y += trustzone.c @@ -33,7 +31,7 @@ ramstage-y += clock_init.c ramstage-y += pinmux.c ramstage-y += power.c -ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += uart.c ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += timer.c -- To view, visit https://review.coreboot.org/29572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9 Gerrit-Change-Number: 29572 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: drivers/uart/Kconfig: Be smarter about DRIVERS_UART_8250IO
by Nico Huber (Code Review) 11 Nov '18

11 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29571 Change subject: drivers/uart/Kconfig: Be smarter about DRIVERS_UART_8250IO ...................................................................... drivers/uart/Kconfig: Be smarter about DRIVERS_UART_8250IO It defaults to y to avoid having to select it per mainboard. But that makes a mess because it results in linker conflicts unless other UART drivers disable it explicitly. We try to be smarter about the default value for now. The real solu- tion would be to hardcode it per mainboard. But who knows which boards actually have it? Change-Id: I7e755fe0e4f6d1c31ef2854603a5510c3cdc4967 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/uart/Kconfig M src/soc/intel/denverton_ns/Kconfig 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/29571/1 diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 39d20a3..1130aeb 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -4,8 +4,11 @@ default n config DRIVERS_UART_8250IO + # FIXME: Shouldn't have a prompt, should default to n, and + # should be selected by boards that have it instead. bool "Serial port on SuperIO" depends on ARCH_X86 + default n if DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL default n if NO_UART_ON_SUPERIO default y diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 736d567..59655ce 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -166,7 +166,7 @@ endchoice config ENABLE_HSUART - depends on (!DRIVERS_UART_8250IO && NON_LEGACY_UART_MODE) + depends on NON_LEGACY_UART_MODE bool "Enable High-speed UART debug port selected by UART_FOR_CONSOLE." default n select CONSOLE_SERIAL -- To view, visit https://review.coreboot.org/29571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7e755fe0e4f6d1c31ef2854603a5510c3cdc4967 Gerrit-Change-Number: 29571 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: soc/intel/braswell: add vmx support via CPU_INTEL_COMMON
by Matt DeVillier (Code Review) 10 Nov '18

10 Nov '18

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/29570 Change subject: soc/intel/braswell: add vmx support via CPU_INTEL_COMMON ...................................................................... soc/intel/braswell: add vmx support via CPU_INTEL_COMMON Braswell allready supported vmx, but offered no mechanism to unset it, nor to set the lock bit required for Windows to recognize virtualization. Enable this functionality by adding CPU_INTEL_COMMON config. Test: build/boot Windows 10 on Braswell ChromeOS device, verify Windows shows virtualization as enabled. Change-Id: I0d39abaeb9eebcceb37dc791df6b06e521fe1992 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/cpu.c 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29570/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 2ba7992..50c2802 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -47,6 +47,7 @@ select GENERIC_GPIO_LIB select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI + select CPU_INTEL_COMMON config VBOOT select VBOOT_STARTS_IN_ROMSTAGE diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 38dcf5a..ac1bacd 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -7,6 +7,7 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/intel/common romstage-y += gpio_support.c romstage-y += iosf.c diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 195dba4..9063c2a 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/microcode.h> #include <cpu/intel/turbo.h> #include <cpu/x86/cache.h> @@ -60,6 +61,9 @@ if (lapicid()) enable_turbo(); + /* Set virtualization based on Kconfig option */ + set_vmx(); + /* Set core MSRs */ reg_script_run(core_msr_script); -- To view, visit https://review.coreboot.org/29570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0d39abaeb9eebcceb37dc791df6b06e521fe1992 Gerrit-Change-Number: 29570 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: lenovo/h8, thinkpads: Re-do USB Always On
by Patrick Rudolph (Code Review) 10 Nov '18

10 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29565 ) Change subject: lenovo/h8,thinkpads: Re-do USB Always On ...................................................................... Patch Set 4: Code-Review+1 (2 comments) https://review.coreboot.org/#/c/29565/4/src/ec/lenovo/h8/h8.c File src/ec/lenovo/h8/h8.c: https://review.coreboot.org/#/c/29565/4/src/ec/lenovo/h8/h8.c@136 PS4, Line 136: bits Pointless comment. It's clear from code below https://review.coreboot.org/#/c/29565/4/src/ec/lenovo/h8/h8.c@141 PS4, Line 141: ; Please don't use magic values -- To view, visit https://review.coreboot.org/29565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If812cd1ef8fb1a24d7fadbe834f574b40cbcd56a Gerrit-Change-Number: 29565 Gerrit-PatchSet: 4 Gerrit-Owner: Nathaniel Roach <nroach44(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 10 Nov 2018 22:29:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/acpi.h: Add FACS – ospm flags
by Patrick Rudolph (Code Review) 10 Nov '18

10 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29569 ) Change subject: arch/acpi.h: Add FACS – ospm_flags ...................................................................... Patch Set 2: Commit message doesn't explain why the change is done. I find sentences starting with 'regarding' hard to understand. -- To view, visit https://review.coreboot.org/29569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I91291c8202d1562b720b9922791c6282e572601f Gerrit-Change-Number: 29569 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 10 Nov 2018 22:21:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: arch/acpi.h: Add FACS – ospm flags
by Elyes HAOUAS (Code Review) 10 Nov '18

10 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29569 to look at the new patch set (#2). Change subject: arch/acpi.h: Add FACS – ospm_flags ...................................................................... arch/acpi.h: Add FACS – ospm_flags regarding ACPI Version 6.2 Errata A, 64BIT_WAKE_F flag can only be set if platform firmware sets 64BIT_WAKE_SUPPORTED_F in the FACS flags field. Change-Id: I91291c8202d1562b720b9922791c6282e572601f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/acpi.h 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29569/2 -- To view, visit https://review.coreboot.org/29569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I91291c8202d1562b720b9922791c6282e572601f Gerrit-Change-Number: 29569 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: arch/acpi.h: Add FACS – ospm flags
by Elyes HAOUAS (Code Review) 10 Nov '18

10 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29569 Change subject: arch/acpi.h: Add FACS – ospm_flags ...................................................................... arch/acpi.h: Add FACS – ospm_flags regarding ACPI Version 6.2 Errata A, 64BIT_WAKE_F flag can only be set if platform firmware sets 64BIT_WAKE_SUPPORTED_F in the FACS flags field. Change-Id: I91291c8202d1562b720b9922791c6282e572601f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/acpi.h 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29569/1 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index b5205c0..b5fac2f 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -600,8 +600,10 @@ u32 flags; /* FACS flags */ u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ - u8 version; /* ACPI 4.0: 2 */ - u8 resv[31]; /* FIXME: 4.0: ospm_flags */ + u8 version; /* ACPI 6.2-A: 2 */ + u8 resv[3]; /* ACPI 6.2-A: 0 */ + u8 ospm_flags; /* 64BIT_WAKE_F */ + u8 resv[24]; /* ACPI 6.2-A: 0 */ } __packed acpi_facs_t; /* FACS flags */ -- To view, visit https://review.coreboot.org/29569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I91291c8202d1562b720b9922791c6282e572601f Gerrit-Change-Number: 29569 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: cpu/intel/speedstep: Add Netburst CPUs
by build bot (Jenkins) (Code Review) 10 Nov '18

10 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22604 ) Change subject: cpu/intel/speedstep: Add Netburst CPUs ...................................................................... Patch Set 42: (1 comment) https://review.coreboot.org/#/c/22604/42/src/cpu/intel/common/fsb.c File src/cpu/intel/common/fsb.c: https://review.coreboot.org/#/c/22604/42/src/cpu/intel/common/fsb.c@48 PS42, Line 48: case 0xf: /* Netburst */ Possible switch case/default not preceded by break or fallthrough comment -- To view, visit https://review.coreboot.org/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 42 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Sat, 10 Nov 2018 11:37:23 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/intel/speedstep: Add Netburst CPUs
by build bot (Jenkins) (Code Review) 10 Nov '18

10 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22604 ) Change subject: cpu/intel/speedstep: Add Netburst CPUs ...................................................................... Patch Set 41: (1 comment) https://review.coreboot.org/#/c/22604/41/src/cpu/intel/common/fsb.c File src/cpu/intel/common/fsb.c: https://review.coreboot.org/#/c/22604/41/src/cpu/intel/common/fsb.c@48 PS41, Line 48: case 0xf: /* Netburst */ Possible switch case/default not preceded by break or fallthrough comment -- To view, visit https://review.coreboot.org/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 41 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Sat, 10 Nov 2018 11:21:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: cpu/intel/speedstep: Add Netburst CPUs
by build bot (Jenkins) (Code Review) 10 Nov '18

10 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22604 ) Change subject: cpu/intel/speedstep: Add Netburst CPUs ...................................................................... Patch Set 40: (1 comment) https://review.coreboot.org/#/c/22604/40/src/cpu/intel/common/fsb.c File src/cpu/intel/common/fsb.c: https://review.coreboot.org/#/c/22604/40/src/cpu/intel/common/fsb.c@48 PS40, Line 48: case 0xf: /* Netburst */ Possible switch case/default not preceded by break or fallthrough comment -- To view, visit https://review.coreboot.org/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 40 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Sat, 10 Nov 2018 11:05:03 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit November 2018