coreboot-gerrit November 2018

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Change in coreboot[master]: mb/emulation/qemu-i440fx|q35: Get rid of unused headers
by Felix Held (Code Review) 11 Nov '18

11 Nov '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/29577 ) Change subject: mb/emulation/qemu-i440fx|q35: Get rid of unused headers ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/29577/1/src/mainboard/emulation/qemu-i440fx… File src/mainboard/emulation/qemu-i440fx/mainboard.c: https://review.coreboot.org/#/c/29577/1/src/mainboard/emulation/qemu-i440fx… PS1, Line 21: pci_write_config8 is implemented in arch/io.h https://review.coreboot.org/#/c/29577/1/src/mainboard/emulation/qemu-q35/ma… File src/mainboard/emulation/qemu-q35/mainboard.c: https://review.coreboot.org/#/c/29577/1/src/mainboard/emulation/qemu-q35/ma… PS1, Line 22: #include <drivers/intel/gma/i915.h> pci_write_config8 is implemented in arch/io.h -- To view, visit https://review.coreboot.org/29577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3cf0e4ef5b090d15ad823747fcf9219644e130fc Gerrit-Change-Number: 29577 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 11 Nov 2018 12:25:47 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/emulation/qemu-i440fx|q35: Link memory.c
by Felix Held (Code Review) 11 Nov '18

11 Nov '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/29574 ) Change subject: mb/emulation/qemu-i440fx|q35: Link memory.c ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/29574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2bc461b13332ec5885c33c87828a5fd023f8e730 Gerrit-Change-Number: 29574 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 11 Nov 2018 12:15:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/emulation/qemu-i440fx|q35: Switch to C_ENVIRONMENT_BOOTBLOCK
by Patrick Rudolph (Code Review) 11 Nov '18

11 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/29578 Change subject: mb/emulation/qemu-i440fx|q35: Switch to C_ENVIRONMENT_BOOTBLOCK ...................................................................... mb/emulation/qemu-i440fx|q35: Switch to C_ENVIRONMENT_BOOTBLOCK Useful for testing stuff in C_ENVIRONMENT_BOOTBLOCK, like VBOOT with separate verstage. Change-Id: Ibf341002c36d868b9b44c8b37381fa78ae5c4381 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/cpu/qemu-x86/Kconfig M src/cpu/qemu-x86/Makefile.inc A src/cpu/qemu-x86/bootblock.c R src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/Makefile.inc M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/romstage.c 9 files changed, 85 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/29578/1 diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index ab8e1a9..70cce9b 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -21,3 +21,4 @@ select ARCH_RAMSTAGE_X86_32 select SMP select UDELAY_TSC + select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index 288eea6..8ddaa81 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -12,6 +12,8 @@ ## GNU General Public License for more details. ## +bootblock-y += cache_as_ram_bootblock.S +bootblock-y += bootblock.c ramstage-y += qemu.c subdirs-y += ../x86/mtrr subdirs-y += ../x86/lapic diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c new file mode 100644 index 0000000..2a4c028 --- /dev/null +++ b/src/cpu/qemu-x86/bootblock.c @@ -0,0 +1,21 @@ +#include <bootblock_common.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <console/console.h> +#include <cpu/x86/bist.h> + +asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist); + +asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) +{ + post_code(0x05); + + /* Halt if there was a built in self test failure */ + if (bist) { + console_init(); + report_bist_failure(bist); + } + + /* Call lib/bootblock.c main */ + bootblock_main_with_timestamp(base_timestamp, NULL, 0); +} diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/cpu/qemu-x86/cache_as_ram_bootblock.S similarity index 67% rename from src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc rename to src/cpu/qemu-x86/cache_as_ram_bootblock.S index d36341c..9b9f070 100644 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -20,8 +20,8 @@ #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) - /* Save the BIST result. */ - movl %eax, %ebp +.global bootblock_pre_c_entry +bootblock_pre_c_entry: cache_as_ram: post_code(0x20) @@ -37,27 +37,32 @@ * of big ramstages. The ramstage will load its own %esp so * there is no harm in using this value. */ - movl $0xa0000, %eax + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax + /* Align the stack and keep aligned for call to bootblock_c_entry() */ + and $0xfffffff0, %esp movl %esp, %ebp + + /* Clear the cache memory region. This will also clear CAR GLOBAL */ + movl $CONFIG_DCACHE_RAM_BASE, %esi + movl %esi, %edi + movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + + /* Restore the BIST result and timestamps. */ + movd %mm0, %ebx + movd %mm1, %eax + movd %mm2, %edx + + pushl %ebx + pushl %edx pushl %eax -before_romstage: +before_c_entry: post_code(0x29) - /* Call romstage.c main function. */ - call romstage_main - - post_code(0x30) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - call copy_and_run - + call bootblock_c_entry_bist + /* Never returns */ .Lhlt: post_code(POST_DEAD_CODE) hlt diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index fc56ab6..0b113cc 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -12,6 +12,7 @@ select BOARD_ROMSIZE_KB_256 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select BOOTBLOCK_CONSOLE config MAINBOARD_DIR string @@ -25,12 +26,23 @@ int default 6 +# Skip the first 64KiB as coreboot table pointer is installed +# at address 0 config DCACHE_RAM_BASE hex - default 0xd0000 + default 0x10000 +# Memory at 0xa0000 decodes to VGA config DCACHE_RAM_SIZE hex - default 0x10000 + default 0x90000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x4000 endif # BOARD_EMULATION_QEMU_X86_I440FX diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index c986667..38e5237 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -1,4 +1,4 @@ -cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +romstage-y += romstage.c ramstage-y += northbridge.c ramstage-y += fw_cfg.c romstage-y += memory.c diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 9530621..3432a00 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -16,30 +16,17 @@ #include <stdint.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <timestamp.h> -#include <delay.h> -#include <cpu/x86/lapic.h> +#include <program_loading.h> - -void *asmlinkage romstage_main(unsigned long bist) +asmlinkage void car_stage_entry(void) { - int cbmem_was_initted; - - /* init_timer(); */ - post_code(0x05); - console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); + cbmem_recovery(0); - cbmem_was_initted = !cbmem_recovery(0); - - timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - /* Emulation uses fixed low stack during ramstage. */ - return NULL; + run_ramstage(); } diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 10b5a93..5aee4ec 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -11,6 +11,7 @@ select BOARD_ROMSIZE_KB_2048 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT + select BOOTBLOCK_CONSOLE config MAINBOARD_DIR string @@ -28,17 +29,28 @@ hex default 0xb0000000 +# Skip the first 64KiB as coreboot table pointer is installed +# at address 0 config DCACHE_RAM_BASE hex - default 0xd0000 + default 0x10000 +# Memory at 0xa0000 decodes to VGA config DCACHE_RAM_SIZE hex - default 0x10000 + default 0x90000 # Do not show IFD/blob options since QEMU doesn't care config HAVE_INTEL_FIRMWARE bool default n +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x4000 + endif # BOARD_EMULATION_QEMU_X86_Q35 diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index deb94af..38ae0ca 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -16,32 +16,19 @@ #include <stdint.h> #include <cbmem.h> #include <console/console.h> -#include <southbridge/intel/i82801ix/i82801ix.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <timestamp.h> -#include <delay.h> -#include <cpu/x86/lapic.h> +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <program_loading.h> - -void * asmlinkage romstage_main(unsigned long bist) +asmlinkage void car_stage_entry(void) { - int cbmem_was_initted; - - /* init_timer(); */ - post_code(0x05); - i82801ix_early_init(); console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); + cbmem_recovery(0); - cbmem_was_initted = !cbmem_recovery(0); - - timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - /* Emulation uses fixed low stack during ramstage. */ - return NULL; + run_ramstage(); } -- To view, visit https://review.coreboot.org/29578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibf341002c36d868b9b44c8b37381fa78ae5c4381 Gerrit-Change-Number: 29578 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mb/emulation/qemu-i440fx|q35: Get rid of unused headers
by Patrick Rudolph (Code Review) 11 Nov '18

11 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/29577 Change subject: mb/emulation/qemu-i440fx|q35: Get rid of unused headers ...................................................................... mb/emulation/qemu-i440fx|q35: Get rid of unused headers Change-Id: I3cf0e4ef5b090d15ad823747fcf9219644e130fc Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/emulation/qemu-i440fx/acpi_tables.c M src/mainboard/emulation/qemu-i440fx/mainboard.c M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/mainboard.c M src/mainboard/emulation/qemu-q35/romstage.c 6 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/29577/1 diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c index f775901..abd2633 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c @@ -14,14 +14,11 @@ */ #include <types.h> -#include <string.h> #include <arch/acpi.h> #include <arch/ioapic.h> #include <arch/acpigen.h> #include <arch/smp/mpspec.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> #include "fw_cfg.h" #include "acpi.h" diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index b2439bb..4886fe1 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -16,10 +16,8 @@ #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/keyboard.h> -#include <arch/io.h> static const unsigned char qemu_i440fx_irqs[] = { 11, 10, 10, 11, diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 0795012..9d9225c 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -21,7 +21,6 @@ #include <device/pci.h> #include <stdlib.h> #include <string.h> -#include <delay.h> #include <smbios.h> #include "memory.h" diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index d41213a..9530621 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -14,10 +14,6 @@ */ #include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 354450b..f89b0a8 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -19,7 +19,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/keyboard.h> -#include <arch/io.h> #include <drivers/intel/gma/i915.h> #define Q35_PAM0 0x90 diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 846fcf3..deb94af 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -14,11 +14,6 @@ */ #include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <pc80/mc146818rtc.h> #include <cbmem.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> -- To view, visit https://review.coreboot.org/29577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3cf0e4ef5b090d15ad823747fcf9219644e130fc Gerrit-Change-Number: 29577 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mb/emulation/qemu-i440fx|q35: Link memory.c
by Patrick Rudolph (Code Review) 11 Nov '18

11 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29574 to look at the new patch set (#2). Change subject: mb/emulation/qemu-i440fx|q35: Link memory.c ...................................................................... mb/emulation/qemu-i440fx|q35: Link memory.c Link memory.c instead of including it. Change-Id: I2bc461b13332ec5885c33c87828a5fd023f8e730 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/emulation/qemu-i440fx/Makefile.inc M src/mainboard/emulation/qemu-i440fx/memory.c A src/mainboard/emulation/qemu-i440fx/memory.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/Makefile.inc M src/mainboard/emulation/qemu-q35/romstage.c 7 files changed, 48 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29574/2 -- To view, visit https://review.coreboot.org/29574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2bc461b13332ec5885c33c87828a5fd023f8e730 Gerrit-Change-Number: 29574 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/octopus/var/bobba: Configure EC_SYNC IRQ as level-triggered
by Furquan Shaikh (Code Review) 11 Nov '18

11 Nov '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/29576 Change subject: mb/google/octopus/var/bobba: Configure EC_SYNC IRQ as level-triggered ...................................................................... mb/google/octopus/var/bobba: Configure EC_SYNC IRQ as level-triggered This change updates the configuration of EC_SYNC IRQ to be level triggered to match the EC behavior. Change-Id: I8e3cb2ae8016ea183d9067697aa5d4b9caa2d07e Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/bobba/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/29576/1 diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index 941a961..6b471e5 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -23,7 +23,7 @@ PAD_NC(GPIO_104, UP_20K), /* CAM_SOC_EC_SYNC */ - PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ -- To view, visit https://review.coreboot.org/29576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8e3cb2ae8016ea183d9067697aa5d4b9caa2d07e Gerrit-Change-Number: 29576 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: ec/google/chromeec: Configure EC_SYNC_IRQ as level triggered
by Furquan Shaikh (Code Review) 11 Nov '18

11 Nov '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/29575 Change subject: ec/google/chromeec: Configure EC_SYNC_IRQ as level triggered ...................................................................... ec/google/chromeec: Configure EC_SYNC_IRQ as level triggered EC_SYNC_IRQ from EC to host is level-triggered in practice and configuring it as edge-triggered on the host results in host missing events if there are multiple events queued on the EC side. This is because Linux kernel driver reads one event per irq and the EC does not de-assert the interrupt line until all events are drained out. This results in event queue being filled up completely on the EC and the host failing to see any of those events. This change configures EC_SYNC_IRQ as level triggered to allow the host to read events from the the EC as long as the line is asserted. BUG=b:118949877 Change-Id: Id3fcfa0445f83865d57975a7bbc179dca047ba4c Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/ec/google/chromeec/acpi/cros_ec.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/29575/1 diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index befd5a7..a5f9202 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -25,7 +25,7 @@ #ifdef EC_ENABLE_SYNC_IRQ Name (_CRS, ResourceTemplate () { - Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive) { EC_SYNC_IRQ } -- To view, visit https://review.coreboot.org/29575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id3fcfa0445f83865d57975a7bbc179dca047ba4c Gerrit-Change-Number: 29575 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/emulation/qemu-i440fx|q35: Fixes and code cleanup
by Patrick Rudolph (Code Review) 11 Nov '18

11 Nov '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/29574 Change subject: mb/emulation/qemu-i440fx|q35: Fixes and code cleanup ...................................................................... mb/emulation/qemu-i440fx|q35: Fixes and code cleanup Changes: * Remove unused headers * Link memory.c instead of including it * Add memory.h for local functions * Add romstage_main.c and link it * Move DCACHE_RAM_BASE to 0x10000 * Set DCACHE_RAM_SIZE to 0x90000 * Clear DCACHE * Set stack pointer to end of DCACHE * Call mainboard_romstage_entry from romstage_main * Code style fixes Fixes: * Console not working in romstage Tested: * qemu-2.11.2 target pc * qemu-2.11.2 target q35 Change-Id: I2bc461b13332ec5885c33c87828a5fd023f8e730 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/Makefile.inc M src/mainboard/emulation/qemu-i440fx/acpi_tables.c M src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc M src/mainboard/emulation/qemu-i440fx/mainboard.c M src/mainboard/emulation/qemu-i440fx/memory.c A src/mainboard/emulation/qemu-i440fx/memory.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-i440fx/romstage.c A src/mainboard/emulation/qemu-i440fx/romstage_main.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/Makefile.inc M src/mainboard/emulation/qemu-q35/mainboard.c M src/mainboard/emulation/qemu-q35/romstage.c 14 files changed, 103 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29574/1 diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index fc56ab6..9450e2c 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -25,12 +25,15 @@ int default 6 +# Skip the first 64KiB as coreboot table pointer is installed +# at address 0 config DCACHE_RAM_BASE hex - default 0xd0000 + default 0x10000 +# Memory at 0xa0000 decodes to VGA config DCACHE_RAM_SIZE hex - default 0x10000 + default 0x90000 endif # BOARD_EMULATION_QEMU_X86_I440FX diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index f9cf252..03a50fc 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -1,3 +1,7 @@ cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +romstage-y += romstage.c ramstage-y += northbridge.c ramstage-y += fw_cfg.c +romstage-y += memory.c +ramstage-y += memory.c +romstage-y += romstage_main.c diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c index f775901..abd2633 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c @@ -14,14 +14,11 @@ */ #include <types.h> -#include <string.h> #include <arch/acpi.h> #include <arch/ioapic.h> #include <arch/acpigen.h> #include <arch/smp/mpspec.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> #include "fw_cfg.h" #include "acpi.h" diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc index d36341c..3f71ce7 100644 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc @@ -37,9 +37,16 @@ * of big ramstages. The ramstage will load its own %esp so * there is no harm in using this value. */ - movl $0xa0000, %eax + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp + /* Clear the cache memory region. This will also clear CAR GLOBAL */ + movl $CONFIG_DCACHE_RAM_BASE, %esi + movl %esi, %edi + movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + /* Restore the BIST result. */ movl %ebp, %eax movl %esp, %ebp @@ -50,14 +57,6 @@ /* Call romstage.c main function. */ call romstage_main - post_code(0x30) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - call copy_and_run - .Lhlt: post_code(POST_DEAD_CODE) hlt diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index b2439bb..4886fe1 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -16,10 +16,8 @@ #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/keyboard.h> -#include <arch/io.h> static const unsigned char qemu_i440fx_irqs[] = { 11, 10, 10, 11, diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index b8109e5..dea96f2 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -14,6 +14,8 @@ */ #include <cbmem.h> +#include <arch/io.h> +#include "memory.h" #define CMOS_ADDR_PORT 0x70 #define CMOS_DATA_PORT 0x71 @@ -25,12 +27,24 @@ #define MID_HIGHRAM_ADDR 0x5c #define LOW_HIGHRAM_ADDR 0x5b -static unsigned long qemu_get_memory_size(void) +unsigned long qemu_get_high_memory_size(void) +{ + unsigned long high; + outb(HIGH_HIGHRAM_ADDR, CMOS_ADDR_PORT); + high = ((unsigned long) inb(CMOS_DATA_PORT)) << 22; + outb(MID_HIGHRAM_ADDR, CMOS_ADDR_PORT); + high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 14; + outb(LOW_HIGHRAM_ADDR, CMOS_ADDR_PORT); + high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6; + return high; +} + +unsigned long qemu_get_memory_size(void) { unsigned long tomk; - outb (HIGH_RAM_ADDR, CMOS_ADDR_PORT); + outb(HIGH_RAM_ADDR, CMOS_ADDR_PORT); tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14; - outb (LOW_RAM_ADDR, CMOS_ADDR_PORT); + outb(LOW_RAM_ADDR, CMOS_ADDR_PORT); tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6; tomk += 16 * 1024; return tomk; diff --git a/src/mainboard/emulation/qemu-i440fx/memory.h b/src/mainboard/emulation/qemu-i440fx/memory.h new file mode 100644 index 0000000..d3b21a6 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/memory.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Stefan Reinauer <stefan.reinauer(a)coreboot.org> + * Copyright (C) 2018 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef __QEMU_MEMORY_H_ +#define __QEMU_MEMORY_H_ + +unsigned long qemu_get_high_memory_size(void); +unsigned long qemu_get_memory_size(void); + +#endif diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index aa309de..9d9225c 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -21,28 +21,14 @@ #include <device/pci.h> #include <stdlib.h> #include <string.h> -#include <delay.h> #include <smbios.h> -#include <cbmem.h> +#include "memory.h" #include "fw_cfg.h" #include "fw_cfg_if.h" -#include "memory.c" #include "acpi.h" -static unsigned long qemu_get_high_memory_size(void) -{ - unsigned long high; - outb (HIGH_HIGHRAM_ADDR, CMOS_ADDR_PORT); - high = ((unsigned long) inb(CMOS_DATA_PORT)) << 22; - outb (MID_HIGHRAM_ADDR, CMOS_ADDR_PORT); - high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 14; - outb (LOW_HIGHRAM_ADDR, CMOS_ADDR_PORT); - high |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6; - return high; -} - static void qemu_reserve_ports(struct device *dev, unsigned int idx, unsigned int base, unsigned int size, const char *name) diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index ce12a8b..9b573f4 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -14,10 +14,7 @@ */ #include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> @@ -25,9 +22,7 @@ #include <delay.h> #include <cpu/x86/lapic.h> -#include "memory.c" - -void *asmlinkage romstage_main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int cbmem_was_initted; @@ -43,7 +38,4 @@ timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - - /* Emulation uses fixed low stack during ramstage. */ - return NULL; } diff --git a/src/mainboard/emulation/qemu-i440fx/romstage_main.c b/src/mainboard/emulation/qemu-i440fx/romstage_main.c new file mode 100644 index 0000000..15e7f56 --- /dev/null +++ b/src/mainboard/emulation/qemu-i440fx/romstage_main.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Stefan Reinauer + * Copyright (C) 2018 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/intel/romstage.h> +#include <console/console.h> +#include <program_loading.h> + +asmlinkage void *romstage_main(unsigned long bist) +{ + mainboard_romstage_entry(bist); + + post_code(0x30); + + run_ramstage(); + + /* We do not return. */ + return NULL; +} diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 10b5a93..faf017a 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -28,13 +28,16 @@ hex default 0xb0000000 +# Skip the first 64KiB as coreboot table pointer is installed +# at address 0 config DCACHE_RAM_BASE hex - default 0xd0000 + default 0x10000 +# Memory at 0xa0000 decodes to VGA config DCACHE_RAM_SIZE hex - default 0x10000 + default 0x90000 # Do not show IFD/blob options since QEMU doesn't care config HAVE_INTEL_FIRMWARE diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index fc4374c..df6e628 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -1,3 +1,6 @@ cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc ramstage-y += ../qemu-i440fx/northbridge.c +ramstage-y += ../qemu-i440fx/memory.c ramstage-y += ../qemu-i440fx/fw_cfg.c +romstage-y += ../qemu-i440fx/memory.c +romstage-y += ../qemu-i440fx/romstage_main.c diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 354450b..f89b0a8 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -19,7 +19,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/keyboard.h> -#include <arch/io.h> #include <drivers/intel/gma/i915.h> #define Q35_PAM0 0x90 diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 870dd07..3be8e03 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -14,22 +14,17 @@ */ #include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <pc80/mc146818rtc.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <timestamp.h> #include <delay.h> +#include <cbmem.h> #include <cpu/x86/lapic.h> +#include "../qemu-i440fx/memory.h" -#include "../qemu-i440fx/memory.c" - -void * asmlinkage romstage_main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int cbmem_was_initted; @@ -46,7 +41,4 @@ timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - - /* Emulation uses fixed low stack during ramstage. */ - return NULL; } -- To view, visit https://review.coreboot.org/29574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2bc461b13332ec5885c33c87828a5fd023f8e730 Gerrit-Change-Number: 29574 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: arch/acpi.h: Add FACS – ospm flags
by Elyes HAOUAS (Code Review) 11 Nov '18

11 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29569 to look at the new patch set (#3). Change subject: arch/acpi.h: Add FACS – ospm_flags ...................................................................... arch/acpi.h: Add FACS – ospm_flags Add ospm_flags needed to set 64BIT_WAKE_F (Bit[0]) to indicate that X FW waking vector requires a 64 bit execution environment. Regarding ACPI Version 6.2 Errata A, 64BIT_WAKE_F flag can only be set if platform firmware sets 64BIT_WAKE_SUPPORTED_F in the FACS flags field. Change-Id: I91291c8202d1562b720b9922791c6282e572601f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/acpi.h 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29569/3 -- To view, visit https://review.coreboot.org/29569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I91291c8202d1562b720b9922791c6282e572601f Gerrit-Change-Number: 29569 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: soc/intel: Clean mess around UART_DEBUG
by Nico Huber (Code Review) 11 Nov '18

11 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29573 Change subject: soc/intel: Clean mess around UART_DEBUG ...................................................................... soc/intel: Clean mess around UART_DEBUG Everything is wrong here, the Kconfig symbols are only the tip of the iceberg. Based on Kconfig prompts the SoC code performed pad configu- rations! I don't see why the person who configures coreboot should have the board schematics at hand. As a mitigation we remove the prompts for UART_DEBUG, which is renamed to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say what it's about), and for UART_FOR_CONSOLE in case the former is selec- ted. Also fixes a bug in `{cannonlake,icelake}/bootblock/pch.c` where the LPC forwarding for an i/o based UART could never have been written because the two checked Kconfigs were mutually exclusive (at least when you tried to link the final binaries together). Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/console/Kconfig M src/mainboard/intel/leafhill/Kconfig M src/mainboard/intel/minnow3/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/bootblock/bootblock.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/common/block/uart/Kconfig M src/soc/intel/common/block/uart/uart.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/bootblock/bootblock.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/me.c 21 files changed, 60 insertions(+), 103 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29573/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index e7e3298..3db7005 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -48,8 +48,16 @@ comment "device-specific UART" depends on HAVE_UART_SPECIAL +config FIXED_UART_FOR_CONSOLE + bool + help + Select to remove the prompt from UART_FOR_CONSOLE in case a + specific UART has to be used (e.g. when the platform code + performs dangerous configurations). + config UART_FOR_CONSOLE - int "Index for UART port to use for console" + int + prompt "Index for UART port to use for console" if !FIXED_UART_FOR_CONSOLE default 0 help Select an I/O port to use for serial console: diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig index 79ee3d0..a2ecf60 100644 --- a/src/mainboard/intel/leafhill/Kconfig +++ b/src/mainboard/intel/leafhill/Kconfig @@ -5,7 +5,7 @@ select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES - select UART_DEBUG + select INTEL_LPSS_UART_FOR_CONSOLE config MAINBOARD_DIR string @@ -28,7 +28,6 @@ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/leafhill.$(CONFIG_COREBOOT_ROMSIZE_KB).fmd" config UART_FOR_CONSOLE - int "Number of UART port to use for serial log" default 2 config NEED_IFWI diff --git a/src/mainboard/intel/minnow3/Kconfig b/src/mainboard/intel/minnow3/Kconfig index 531036a..a787a2d 100644 --- a/src/mainboard/intel/minnow3/Kconfig +++ b/src/mainboard/intel/minnow3/Kconfig @@ -5,7 +5,7 @@ select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES - select UART_DEBUG + select INTEL_LPSS_UART_FOR_CONSOLE config MAINBOARD_DIR string @@ -20,7 +20,6 @@ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/minnow3.fmd" config UART_FOR_CONSOLE - int "Number of UART port to use for serial log" default 2 config NEED_IFWI diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0c0fca9..4a412f1 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -169,14 +169,6 @@ int default 133 -config UART_DEBUG - bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE." - default n - select CONSOLE_SERIAL - select DRIVERS_UART - select DRIVERS_UART_8250MEM_32 - select NO_UART_ON_SUPERIO - # 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. config C_ENV_BOOTBLOCK_SIZE hex diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 6168f86..e4fe453 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -18,14 +18,14 @@ bootblock-y += mmap_boot.c bootblock-y += pmutil.c bootblock-y += spi.c -bootblock-$(CONFIG_UART_DEBUG) += uart.c +bootblock-y += uart.c romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gspi.c romstage-y += heci.c romstage-y += i2c.c -romstage-$(CONFIG_UART_DEBUG) += uart.c +romstage-y += uart.c romstage-y += memmap.c romstage-y += meminit.c ifeq ($(CONFIG_SOC_INTEL_GLK),y) @@ -42,7 +42,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += spi.c -smm-$(CONFIG_UART_DEBUG) += uart.c +smm-y += uart.c smm-y += elog.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c @@ -57,7 +57,7 @@ ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += mmap_boot.c -ramstage-$(CONFIG_UART_DEBUG) += uart.c +ramstage-y += uart.c ramstage-y += nhlt.c ramstage-y += spi.c ramstage-y += systemagent.c @@ -74,7 +74,7 @@ postcar-y += i2c.c postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c -postcar-$(CONFIG_UART_DEBUG) += uart.c +postcar-y += uart.c verstage-y += car.c verstage-y += i2c.c @@ -82,7 +82,7 @@ verstage-y += heci.c verstage-y += memmap.c verstage-y += mmap_boot.c -verstage-$(CONFIG_UART_DEBUG) += uart.c +verstage-y += uart.c verstage-y += pmutil.c verstage-y += reset.c verstage-y += spi.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index bc5c170..ccfe104 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -95,7 +95,7 @@ pmc_global_reset_enable(0); /* Prepare UART for serial console. */ - if (IS_ENABLED(CONFIG_UART_DEBUG)) + if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI)) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index c20097e..f36817f 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -279,7 +279,7 @@ static void fill_console_params(FSPM_UPD *mupd) { if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { - if (IS_ENABLED(CONFIG_UART_DEBUG)) { + if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) { mupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; /* use MMIO port type */ diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9452b6d..53e147d 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -77,23 +77,6 @@ select DISPLAY_FSP_VERSION_INFO select FSP_T_XIP if FSP_CAR -config UART_DEBUG - bool "Enable UART debug port." - default n - select CONSOLE_SERIAL - select BOOTBLOCK_CONSOLE - select DRIVERS_UART - select DRIVERS_UART_8250MEM_32 - select NO_UART_ON_SUPERIO - -config UART_FOR_CONSOLE - int "Index for LPSS UART port to use for console" - default 2 if DRIVERS_UART_8250MEM_32 - default 0 - help - Index for LPSS UART port to use for console: - 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 - config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 2452f50..bfee784 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -19,7 +19,7 @@ bootblock-y += spi.c bootblock-y += lpc.c bootblock-y += p2sb.c -bootblock-$(CONFIG_UART_DEBUG) += uart.c +bootblock-y += uart.c romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c romstage-y += gspi.c @@ -29,7 +29,7 @@ romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c -romstage-$(CONFIG_UART_DEBUG) += uart.c +romstage-y += uart.c ramstage-y += acpi.c ramstage-y += chip.c @@ -50,27 +50,27 @@ ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c -ramstage-$(CONFIG_UART_DEBUG) += uart.c +ramstage-y += uart.c ramstage-y += vr_config.c ramstage-y += sd.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c -smm-$(CONFIG_UART_DEBUG) += uart.c +smm-y += uart.c postcar-y += memmap.c postcar-y += pmutil.c postcar-y += i2c.c postcar-y += gspi.c postcar-y += spi.c -postcar-$(CONFIG_UART_DEBUG) += uart.c +postcar-y += uart.c verstage-y += gspi.c verstage-y += i2c.c verstage-y += pmutil.c verstage-y += spi.c -verstage-$(CONFIG_UART_DEBUG) += uart.c +verstage-y += uart.c ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y) bootblock-y += gpio_cnp_h.c diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 4eeef59..fcd815d 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -50,7 +50,7 @@ bootblock_pch_early_init(); bootblock_cpu_init(); pch_early_iorange_init(); - if (IS_ENABLED(CONFIG_UART_DEBUG)) + if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); } diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 3ef084a..d4427c2 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -173,8 +173,7 @@ uint16_t dec_rng, dec_en = 0; /* IO Decode Range */ - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) && - IS_ENABLED(CONFIG_UART_DEBUG)) { + if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) { dec_rng = COMA_RANGE | (COMB_RANGE << 4); dec_en = COMA_LPC_EN | COMB_LPC_EN; pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, dec_rng); diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig index f4a0e4e..e731465 100644 --- a/src/soc/intel/common/block/uart/Kconfig +++ b/src/soc/intel/common/block/uart/Kconfig @@ -15,3 +15,14 @@ hex help Clock m-divisor value for m/n divider + +config INTEL_LPSS_UART_FOR_CONSOLE + bool + depends on SOC_INTEL_COMMON_BLOCK_UART + select DRIVERS_UART_8250MEM_32 + select FIXED_UART_FOR_CONSOLE + help + Selected by mainboards that use one of the SoC's LPSS UARTS + for the coreboot console. + WARNING: UART_FOR_CONSOLE has to be set to a correct value, + otherwise wrong pad configurations might be selected. diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index f7235cf..f0b6b24 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -88,12 +88,11 @@ struct device *uart_get_device(void) { /* - * This function will get called even if UART_DEBUG config options is - * not selected. - * By default returning NULL in case CONFIG_UART_DEBUG option is not - * selected to avoid compilation errors. + * This function will get called even if INTEL_LPSS_UART_FOR_CONSOLE + * config option is not selected. + * By default return NULL in this case to avoid compilation errors. */ - if (!IS_ENABLED(CONFIG_UART_DEBUG)) + if (!IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) return NULL; int console_index = uart_get_valid_index(); @@ -157,7 +156,8 @@ pci_dev_read_resources(dev); /* Set the configured UART base address for the debug port */ - if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) { + if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE) && + uart_is_debug_controller(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); /* Need to set the base and size for the resource allocator. */ res->base = UART_BASE(CONFIG_UART_FOR_CONSOLE); diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index c4ee841..df2dbc3 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -62,23 +62,6 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO -config UART_DEBUG - bool "Enable UART debug port." - default n - select CONSOLE_SERIAL - select BOOTBLOCK_CONSOLE - select DRIVERS_UART - select DRIVERS_UART_8250MEM_32 - select NO_UART_ON_SUPERIO - -config UART_FOR_CONSOLE - int "Index for LPSS UART port to use for console" - default 2 if DRIVERS_UART_8250MEM_32 - default 0 - help - Index for LPSS UART port to use for console: - 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 - config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index a81edd4..74c9182 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -20,7 +20,7 @@ bootblock-y += spi.c bootblock-y += lpc.c bootblock-y += p2sb.c -bootblock-$(CONFIG_UART_DEBUG) += uart.c +bootblock-y += uart.c romstage-y += gpio.c romstage-y += gspi.c @@ -30,7 +30,7 @@ romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c -romstage-$(CONFIG_UART_DEBUG) += uart.c +romstage-y += uart.c ramstage-y += acpi.c ramstage-y += chip.c @@ -52,27 +52,27 @@ ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c -ramstage-$(CONFIG_UART_DEBUG) += uart.c +ramstage-y += uart.c ramstage-y += sd.c smm-y += gpio.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c -smm-$(CONFIG_UART_DEBUG) += uart.c +smm-y += uart.c postcar-y += memmap.c postcar-y += pmutil.c postcar-y += i2c.c postcar-y += gspi.c postcar-y += spi.c -postcar-$(CONFIG_UART_DEBUG) += uart.c +postcar-y += uart.c verstage-y += gspi.c verstage-y += i2c.c verstage-y += pmutil.c verstage-y += spi.c -verstage-$(CONFIG_UART_DEBUG) += uart.c +verstage-y += uart.c CPPFLAGS_common += -I$(src)/soc/intel/icelake CPPFLAGS_common += -I$(src)/soc/intel/icelake/include diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index 40c2d41..d26fa42 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -32,7 +32,7 @@ bootblock_pch_early_init(); bootblock_cpu_init(); pch_early_iorange_init(); - if (IS_ENABLED(CONFIG_UART_DEBUG)) + if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); } diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 96722e2..ee07d92 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -151,8 +151,7 @@ uint16_t dec_rng, dec_en = 0; /* IO Decode Range */ - if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) && - IS_ENABLED(CONFIG_UART_DEBUG)) { + if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) { dec_rng = COMA_RANGE | (COMB_RANGE << 4); dec_en = COMA_LPC_EN | COMB_LPC_EN; pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, dec_rng); diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 2db8217..834422d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -191,22 +191,6 @@ string default "8086,0406" -config UART_DEBUG - bool "Enable UART debug port." - default n - select CONSOLE_SERIAL - select DRIVERS_UART - select DRIVERS_UART_8250MEM_32 - select NO_UART_ON_SUPERIO - -config UART_FOR_CONSOLE - int "Index for LPSS UART port to use for console" - default 2 if DRIVERS_UART_8250MEM - default 0 - help - Index for LPSS UART port to use for console: - 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 - config SKYLAKE_SOC_PCH_H bool default n diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 480c71e..ee2c928 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -22,13 +22,13 @@ bootblock-y += pmutil.c bootblock-y += spi.c bootblock-y += lpc.c -bootblock-$(CONFIG_UART_DEBUG) += uart.c +bootblock-y += uart.c verstage-y += gspi.c verstage-y += pmutil.c verstage-y += i2c.c verstage-y += spi.c -verstage-$(CONFIG_UART_DEBUG) += uart.c +verstage-y += uart.c romstage-y += gpio.c romstage-y += gspi.c @@ -40,7 +40,7 @@ romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += spi.c -romstage-$(CONFIG_UART_DEBUG) += uart.c +romstage-y += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c @@ -67,7 +67,7 @@ ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += thermal.c -ramstage-$(CONFIG_UART_DEBUG) += uart.c +ramstage-y += uart.c ramstage-y += vr_config.c smm-y += elog.c @@ -75,13 +75,13 @@ smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c -smm-$(CONFIG_UART_DEBUG) += uart.c +smm-y += uart.c postcar-y += memmap.c postcar-y += gspi.c postcar-y += spi.c postcar-y += i2c.c -postcar-$(CONFIG_UART_DEBUG) += uart.c +postcar-y += uart.c # Skylake D0 diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index a2bcaaf..acf25ff 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -32,7 +32,7 @@ bootblock_cpu_init(); pch_early_iorange_init(); - if (IS_ENABLED(CONFIG_UART_DEBUG)) + if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); } diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 6baa568..18c07c4 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -240,7 +240,7 @@ * Print ME version only if UART debugging is enabled. Else, it takes ~1 * second to talk to ME and get this information. */ - if (!IS_ENABLED(CONFIG_UART_DEBUG)) + if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) return; hfs.data = me_read_config32(PCI_ME_HFSTS1); -- To view, visit https://review.coreboot.org/29573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b Gerrit-Change-Number: 29573 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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coreboot-gerrit November 2018