coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number
by Kevin Chiu (Code Review) 09 Nov '18

09 Nov '18

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/29557 Change subject: grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number ...................................................................... grunt: Update Samsung K4A8G165WC-BCTD SPD Module Part Number Correct SPD Module Part Number to "K4A8G165WC-BCTD" from "M471A5244CB0-CTD". BUG=none BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage mosys memory spd print all 0 | DDR4 | SO-DIMM 0 | 1-78: Samsung | 00000000 | K4A8G165WC-BCTD 0 | 4096 | 1 | 64 0 | DDR4-1333, DDR4-1600, DDR4-2400 Change-Id: I29505d3eece2283579499a0afc424c4a28017fa5 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29557/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex index 2688254..d03dc5b 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/samsung-K4A8G165WC-BCTD.spd.hex @@ -19,8 +19,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 35 32 -34 34 43 42 30 2D 43 54 44 20 20 20 20 00 80 CE +80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36 +35 57 43 2D 42 43 54 44 20 20 20 20 20 00 80 CE 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/29557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I29505d3eece2283579499a0afc424c4a28017fa5 Gerrit-Change-Number: 29557 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

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Change in coreboot[master]: siemens/mc_apl4: Disable CLKREQ of PCIe root ports
by Werner Zeh (Code Review) 09 Nov '18

09 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29556 ) Change subject: siemens/mc_apl4: Disable CLKREQ of PCIe root ports ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4 Gerrit-Change-Number: 29556 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Nov 2018 08:37:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
by Werner Zeh (Code Review) 09 Nov '18

09 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29549 ) Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/29549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Gerrit-Change-Number: 29549 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Nov 2018 08:30:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
by Mario Scheithauer (Code Review) 09 Nov '18

09 Nov '18

Hello Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29549 to look at the new patch set (#5). Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges ...................................................................... siemens/mc_apl3: Disable PCI clock outputs on XIO bridges On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c 1 file changed, 17 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29549/5 -- To view, visit https://review.coreboot.org/29549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Gerrit-Change-Number: 29549 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: siemens/mc_apl4: Disable CLKREQ of PCIe root ports
by Mario Scheithauer (Code Review) 09 Nov '18

09 Nov '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29556 Change subject: siemens/mc_apl4: Disable CLKREQ of PCIe root ports ...................................................................... siemens/mc_apl4: Disable CLKREQ of PCIe root ports All PCIe root ports of this mainboard do not have an associated CLKREQ signal. Therefore the ports are marked with "CLKREQ_DISABLED". Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb 1 file changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/29556/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index f3e8a77..a2a2ba1 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -6,11 +6,12 @@ register "sci_irq" = "SCIS_IRQ10" - # Disable unused clkreq of PCIe root ports - register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge - register "pcie_rp_clkreq_pin[1]" = "2" # FPGA - register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY - register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY + # Disable all clkreq of PCIe root ports as SMARC interface do not + # have this pins. + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" -- To view, visit https://review.coreboot.org/29556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4 Gerrit-Change-Number: 29556 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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Change in coreboot[master]: soc/intel/cannonlake: Remove SmbusEnable
by Furquan Shaikh (Code Review) 09 Nov '18

09 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29552 ) Change subject: soc/intel/cannonlake: Remove SmbusEnable ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a Gerrit-Change-Number: 29552 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Nov 2018 05:56:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/cannonlake: Remove SmbusEnable from devicetree
by Furquan Shaikh (Code Review) 09 Nov '18

09 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29551 ) Change subject: mb/cannonlake: Remove SmbusEnable from devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ece6768da4c517747af12a07012583575816ae1 Gerrit-Change-Number: 29551 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Nov 2018 05:56:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz
by Gaggery Tsai (Code Review) 09 Nov '18

09 Nov '18

Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/29553 ) Change subject: mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz ...................................................................... Patch Set 1: Code-Review+1 (2 comments) https://review.coreboot.org/#/c/29553/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29553/1//COMMIT_MSG@15 PS1, Line 15: Data Hold_time larger than 260ns (32 * 8.3ns = 265ns) It shouldn't be 260ns. According to Grant, it should be 0ns for fast plus mode, please double check. Otherwise, the setting now is 20 --> 20*8.3 would less than 265ns. https://review.coreboot.org/#/c/29553/1//COMMIT_MSG@34 PS1, Line 34: Verified by gaggery.tsai(a)intel.corp-partner.google.com. : See b/78601949 comment #177 (and many comments up to this one) : : Verified by grundler(a)chromium.org. : See b/78601949 comment #155, #100, et al. Do we need this in comment? -- To view, visit https://review.coreboot.org/29553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38 Gerrit-Change-Number: 29553 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Fri, 09 Nov 2018 05:22:31 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86: Fix car_active for CONFIG_NO_CAR_GLOBAL_MIGRATION
by Furquan Shaikh (Code Review) 09 Nov '18

09 Nov '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/29555 Change subject: arch/x86: Fix car_active for CONFIG_NO_CAR_GLOBAL_MIGRATION ...................................................................... arch/x86: Fix car_active for CONFIG_NO_CAR_GLOBAL_MIGRATION Change 76ab2b7 ("arch/x86: allow global .bss objects without CAR_GLOBAL") allowed use of global .bss objects and hence moved around the macros resulting in car_active returning 0 even for those boards where CAR is actually active but do not require global migration. This resulted in boards getting stuck when doing a reset in verstage because the code flow incorrectly assumed that there was no CAR active and hence triggered a cache invalidate. This change fixes the above issue by returning 1 for car_active if ENV_CACHE_AS_RAM is set even if global migration is not required. BUG=b:109717603 TEST=Verified that board reset does not trigger cache invalidate in verstage and does not result in board hang. Change-Id: I182f3e4277c57d6c50f7fcac2be72514896b3c61 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/arch/x86/include/arch/early_variables.h 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/29555/1 diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index e95a45c..68cb9ff 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -79,12 +79,28 @@ } #else + +/* + * We might end up here if: + * 1. ENV_CACHE_AS_RAM is not set for the stage or + * 2. ENV_CACHE_AS_RAM is set for the stage but CONFIG_NO_CAR_GLOBAL_MIGRATION + * is also set. In this case, there is no need to migrate CAR global + * variables. But, since we might still be running out of CAR, car_active needs + * to return 1 if ENV_CACHE_AS_RAM is set. + */ + #define CAR_GLOBAL static inline void *car_get_var_ptr(void *var) { return var; } + +#if ENV_CACHE_AS_RAM +static inline int car_active(void) { return 1; } +#else static inline int car_active(void) { return 0; } +#endif /* ENV_CACHE_AS_RAM */ + #define car_get_var(var) (var) #define car_sync_var(var) (var) #define car_set_var(var, val) (var) = (val) -#endif +#endif /* ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) */ #endif -- To view, visit https://review.coreboot.org/29555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I182f3e4277c57d6c50f7fcac2be72514896b3c61 Gerrit-Change-Number: 29555 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/skylake: Drop FSP_CAR options
by Boon Tiong Teo (Code Review) 09 Nov '18

09 Nov '18

Boon Tiong Teo has posted comments on this change. ( https://review.coreboot.org/29533 ) Change subject: soc/intel/skylake: Drop FSP_CAR options ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29533/1/src/soc/intel/skylake/Kconfig File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/#/c/29533/1/src/soc/intel/skylake/Kconfig@105 PS1, Line 105: select SKIP_FSP_CAR If we want to use FSP_CAR, what is the right config how to set? Is that ok to use mb config to override those config? -- To view, visit https://review.coreboot.org/29533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28 Gerrit-Change-Number: 29533 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boon Tiong Teo <boon.tiong.teo(a)intel.com> Gerrit-Comment-Date: Fri, 09 Nov 2018 03:35:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit November 2018