coreboot-gerrit November 2018

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Change in coreboot[master]: siemens/mc_apl3: Set Full Reset Bit into Reset Control Register
by Werner Zeh (Code Review) 08 Nov '18

08 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29530 ) Change subject: siemens/mc_apl3: Set Full Reset Bit into Reset Control Register ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/29530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b Gerrit-Change-Number: 29530 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 12:52:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/grunt/aleena: Update H1/TP/TS i2c timings
by Lucas Chen (Code Review) 08 Nov '18

08 Nov '18

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/29548 Change subject: google/grunt/aleena: Update H1/TP/TS i2c timings ...................................................................... google/grunt/aleena: Update H1/TP/TS i2c timings After adjustment on aleena EVT Audio: 390.0 KHz H1: 390.0 KHz TP: 399.8 KHz TS: 399.8 kHz BUG=b:116306959 BRANCH=master TEST=emerge-grunt coreboot, scope measuring. Change-Id: I6f621508ce2dbb1b9dcdf529ac35afc80d485f53 Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/aleena/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/29548/1 diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index 5438e6d..8f2f985 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -32,22 +32,22 @@ register "i2c[1]" = "{ .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 84, + .rise_time_ns = 45, .fall_time_ns = 4, }" # Enable I2C2 for trackpad, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 117, - .fall_time_ns = 113, + .rise_time_ns = 26, + .fall_time_ns = 11, }" # Enable I2C3 for touchscreen at 400kHz register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 82, - .fall_time_ns = 67, + .rise_time_ns = 20, + .fall_time_ns = 19, }" register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ -- To view, visit https://review.coreboot.org/29548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6f621508ce2dbb1b9dcdf529ac35afc80d485f53 Gerrit-Change-Number: 29548 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: [WIP]mb/opencellular/elgon: Enable write protection
by Philipp Deppenwiese (Code Review) 08 Nov '18

08 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29532 ) Change subject: [WIP]mb/opencellular/elgon: Enable write protection ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29532/1/src/mainboard/opencellular/elgon/bo… File src/mainboard/opencellular/elgon/bootblock.c: https://review.coreboot.org/#/c/29532/1/src/mainboard/opencellular/elgon/bo… PS1, Line 73: u8 reg8 = 0; Why another check before spi_flash_is_write_protected() ? -- To view, visit https://review.coreboot.org/29532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6a940c69ecb1dfd9704b2101c263570bebc5540e Gerrit-Change-Number: 29532 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 12:00:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macros
by Patrick Georgi (Code Review) 08 Nov '18

08 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29525 ) Change subject: nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macros ...................................................................... nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macros Change-Id: I6d161e9e44ebd284e229ea38b6e23d571aa7bf1e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/29525 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c 1 file changed, 5 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index cd1f165..34d1c1f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -39,6 +39,7 @@ #include <southbridge/amd/common/reset.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> +#include <cpu/x86/mtrr.h> #include <arch/acpi.h> #include <string.h> #include <device/dram/ddr3.h> @@ -3577,10 +3578,10 @@ mctHookBeforeAnyTraining(pMCTstat, pDCTstatA); if (!is_fam15h()) { /* TODO: should be in mctHookBeforeAnyTraining */ - _WRMSR(0x26C, 0x04040404, 0x04040404); - _WRMSR(0x26D, 0x04040404, 0x04040404); - _WRMSR(0x26E, 0x04040404, 0x04040404); - _WRMSR(0x26F, 0x04040404, 0x04040404); + _WRMSR(MTRR_FIX_4K_E0000, 0x04040404, 0x04040404); + _WRMSR(MTRR_FIX_4K_E8000, 0x04040404, 0x04040404); + _WRMSR(MTRR_FIX_4K_F0000, 0x04040404, 0x04040404); + _WRMSR(MTRR_FIX_4K_F8000, 0x04040404, 0x04040404); } if (nv_DQSTrainCTL) { -- To view, visit https://review.coreboot.org/29525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I6d161e9e44ebd284e229ea38b6e23d571aa7bf1e Gerrit-Change-Number: 29525 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macros
by Patrick Georgi (Code Review) 08 Nov '18

08 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/29525 ) Change subject: nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macros ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/29525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6d161e9e44ebd284e229ea38b6e23d571aa7bf1e Gerrit-Change-Number: 29525 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 11:36:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST
by Patrick Georgi (Code Review) 08 Nov '18

08 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29538 ) Change subject: mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST ...................................................................... mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ storm after S3 resume and hence configuring GPP_D9 and GPP_D10 to use PLTRST. BUG=b:119202293 TEST=none Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/29538 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/nocturne/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 9aa7706..70b748b 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -180,9 +180,9 @@ /* D8 : ISH_I2C1_SCL ==> NC */ PAD_CFG_NC(GPP_D8), /* D9 : ISH_SPI_CS# ==> PCH_SR1_INT_L */ - PAD_CFG_GPI_APIC(GPP_D9, NONE, DEEP), + PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> PCH_SR0_INT_L */ - PAD_CFG_GPI_APIC(GPP_D10, NONE, DEEP), + PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST), /* D11 : ISH_SPI_MISO ==> NC */ PAD_CFG_NC(GPP_D11), /* D12 : ISH_SPI_MOSI ==> NC */ -- To view, visit https://review.coreboot.org/29538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43 Gerrit-Change-Number: 29538 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: include/program_loading: Add POSTCAR prog type
by Philipp Deppenwiese (Code Review) 08 Nov '18

08 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29545 ) Change subject: include/program_loading: Add POSTCAR prog type ...................................................................... Patch Set 3: @patrick fixed -- To view, visit https://review.coreboot.org/29545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Gerrit-Change-Number: 29545 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Nov 2018 11:33:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: include/program_loading: Add POSTCAR prog type
by Philipp Deppenwiese (Code Review) 08 Nov '18

08 Nov '18

Hello Werner Zeh, Patrick Rudolph, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29545 to look at the new patch set (#3). Change subject: include/program_loading: Add POSTCAR prog type ...................................................................... include/program_loading: Add POSTCAR prog type Now postcar is a standalone stage give it a proper type. Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/arch/x86/postcar_loader.c M src/include/program_loading.h 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29545/3 -- To view, visit https://review.coreboot.org/29545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8 Gerrit-Change-Number: 29545 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11
by Patrick Georgi (Code Review) 08 Nov '18

08 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29429 ) Change subject: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11 ...................................................................... mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11 GPP_C11 (FPMCU_INT_L) was set to DEEP, causing problems with S3. Changed GPP_C11 configuration to use PLTRST instead. BUG=b:114196791 TEST=Build, flash, boot nocturne, log in to kernel and execute the following two commands and verify it passes : echo 0 > /var/lib/power_manager/suspend_to_idle && restart powerd sudo suspend_stress_test -c 2 Change-Id: I008532fce963c51a435378001440ac72b5ebfffc Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/29429 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 16ff982..9aa7706 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -135,7 +135,7 @@ /* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> FPMCU_INT */ - PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, DEEP), + PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, PLTRST), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ -- To view, visit https://review.coreboot.org/29429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I008532fce963c51a435378001440ac72b5ebfffc Gerrit-Change-Number: 29429 Gerrit-PatchSet: 5 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variants/nami: add the hynix memory parts
by Patrick Georgi (Code Review) 08 Nov '18

08 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29524 ) Change subject: mb/google/poppy/variants/nami: add the hynix memory parts ...................................................................... mb/google/poppy/variants/nami: add the hynix memory parts add the memory parts as ram id 10: hynix_dimm_H5ANAG6NAFR-UHC BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I137259b88f39779768a58959a2dcc565645eee6d Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29524 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- A src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NAFR-UHC.spd.hex M src/mainboard/google/poppy/variants/nami/Makefile.inc 2 files changed, 33 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved Ren Kuo: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NAFR-UHC.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NAFR-UHC.spd.hex new file mode 100644 index 0000000..9a702ce --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NAFR-UHC.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 44 19 00 08 00 40 00 03 02 03 00 00 +00 00 07 0D F8 0F 00 00 6E 6E 6E 11 00 6E 20 08 +00 05 70 03 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 D6 B2 F3 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 4D 41 34 32 35 53 +36 41 46 52 36 4E 2D 55 48 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index ae33c27..690b9c8 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -11,7 +11,7 @@ SPD_SOURCES += samsung_dimm_K4A4G165WE-BCRC # 0b0111 SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b1000 SPD_SOURCES += samsung_dimm_K4AAG165WB-MCRC # 0b1001 -SPD_SOURCES += empty_ddr4 # 0b1010 +SPD_SOURCES += hynix_dimm_H5ANAG6NAFR-UHC # 0b1010 SPD_SOURCES += empty_ddr4 # 0b1011 SPD_SOURCES += empty_ddr4 # 0b1100 SPD_SOURCES += micron_dimm_MT40A1G16KNR-075E # 0b1101 -- To view, visit https://review.coreboot.org/29524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I137259b88f39779768a58959a2dcc565645eee6d Gerrit-Change-Number: 29524 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit November 2018