coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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1699 discussions

Change in coreboot[master]: nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macros
by Elyes HAOUAS (Code Review) 07 Nov '18

07 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29525 Change subject: nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macros ...................................................................... nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macros Change-Id: I6d161e9e44ebd284e229ea38b6e23d571aa7bf1e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/29525/1 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index cd1f165..05582fc 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -39,6 +39,7 @@ #include <southbridge/amd/common/reset.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> #include <arch/acpi.h> #include <string.h> #include <device/dram/ddr3.h> @@ -3577,10 +3578,10 @@ mctHookBeforeAnyTraining(pMCTstat, pDCTstatA); if (!is_fam15h()) { /* TODO: should be in mctHookBeforeAnyTraining */ - _WRMSR(0x26C, 0x04040404, 0x04040404); - _WRMSR(0x26D, 0x04040404, 0x04040404); - _WRMSR(0x26E, 0x04040404, 0x04040404); - _WRMSR(0x26F, 0x04040404, 0x04040404); + _WRMSR(MTRR_FIX_4K_E0000, 0x04040404, 0x04040404); + _WRMSR(MTRR_FIX_4K_E8000, 0x04040404, 0x04040404); + _WRMSR(MTRR_FIX_4K_F0000, 0x04040404, 0x04040404); + _WRMSR(MTRR_FIX_4K_F8000, 0x04040404, 0x04040404); } if (nv_DQSTrainCTL) { -- To view, visit https://review.coreboot.org/29525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6d161e9e44ebd284e229ea38b6e23d571aa7bf1e Gerrit-Change-Number: 29525 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/google/poppy/variants/nami: add the hynix memory parts
by Ren Kuo (Code Review) 07 Nov '18

07 Nov '18

Ren Kuo has posted comments on this change. ( https://review.coreboot.org/29524 ) Change subject: mb/google/poppy/variants/nami: add the hynix memory parts ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/29524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I137259b88f39779768a58959a2dcc565645eee6d Gerrit-Change-Number: 29524 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 07 Nov 2018 05:53:04 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: add the hynix memory parts
by Ren Kuo (Code Review) 07 Nov '18

07 Nov '18

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/29524 Change subject: mb/google/poppy/variants/nami: add the hynix memory parts ...................................................................... mb/google/poppy/variants/nami: add the hynix memory parts add the memory parts as ram id 10: hynix_dimm_H5ANAG6NAFR-UHC BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I137259b88f39779768a58959a2dcc565645eee6d Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- A src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NAFR-UHC.spd.hex M src/mainboard/google/poppy/variants/nami/Makefile.inc 2 files changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29524/1 diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NAFR-UHC.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NAFR-UHC.spd.hex new file mode 100644 index 0000000..9a702ce --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NAFR-UHC.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 44 19 00 08 00 40 00 03 02 03 00 00 +00 00 07 0D F8 0F 00 00 6E 6E 6E 11 00 6E 20 08 +00 05 70 03 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 D6 B2 F3 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 4D 41 34 32 35 53 +36 41 46 52 36 4E 2D 55 48 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index ae33c27..690b9c8 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -11,7 +11,7 @@ SPD_SOURCES += samsung_dimm_K4A4G165WE-BCRC # 0b0111 SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b1000 SPD_SOURCES += samsung_dimm_K4AAG165WB-MCRC # 0b1001 -SPD_SOURCES += empty_ddr4 # 0b1010 +SPD_SOURCES += hynix_dimm_H5ANAG6NAFR-UHC # 0b1010 SPD_SOURCES += empty_ddr4 # 0b1011 SPD_SOURCES += empty_ddr4 # 0b1100 SPD_SOURCES += micron_dimm_MT40A1G16KNR-075E # 0b1101 -- To view, visit https://review.coreboot.org/29524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I137259b88f39779768a58959a2dcc565645eee6d Gerrit-Change-Number: 29524 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: [DoNotMerge]soc/intel/cannonlake: Enable Debugging
by Lijian Zhao (Code Review) 07 Nov '18

07 Nov '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/29523 Change subject: [DoNotMerge]soc/intel/cannonlake: Enable Debugging ...................................................................... [DoNotMerge]soc/intel/cannonlake: Enable Debugging Change-Id: I5986007f3f36bc7fdc8e427fa311f98890069cd3 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29523/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index e3b9680..4eaec99 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -8,6 +8,9 @@ register "gpe0_dw1" = "PMC_GPP_C" register "gpe0_dw2" = "PMC_GPP_D" + #Debug + register "DebugConsent" = DebugConsent_DCI_DBC + # EC host command ranges register "gen1_dec" = "0x00040931" # 0x930-0x937 register "gen2_dec" = "0x00040941" # 0x940-0x947 diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 8506214..9c57b12 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -61,6 +61,7 @@ m_cfg->PchIshEnable = 0; else m_cfg->PchIshEnable = dev->enabled; + m_cfg->PchTraceHubMode = 2; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/29523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5986007f3f36bc7fdc8e427fa311f98890069cd3 Gerrit-Change-Number: 29523 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: HACK: Julius' changes for v18
by Julius Werner (Code Review) 07 Nov '18

07 Nov '18

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/29521 Change subject: HACK: Julius' changes for v18 ...................................................................... HACK: Julius' changes for v18 Change-Id: Ie8c222c152b2f6925c6c5a391a2c7b51e36d54df Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/arm64/Makefile.inc M src/soc/qualcomm/sdm845/Makefile.inc 2 files changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/29521/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 5f8b092..6bb7196 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -156,8 +156,6 @@ # Build ARM Trusted Firmware (BL31) ifeq ($(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE),y) -# temporary change, soc makefile process would pack pre-built bl31 -ifneq ($(CONFIG_SOC_QUALCOMM_SDM845),y) ifeq ($(CONFIG_ARM64_BL31_EXTERNAL_FILE),"") @@ -237,8 +235,6 @@ endif # CONFIG_ARM64_USE_SECURE_OS -endif # CONFIG_SOC_QUALCOMM_845 - endif # CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE endif # CONFIG_ARCH_RAMSTAGE_ARM64 diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index 711c62d..6249040 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -166,17 +166,6 @@ endif ################################################################################ -BL31_FILE := $(SDM845_BLOB)/bl31.elf -bl31_file := $(shell ls $(BL31_FILE)) -ifneq (,$(findstring $(BL31_FILE),$(bl31_file))) - BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31 - $(BL31_CBFS)-file := $(BL31_FILE) - $(BL31_CBFS)-type := payload - $(BL31_CBFS)-compression := none - cbfs-files-y += $(BL31_CBFS) -endif - -################################################################################ QC_SEC_FILE := $(SDM845_BLOB)/qc_sec.mbn qc_sec_file := $(shell ls $(QC_SEC_FILE)) ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) -- To view, visit https://review.coreboot.org/29521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie8c222c152b2f6925c6c5a391a2c7b51e36d54df Gerrit-Change-Number: 29521 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>

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Change in coreboot[master]: mb/google/sarien: Program HD Audio SVID/SSID
by build bot (Jenkins) (Code Review) 06 Nov '18

06 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29492 ) Change subject: mb/google/sarien: Program HD Audio SVID/SSID ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/29492/2/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h: https://review.coreboot.org/#/c/29492/2/src/mainboard/google/sarien/variant… PS2, Line 25: {{{PCI_SUBSYSTEM_VENDOR_ID, HDA_FUNC, PCH_DEV_SLOT_LPC, 0, 0, 0, 0 }}, space required after that close brace '}' https://review.coreboot.org/#/c/29492/2/src/mainboard/google/sarien/variant… File src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h: https://review.coreboot.org/#/c/29492/2/src/mainboard/google/sarien/variant… PS2, Line 25: {{{PCI_SUBSYSTEM_VENDOR_ID, HDA_FUNC, PCH_DEV_SLOT_LPC, 0, 0, 0, 0 }}, space required after that close brace '}' -- To view, visit https://review.coreboot.org/29492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3c08da2daf8539864ea3f9aa04ccf488e2844da5 Gerrit-Change-Number: 29492 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Nov 2018 23:58:28 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd: Convert from AMD units to coreboot units
by Richard Spiegel (Code Review) 06 Nov '18

06 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29520 to look at the new patch set (#2). Change subject: soc/amd: Convert from AMD units to coreboot units ...................................................................... soc/amd: Convert from AMD units to coreboot units There are several files under soc/amd that use units defined by file porting.h. These units use upper case, and are not recognized by checkpatch, thus causing problems when defining a pointer (request to use space before and after the star symbol). These are the definitions from porting.h showing the units that this patch will change and their coreboot definitions (not all are actually used): typedef uintptr_t UINTN; typedef int64_t INT64; typedef uint64_t UINT64; typedef int32_t INT32; typedef uint32_t UINT32; typedef int16_t INT16; typedef uint16_t UINT16; typedef int8_t INT8; typedef uint8_t UINT8; typedef char CHAR8; typedef unsigned short CHAR16; typedef unsigned char BOOLEAN; typedef void VOID; BUG=b:118775313 TEST=Build and boot grunt. Change-Id: Ic1bd64d6224a030a65d23decabf0e602cee02871 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h M src/soc/amd/common/block/include/amdblocks/agesawrapper.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/common/block/pi/heapmanager.c M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/amd/stoneyridge/northbridge.c 7 files changed, 119 insertions(+), 102 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/29520/2 -- To view, visit https://review.coreboot.org/29520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic1bd64d6224a030a65d23decabf0e602cee02871 Gerrit-Change-Number: 29520 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd: Convert from AMD units to coreboot units
by build bot (Jenkins) (Code Review) 06 Nov '18

06 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29520 ) Change subject: soc/amd: Convert from AMD units to coreboot units ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29520/1/src/soc/amd/common/block/include/am… File src/soc/amd/common/block/include/amdblocks/agesawrapper.h: https://review.coreboot.org/#/c/29520/1/src/soc/amd/common/block/include/am… PS1, Line 54: void OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/29520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic1bd64d6224a030a65d23decabf0e602cee02871 Gerrit-Change-Number: 29520 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Nov 2018 23:35:15 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd: Convert from AMD units to coreboot units
by Richard Spiegel (Code Review) 06 Nov '18

06 Nov '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29520 Change subject: soc/amd: Convert from AMD units to coreboot units ...................................................................... soc/amd: Convert from AMD units to coreboot units There are several files under soc/amd that use units defined by file porting.h. These units use upper case, and are not recognized by checkpatch, thus causing problems when defining a pointer (request to use space before and after the star symbol). These are the definitions from porting.h showing the units that this patch will change and their coreboot definitions (not all are actually used): typedef uintptr_t UINTN; typedef int64_t INT64; typedef uint64_t UINT64; typedef int32_t INT32; typedef uint32_t UINT32; typedef int16_t INT16; typedef uint16_t UINT16; typedef int8_t INT8; typedef uint8_t UINT8; typedef char CHAR8; typedef unsigned short CHAR16; typedef unsigned char BOOLEAN; typedef void VOID; BUG=b:118775313 TEST=Build and boot grunt. Change-Id: Ic1bd64d6224a030a65d23decabf0e602cee02871 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h M src/soc/amd/common/block/include/amdblocks/agesawrapper.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/common/block/pi/heapmanager.c M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/amd/stoneyridge/northbridge.c 7 files changed, 119 insertions(+), 102 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/29520/1 diff --git a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h index 3d5ae8f..829630b 100644 --- a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h +++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h @@ -23,51 +23,59 @@ #define BSP_STACK_BASE_ADDR 0x30000 typedef struct _BIOS_HEAP_MANAGER { - UINT32 StartOfAllocatedNodes; - UINT32 StartOfFreedNodes; + uint32_t StartOfAllocatedNodes; + uint32_t StartOfFreedNodes; } BIOS_HEAP_MANAGER; typedef struct _BIOS_BUFFER_NODE { - UINT32 BufferHandle; - UINT32 BufferSize; - UINT32 NextNodeOffset; + uint32_t BufferHandle; + uint32_t BufferSize; + uint32_t NextNodeOffset; } BIOS_BUFFER_NODE; -AGESA_STATUS agesa_GetTempHeapBase(UINT32 Func, UINTN Data, VOID *ConfigPtr); -AGESA_STATUS agesa_HeapRebase(UINT32 Func, UINTN Data, VOID *ConfigPtr); +AGESA_STATUS agesa_GetTempHeapBase(uint32_t Func, uintptr_t Data, + void *ConfigPtr); +AGESA_STATUS agesa_HeapRebase(uint32_t Func, uintptr_t Data, void *ConfigPtr); -AGESA_STATUS agesa_AllocateBuffer(UINT32 Func, UINTN Data, VOID *ConfigPtr); -AGESA_STATUS agesa_DeallocateBuffer(UINT32 Func, UINTN Data, VOID *ConfigPtr); -AGESA_STATUS agesa_LocateBuffer(UINT32 Func, UINTN Data, VOID *ConfigPtr); +AGESA_STATUS agesa_AllocateBuffer(uint32_t Func, uintptr_t Data, + void *ConfigPtr); +AGESA_STATUS agesa_DeallocateBuffer(uint32_t Func, uintptr_t Data, + void *ConfigPtr); +AGESA_STATUS agesa_LocateBuffer(uint32_t Func, uintptr_t Data, void *ConfigPtr); -AGESA_STATUS agesa_NoopUnsupported(UINT32 Func, UINTN Data, VOID *ConfigPtr); -AGESA_STATUS agesa_NoopSuccess(UINT32 Func, UINTN Data, VOID *ConfigPtr); -AGESA_STATUS agesa_EmptyIdsInitData(UINT32 Func, UINTN Data, VOID *ConfigPtr); -AGESA_STATUS agesa_Reset(UINT32 Func, UINTN Data, VOID *ConfigPtr); -AGESA_STATUS agesa_RunFuncOnAp(UINT32 Func, UINTN Data, VOID *ConfigPtr); -AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, - VOID *ConfigPrt); +AGESA_STATUS agesa_NoopUnsupported(uint32_t Func, uintptr_t Data, + void *ConfigPtr); +AGESA_STATUS agesa_NoopSuccess(uint32_t Func, uintptr_t Data, void *ConfigPtr); +AGESA_STATUS agesa_EmptyIdsInitData(uint32_t Func, uintptr_t Data, + void *ConfigPtr); +AGESA_STATUS agesa_Reset(uint32_t Func, uintptr_t Data, void *ConfigPtr); +AGESA_STATUS agesa_RunFuncOnAp(uint32_t Func, uintptr_t Data, void *ConfigPtr); +AGESA_STATUS agesa_GfxGetVbiosImage(uint32_t Func, uintptr_t FchData, + void *ConfigPrt); -AGESA_STATUS agesa_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr); -AGESA_STATUS agesa_RunFcnOnAllAps(UINT32 Func, UINTN Data, VOID *ConfigPtr); -AGESA_STATUS agesa_PcieSlotResetControl(UINT32 Func, UINTN Data, - VOID *ConfigPtr); -AGESA_STATUS agesa_WaitForAllApsFinished(UINT32 Func, UINTN Data, - VOID *ConfigPtr); -AGESA_STATUS agesa_IdleAnAp(UINT32 Func, UINTN Data, VOID *ConfigPtr); +AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr); +AGESA_STATUS agesa_RunFcnOnAllAps(uint32_t Func, uintptr_t Data, + void *ConfigPtr); +AGESA_STATUS agesa_PcieSlotResetControl(uint32_t Func, uintptr_t Data, + void *ConfigPtr); +AGESA_STATUS agesa_WaitForAllApsFinished(uint32_t Func, uintptr_t Data, + void *ConfigPtr); +AGESA_STATUS agesa_IdleAnAp(uint32_t Func, uintptr_t Data, void *ConfigPtr); -AGESA_STATUS GetBiosCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr); +AGESA_STATUS GetBiosCallout(uint32_t Func, uintptr_t Data, void *ConfigPtr); -AGESA_STATUS agesa_fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr); -AGESA_STATUS agesa_fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr); -AGESA_STATUS agesa_HaltThisAp(UINT32 Func, UINTN Data, VOID *ConfigPtr); +AGESA_STATUS agesa_fch_initreset(uint32_t Func, uintptr_t FchData, + void *ConfigPtr); +AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData, + void *ConfigPtr); +AGESA_STATUS agesa_HaltThisAp(uint32_t Func, uintptr_t Data, void *ConfigPtr); void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset); void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env); -AGESA_STATUS platform_PcieSlotResetControl(UINT32 Func, UINTN Data, - VOID *ConfigPtr); +AGESA_STATUS platform_PcieSlotResetControl(uint32_t Func, uintptr_t Data, + void *ConfigPtr); typedef struct { - UINT32 CalloutName; + uint32_t CalloutName; CALLOUT_ENTRY CalloutPtr; } BIOS_CALLOUT_STRUCT; diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index 713f76c..a48a535 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -41,7 +41,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void); AGESA_STATUS agesawrapper_amdinitmid(void); void *agesawrapper_getlateinitptr(int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINTN Data, +AGESA_STATUS agesawrapper_amdlaterunaptask(uint32_t Func, uintptr_t Data, void *ConfigPtr); AGESA_STATUS agesawrapper_amdinitrtb(void); AGESA_STATUS agesawrapper_amdinitresume(void); @@ -51,9 +51,9 @@ AGESA_STATUS agesawrapper_fchs3earlyrestore(void); AGESA_STATUS agesawrapper_fchs3laterestore(void); -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); -VOID amd_initcpuio(void); -const void *agesawrapper_locate_module(const CHAR8 name[8]); +void OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); +void amd_initcpuio(void); +const void *agesawrapper_locate_module(const char name[8]); void SetFchResetParams(FCH_RESET_INTERFACE *params); void OemPostParams(AMD_POST_PARAMS *PostParams); diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 181eafd..9c10fec 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -49,7 +49,7 @@ static void *AcpiIvrs; static void *AcpiCrat; -static AGESA_STATUS agesawrapper_readeventlog(UINT8 HeapStatus) +static AGESA_STATUS agesawrapper_readeventlog(uint8_t HeapStatus) { AGESA_STATUS Status; EVENT_PARAMS AmdEventParams = { @@ -190,7 +190,7 @@ PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; - PostParams->MemConfig.BottomIo = (UINT16) + PostParams->MemConfig.BottomIo = (uint16_t) (CONFIG_BOTTOMIO_POSITION >> 24); SetMemParams(PostParams); @@ -257,7 +257,7 @@ return status; } -VOID *agesawrapper_getlateinitptr(int pick) +void *agesawrapper_getlateinitptr(int pick) { switch (pick) { case PICK_DMI: @@ -326,7 +326,8 @@ const struct device *dev = dev_find_slot(0, IOMMU_DEVFN); if (dev && dev->enabled) { - LateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; + LateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + + 1; LateParams->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; } @@ -359,8 +360,8 @@ return Status; } -AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINTN Data, - VOID *ConfigPtr) +AGESA_STATUS agesawrapper_amdlaterunaptask(uint32_t Func, uintptr_t Data, + void *ConfigPtr) { AGESA_STATUS Status; AP_EXE_PARAMS ApExeParams; @@ -585,7 +586,7 @@ return CONFIG_AGESA_POST_MEMORY_CBFS_NAME; } -const void *agesawrapper_locate_module(const CHAR8 name[8]) +const void *agesawrapper_locate_module(const char name[8]) { const void *agesa; const AMD_IMAGE_HEADER *image; @@ -627,7 +628,7 @@ MODULE_ENTRY agesa_get_dispatcher(void) { const AMD_MODULE_HEADER *module; - static const CHAR8 id[8] = AGESA_ID; + static const char id[8] = AGESA_ID; MODULE_ENTRY val = car_get_var(agesa_dispatcher); if (val != NULL) diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index 60bfad1..0fffaf3 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -74,9 +74,9 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); -AGESA_STATUS GetBiosCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS GetBiosCallout(uint32_t Func, uintptr_t Data, void *ConfigPtr) { - UINTN i; + uintptr_t i; for (i = 0 ; i < BiosCalloutsLen ; i++) { if (BiosCallouts[i].CalloutName == Func) @@ -92,17 +92,19 @@ return BiosCallouts[i].CalloutPtr(Func, Data, ConfigPtr); } -AGESA_STATUS agesa_NoopUnsupported(UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_NoopUnsupported(uint32_t Func, uintptr_t Data, + void *ConfigPtr) { return AGESA_UNSUPPORTED; } -AGESA_STATUS agesa_NoopSuccess(UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_NoopSuccess(uint32_t Func, uintptr_t Data, void *ConfigPtr) { return AGESA_SUCCESS; } -AGESA_STATUS agesa_EmptyIdsInitData(UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_EmptyIdsInitData(uint32_t Func, uintptr_t Data, + void *ConfigPtr) { IDS_NV_ITEM *IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; if (Data == IDS_CALLOUT_INIT) @@ -110,10 +112,10 @@ return AGESA_SUCCESS; } -AGESA_STATUS agesa_Reset(UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_Reset(uint32_t Func, uintptr_t Data, void *ConfigPtr) { AGESA_STATUS Status; - UINTN ResetType; + uintptr_t ResetType; AMD_CONFIG_PARAMS *StdHeader; ResetType = Data; @@ -143,8 +145,8 @@ return Status; } -AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, - VOID *ConfigPrt) +AGESA_STATUS agesa_GfxGetVbiosImage(uint32_t Func, uintptr_t FchData, + void *ConfigPrt) { GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo; @@ -157,16 +159,16 @@ return pVbiosImageInfo->ImagePtr ? AGESA_SUCCESS : AGESA_WARNING; } -AGESA_STATUS __weak platform_PcieSlotResetControl(UINT32 Func, - UINTN Data, VOID *ConfigPtr) +AGESA_STATUS __weak platform_PcieSlotResetControl(uint32_t Func, + uintptr_t Data, void *ConfigPtr) { printk(BIOS_WARNING, "Warning - AGESA callout: %s not supported\n", __func__); return AGESA_UNSUPPORTED; } -AGESA_STATUS agesa_PcieSlotResetControl(UINT32 Func, UINTN Data, - VOID *ConfigPtr) +AGESA_STATUS agesa_PcieSlotResetControl(uint32_t Func, uintptr_t Data, + void *ConfigPtr) { return platform_PcieSlotResetControl(Func, Data, ConfigPtr); } @@ -184,9 +186,9 @@ * Passed from the AGESA_Callout for the agesawrapper_amdlaterunaptask. */ static struct agesa_data { - UINT32 Func; - UINTN Data; - VOID *ConfigPtr; + uint32_t Func; + uintptr_t Data; + void *ConfigPtr; } agesadata; /* @@ -213,7 +215,7 @@ lapicid(), decodeAGESA_STATUS(Status)); } -AGESA_STATUS agesa_RunFuncOnAp(UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_RunFuncOnAp(uint32_t Func, uintptr_t Data, void *ConfigPtr) { printk(BIOS_DEBUG, "%s\n", __func__); @@ -226,7 +228,8 @@ return AGESA_SUCCESS; } -AGESA_STATUS agesa_RunFcnOnAllAps(UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_RunFcnOnAllAps(uint32_t Func, uintptr_t Data, + void *ConfigPtr) { printk(BIOS_DEBUG, "%s\n", __func__); @@ -239,8 +242,8 @@ return AGESA_SUCCESS; } -AGESA_STATUS agesa_WaitForAllApsFinished(UINT32 Func, UINTN Data, - VOID *ConfigPtr) +AGESA_STATUS agesa_WaitForAllApsFinished(uint32_t Func, uintptr_t Data, + void *ConfigPtr) { printk(BIOS_WARNING, "Warning - AGESA callout: %s not supported\n", __func__); @@ -249,7 +252,7 @@ return Status; } -AGESA_STATUS agesa_IdleAnAp(UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_IdleAnAp(uint32_t Func, uintptr_t Data, void *ConfigPtr) { printk(BIOS_WARNING, "Warning - AGESA callout: %s no supported\n", __func__); diff --git a/src/soc/amd/common/block/pi/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c index e6a0c46..683a572 100644 --- a/src/soc/amd/common/block/pi/heapmanager.c +++ b/src/soc/amd/common/block/pi/heapmanager.c @@ -44,7 +44,8 @@ * Status Indicates whether TempHeapAddress was successfully * set. */ -AGESA_STATUS agesa_GetTempHeapBase(UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_GetTempHeapBase(uint32_t Func, uintptr_t Data, + void *ConfigPtr) { AGESA_TEMP_HEAP_BASE_PARAMS *pTempHeapBase; @@ -67,12 +68,12 @@ * Status Indicates whether HeapAddress was successfully * set. */ -AGESA_STATUS agesa_HeapRebase(UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_HeapRebase(uint32_t Func, uintptr_t Data, void *ConfigPtr) { AGESA_REBASE_PARAMS *Rebase; Rebase = (AGESA_REBASE_PARAMS *)ConfigPtr; - Rebase->HeapAddress = (UINTN)agesa_heap_base(); + Rebase->HeapAddress = (uintptr_t)agesa_heap_base(); if (!Rebase->HeapAddress) Rebase->HeapAddress = CONFIG_PI_AGESA_CAR_HEAP_BASE; @@ -94,8 +95,8 @@ static AGESA_STATUS FindAllocatedNode(uint32_t handle, BIOS_BUFFER_NODE **last_allocd_or_match) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; + uint32_t AllocNodeOffset; + uint8_t *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_STATUS Status = AGESA_SUCCESS; @@ -141,7 +142,8 @@ ROMSTAGE_CBMEM_INIT_HOOK(EmptyHeap) -AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_AllocateBuffer(uint32_t Func, uintptr_t Data, + void *ConfigPtr) { /* * Size variables explanation: @@ -155,17 +157,17 @@ * down into 2 nodes, once a node is selected as * the best fit. */ - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 FreedNodeSize; - UINT32 BestFitNodeOffset; - UINT32 BestFitNodeSize; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; - UINT32 MinimumSize; + uint32_t AvailableHeapSize; + uint8_t *BiosHeapBaseAddr; + uint32_t CurrNodeOffset; + uint32_t PrevNodeOffset; + uint32_t FreedNodeOffset; + uint32_t FreedNodeSize; + uint32_t BestFitNodeOffset; + uint32_t BestFitNodeSize; + uint32_t BestFitPrevNodeOffset; + uint32_t NextFreeOffset; + uint32_t MinimumSize; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -192,7 +194,7 @@ CurrNodePtr->BufferHandle = AllocParams->BufferHandle; CurrNodePtr->BufferSize = AllocParams->BufferLength; CurrNodePtr->NextNodeOffset = 0; - AllocParams->BufferPointer = (UINT8 *)CurrNodePtr + AllocParams->BufferPointer = (uint8_t *)CurrNodePtr + sizeof(BIOS_BUFFER_NODE); /* Update the remaining free space */ @@ -309,22 +311,23 @@ BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; BestFitNodePtr->NextNodeOffset = 0; - AllocParams->BufferPointer = (UINT8 *)BestFitNodePtr + + AllocParams->BufferPointer = (uint8_t *)BestFitNodePtr + sizeof(BIOS_BUFFER_NODE); } return AGESA_SUCCESS; } -AGESA_STATUS agesa_DeallocateBuffer (UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_DeallocateBuffer(uint32_t Func, uintptr_t Data, + void *ConfigPtr) { - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + uint8_t *BiosHeapBaseAddr; + uint32_t AllocNodeOffset; + uint32_t PrevNodeOffset; + uint32_t NextNodeOffset; + uint32_t FreedNodeOffset; + uint32_t EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -358,7 +361,7 @@ PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; /* Zero out the buffer, and clear the BufferHandle */ - memset((UINT8 *)AllocNodePtr + sizeof(BIOS_BUFFER_NODE), 0, + memset((uint8_t *)AllocNodePtr + sizeof(BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize); AllocNodePtr->BufferHandle = 0; @@ -429,7 +432,7 @@ return AGESA_SUCCESS; } -AGESA_STATUS agesa_LocateBuffer (UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_LocateBuffer(uint32_t Func, uintptr_t Data, void *ConfigPtr) { BIOS_BUFFER_NODE *AllocNodePtr; AGESA_BUFFER_PARAMS *AllocParams; @@ -440,7 +443,7 @@ Status = FindAllocatedNode(AllocParams->BufferHandle, &AllocNodePtr); if (Status == AGESA_SUCCESS) { - AllocParams->BufferPointer = (UINT8 *)((UINT8 *)AllocNodePtr + AllocParams->BufferPointer = (uint8_t *)((uint8_t *)AllocNodePtr + sizeof(BIOS_BUFFER_NODE)); AllocParams->BufferLength = AllocNodePtr->BufferSize; } diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index 5e6c899..fdef166 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -27,10 +27,10 @@ #include "chip.h" #include <amdblocks/car.h> -void __weak platform_FchParams_reset( - FCH_RESET_DATA_BLOCK *FchParams_reset) {} +void __weak platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) {} -AGESA_STATUS agesa_fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +AGESA_STATUS agesa_fch_initreset(uint32_t Func, uintptr_t FchData, + void *ConfigPtr) { AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; @@ -48,7 +48,8 @@ return AGESA_SUCCESS; } -AGESA_STATUS agesa_fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData, + void *ConfigPtr) { AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; const struct device *dev = dev_find_slot(0, SATA_DEVFN); @@ -92,7 +93,7 @@ return AGESA_SUCCESS; } -AGESA_STATUS agesa_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr) { uint8_t spd_address; int err; @@ -137,7 +138,7 @@ return AGESA_SUCCESS; } -AGESA_STATUS agesa_HaltThisAp(UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_HaltThisAp(uint32_t Func, uintptr_t Data, void *ConfigPtr) { AGESA_HALT_THIS_AP_PARAMS *info = ConfigPtr; uint32_t flags = 0; diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index d7a20a3..9c52297 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -86,7 +86,8 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, struct resource *resource, + u32 nodeid) { resource_t rbase, rend; unsigned int reg, link_num; @@ -187,12 +188,12 @@ addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) current += acpi_create_hest_error_source(hest, current, 0, - (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + (void *)((u32)addr + 2), *(uint16_t *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) current += acpi_create_hest_error_source(hest, current, 1, - (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + (void *)((u32)addr + 2), *(uint16_t *)addr - 2); return (unsigned long)current; } -- To view, visit https://review.coreboot.org/29520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic1bd64d6224a030a65d23decabf0e602cee02871 Gerrit-Change-Number: 29520 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: drivers/intel/fsp2_0: Run SplitFspBin with python2
by Nico Huber (Code Review) 06 Nov '18

06 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29519 Change subject: drivers/intel/fsp2_0: Run SplitFspBin with python2 ...................................................................... drivers/intel/fsp2_0: Run SplitFspBin with python2 It's not Python 3 compatible. Change-Id: Ibaad2c31bb6494652ce650ab7c1064728ec5fe80 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/fsp2_0/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/29519/1 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 0bfe90d..79fe5f8 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -69,7 +69,7 @@ ifeq ($(CONFIG_FSP_USE_REPO),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) - python 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" + python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" $(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd true -- To view, visit https://review.coreboot.org/29519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibaad2c31bb6494652ce650ab7c1064728ec5fe80 Gerrit-Change-Number: 29519 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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coreboot-gerrit November 2018