coreboot-gerrit November 2018

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Change in coreboot[master]: fsp_broadwell_de: Make sure SPI driver can be used across all stages
by Werner Zeh (Code Review) 12 Nov '18

12 Nov '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/29594 Change subject: fsp_broadwell_de: Make sure SPI driver can be used across all stages ...................................................................... fsp_broadwell_de: Make sure SPI driver can be used across all stages If the SPI driver is used in romstage after the cache memory has beed migrated to DRAM by FSP, there is no access to the fixed structure for cntlr and ichspi_lock variables as the cache, where they have been allocated in by the compiler, is not usable anymore. The right way to handle this case is using car_get_var_ptr() so that one will always have the right memory location for the given variables. Change-Id: I148acffbe9c93b23eb21e7e704b178c187895da1 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/fsp_broadwell_de/spi.c 1 file changed, 58 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29594/1 diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index a778aa9..c6e9371 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -59,7 +59,7 @@ typedef struct spi_slave ich_spi_slave; -static int ichspi_lock CAR_GLOBAL = 0; +static int ichspi_lock_var CAR_GLOBAL = 0; typedef struct ich9_spi_regs { uint32_t bfpr; @@ -109,7 +109,7 @@ uint32_t *bbar; } ich_spi_controller; -static ich_spi_controller cntlr CAR_GLOBAL; +static ich_spi_controller cntlr_var CAR_GLOBAL; enum { SPIS_SCIP = 0x0001, @@ -254,11 +254,13 @@ { const uint32_t bbar_mask = 0x00ffff00; uint32_t ichspi_bbar; + ich_spi_controller *cntlr; + cntlr = car_get_var_ptr(&cntlr); minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; + ichspi_bbar = readl_(cntlr->bbar) & ~bbar_mask; ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr.bbar); + writel_(ichspi_bbar, cntlr->bbar); } void spi_init(void) @@ -267,6 +269,8 @@ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; ich9_spi_regs *ich9_spi; + ich_spi_controller *cntlr; + int *ichspi_lock; #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = PCI_DEV(0, 31, 0); @@ -275,21 +279,23 @@ dev = dev_find_slot(0, PCI_DEVFN(31, 0)); #endif + cntlr = car_get_var_ptr(&cntlr_var); + ichspi_lock = car_get_var_ptr(&ichspi_lock_var); pci_read_config_dword(dev, 0xf0, &rcba); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000); ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; - cntlr.preop = &ich9_spi->preop; + *ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; + cntlr->opmenu = ich9_spi->opmenu; + cntlr->menubytes = sizeof(ich9_spi->opmenu); + cntlr->optype = &ich9_spi->optype; + cntlr->addr = &ich9_spi->faddr; + cntlr->data = (uint8_t *)ich9_spi->fdata; + cntlr->databytes = sizeof(ich9_spi->fdata); + cntlr->status = &ich9_spi->ssfs; + cntlr->control = (uint16_t *)ich9_spi->ssfc; + cntlr->bbar = &ich9_spi->bbar; + cntlr->preop = &ich9_spi->preop; ich_set_bbar(0); /* Disable the BIOS write protect so write commands are allowed. */ @@ -357,40 +363,44 @@ static int spi_setup_opcode(spi_transaction *trans) { uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + ich_spi_controller *cntlr; + int *ichspi_lock; + cntlr = car_get_var_ptr(&cntlr_var); + ichspi_lock = car_get_var_ptr(&ichspi_lock_var); trans->opcode = trans->out[0]; spi_use_out(trans, 1); - if (!ichspi_lock) { + if (!(*ichspi_lock)) { /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); + writeb_(trans->opcode, cntlr->opmenu); + optypes = readw_(cntlr->optype); optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); + writew_(optypes, cntlr->optype); return 0; } else { /* The lock is on. See if what we need is on the menu. */ uint8_t optype; uint16_t opcode_index; + uint8_t opmenu[cntlr->menubytes]; /* Write Enable is handled as atomic prefix */ if (trans->opcode == SPI_OPCODE_WREN) return 0; - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; + read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr->menubytes; opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; } - if (opcode_index == cntlr.menubytes) { + if (opcode_index == cntlr->menubytes) { printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", trans->opcode); return -1; } - optypes = readw_(cntlr.optype); + optypes = readw_(cntlr->optype); optype = (optypes >> (opcode_index * 2)) & 0x3; if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && @@ -438,12 +448,15 @@ { int timeout = 40000; /* This will result in 400 ms */ uint16_t status = 0; + ich_spi_controller *cntlr; + + cntlr = car_get_var_ptr(&cntlr_var); while (timeout--) { - status = readw_(cntlr.status); + status = readw_(cntlr->status); if (wait_til_set ^ ((status & bitmask) == 0)) { if (wait_til_set) - writew_((status & bitmask), cntlr.status); + writew_((status & bitmask), cntlr->status); return status; } udelay(10); @@ -461,6 +474,8 @@ int16_t opcode_index; int with_address; int status; + int *ichspi_lock; + ich_spi_controller *cntlr; spi_transaction trans = { dout, bytesout, @@ -482,7 +497,8 @@ if (ich_status_poll(SPIS_SCIP, 0) == -1) return -1; - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); + cntlr = car_get_var_ptr(&cntlr_var); + writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); spi_setup_type(&trans); opcode_index = spi_setup_opcode(&trans); @@ -492,13 +508,14 @@ if (with_address < 0) return -1; - if (!ichspi_lock && trans.opcode == SPI_OPCODE_WREN) { + ichspi_lock = car_get_var_ptr(&ichspi_lock_var); + if (!(*ichspi_lock) && trans.opcode == SPI_OPCODE_WREN) { /* * Treat Write Enable as Atomic Pre-Op if possible * in order to prevent the Management Engine from * issuing a transaction between WREN and DATA. */ - writew_(trans.opcode, cntlr.preop); + writew_(trans.opcode, cntlr->preop); return 0; } @@ -506,13 +523,13 @@ control = SPIC_SCGO | ((opcode_index & 0x07) << 4); /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) + if (readw_(cntlr->preop)) control |= SPIC_ACS; if (!trans.bytesout && !trans.bytesin) { /* SPI addresses are 24 bit only */ if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); /* * This is a 'no data' command (like Write Enable), its @@ -520,7 +537,7 @@ * spi_setup_opcode() above. Tell the chip to send the * command. */ - writew_(control, cntlr.control); + writew_(control, cntlr->control); /* wait for the result */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -542,7 +559,7 @@ * and followed by other SPI commands, and this sequence is controlled * by the SPI chip driver. */ - if (trans.bytesout > cntlr.databytes) { + if (trans.bytesout > cntlr->databytes) { printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" " spi_crop_chunk()?\n"); return -1; @@ -556,28 +573,28 @@ uint32_t data_length; /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); + data_length = min(trans.bytesout, cntlr->databytes); else - data_length = min(trans.bytesin, cntlr.databytes); + data_length = min(trans.bytesin, cntlr->databytes); /* Program data into FDATA0 to N */ if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); + write_reg(trans.out, cntlr->data, data_length); spi_use_out(&trans, data_length); if (with_address) trans.offset += data_length; } /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); + control &= ~((cntlr->databytes - 1) << 8); control |= SPIC_DS; control |= (data_length - 1) << 8; /* write it */ - writew_(control, cntlr.control); + writew_(control, cntlr->control); /* Wait for Cycle Done Status or Flash Cycle Error. */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -590,7 +607,7 @@ } if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); + read_reg(cntlr->data, trans.in, data_length); spi_use_in(&trans, data_length); if (with_address) trans.offset += data_length; @@ -599,7 +616,7 @@ spi_xfer_exit: /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); + writew_(0, cntlr->preop); return 0; } -- To view, visit https://review.coreboot.org/29594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I148acffbe9c93b23eb21e7e704b178c187895da1 Gerrit-Change-Number: 29594 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: security/tpm: Fix TCPA log feature
by build bot (Jenkins) (Code Review) 12 Nov '18

12 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29563 ) Change subject: security/tpm: Fix TCPA log feature ...................................................................... Patch Set 11: (2 comments) https://review.coreboot.org/#/c/29563/11/src/include/memlayout.h File src/include/memlayout.h: https://review.coreboot.org/#/c/29563/11/src/include/memlayout.h@168 PS11, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/#/c/29563/11/src/include/memlayout.h@168 PS11, Line 168: #define VBOOT2_TPM_LOG(addr, size) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/29563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Gerrit-Change-Number: 29563 Gerrit-PatchSet: 11 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph (1001864) Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 12 Nov 2018 11:35:15 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/ocp/wedge100s: Add vboot support
by Philipp Deppenwiese (Code Review) 12 Nov '18

12 Nov '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29593 Change subject: mainboard/ocp/wedge100s: Add vboot support ...................................................................... mainboard/ocp/wedge100s: Add vboot support * Add RO only FMAP. * Add kconfig options. Tested=OCP Wedge100s Change-Id: I1979e0263e41f21c01c407ac81ad1198a53741e8 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/mainboard/ocp/wedge100s/Kconfig A src/mainboard/ocp/wedge100s/vboot-ro.fmd 2 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29593/1 diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index 5d4349d..9c10d7d 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -16,6 +16,14 @@ select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 +config VBOOT + select VBOOT_VBNV_CMOS + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + config MAINBOARD_DIR string default "ocp/wedge100s" @@ -31,6 +39,7 @@ config CBFS_SIZE hex default 0x00200000 + default 0x006fa000 if VBOOT config VIRTUAL_ROM_SIZE hex @@ -46,5 +55,6 @@ config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro.fmd" if VBOOT endif # BOARD_OCP_WEDGE100S diff --git a/src/mainboard/ocp/wedge100s/vboot-ro.fmd b/src/mainboard/ocp/wedge100s/vboot-ro.fmd new file mode 100644 index 0000000..81b4cb8 --- /dev/null +++ b/src/mainboard/ocp/wedge100s/vboot-ro.fmd @@ -0,0 +1,20 @@ +FLASH 16M { + SI_ALL@0x0 0x800000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x7ff000 + } + SI_BIOS@0x800000 0x800000 { + RW_MRC_CACHE@0x0 0x10000 + RW_VPD@0x010000 0x2000 + WP_RO@0x012000 0x7ee000 { + RO_VPD@0x0 0x4000 + RO_SECTION@0x4000 0x7ea000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x6fa000 + } + } + } +} -- To view, visit https://review.coreboot.org/29593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1979e0263e41f21c01c407ac81ad1198a53741e8 Gerrit-Change-Number: 29593 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

1 0

Change in coreboot[master]: soc/intel/cannonlake/irqlinks.asl: Don't use hardcoded _CRS
by Arthur Heymans (Code Review) 12 Nov '18

12 Nov '18

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/29592 Change subject: soc/intel/cannonlake/irqlinks.asl: Don't use hardcoded _CRS ...................................................................... soc/intel/cannonlake/irqlinks.asl: Don't use hardcoded _CRS While FSP hardcodes the ITSS PIRQx registers to LINKB to IRQ10 and all the rest to IRQ11, it is no reason not to fetch this information from the ITSS registers. Change-Id: I8f9c4acbc1ea029ca679ee752592ca55b8eecb8e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/cannonlake/acpi/irqlinks.asl 1 file changed, 184 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/29592/1 diff --git a/src/soc/intel/cannonlake/acpi/irqlinks.asl b/src/soc/intel/cannonlake/acpi/irqlinks.asl index 0403ea0..1dd50ba 100644 --- a/src/soc/intel/cannonlake/acpi/irqlinks.asl +++ b/src/soc/intel/cannonlake/acpi/irqlinks.asl @@ -1,7 +1,9 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corporation. + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -46,11 +48,17 @@ Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 1) + Name (_PRS, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) + { 3, 4, 5, 6, 10, 12, 14, 15 } + }) + Method (_CRS, 0, Serialized) { Name (RTLA, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {11} + IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) @@ -61,6 +69,14 @@ Return (RTLA) } + Method (_SRS, 1, Serialized) + { + CreateWordField (Arg0, 1, IRQ0) + FindSetRightBit (IRQ0, Local0) + Decrement (Local0) + Store (Local0, ^^PIRA) + } + Method (_STA, 0, Serialized) { If (And (^^PIRA, ^^IREN)) { @@ -69,6 +85,11 @@ Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRA, ^^IREN, ^^PIRA) + } } Device (LNKB) @@ -76,19 +97,33 @@ Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 2) + Name (_PRS, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) + { 3, 4, 5, 6, 10, 12, 14, 15 } + }) + Method (_CRS, 0, Serialized) { - Name (RTLB, ResourceTemplate () + Name (RTLA, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {10} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLB, 1, IRQ0) + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) /* Set the bit from PIRQ Routing Register */ ShiftLeft (1, And (^^PIRB, ^^IREM), IRQ0) - Return (RTLB) + Return (RTLA) + } + + Method (_SRS, 1, Serialized) + { + CreateWordField (Arg0, 1, IRQ0) + FindSetRightBit (IRQ0, Local0) + Decrement (Local0) + Store (Local0, ^^PIRB) } Method (_STA, 0, Serialized) @@ -99,6 +134,11 @@ Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRB, ^^IREN, ^^PIRB) + } } Device (LNKC) @@ -106,19 +146,33 @@ Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 3) + Name (_PRS, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) + { 3, 4, 5, 6, 10, 12, 14, 15 } + }) + Method (_CRS, 0, Serialized) { - Name (RTLC, ResourceTemplate () + Name (RTLA, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {11} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLC, 1, IRQ0) + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) /* Set the bit from PIRQ Routing Register */ ShiftLeft (1, And (^^PIRC, ^^IREM), IRQ0) - Return (RTLC) + Return (RTLA) + } + + Method (_SRS, 1, Serialized) + { + CreateWordField (Arg0, 1, IRQ0) + FindSetRightBit (IRQ0, Local0) + Decrement (Local0) + Store (Local0, ^^PIRC) } Method (_STA, 0, Serialized) @@ -129,6 +183,11 @@ Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRC, ^^IREN, ^^PIRC) + } } Device (LNKD) @@ -136,19 +195,33 @@ Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 4) + Name (_PRS, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) + { 3, 4, 5, 6, 10, 12, 14, 15 } + }) + Method (_CRS, 0, Serialized) { - Name (RTLD, ResourceTemplate () + Name (RTLA, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {11} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLD, 1, IRQ0) + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) /* Set the bit from PIRQ Routing Register */ ShiftLeft (1, And (^^PIRD, ^^IREM), IRQ0) - Return (RTLD) + Return (RTLA) + } + + Method (_SRS, 1, Serialized) + { + CreateWordField (Arg0, 1, IRQ0) + FindSetRightBit (IRQ0, Local0) + Decrement (Local0) + Store (Local0, ^^PIRD) } Method (_STA, 0, Serialized) @@ -159,6 +232,11 @@ Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRD, ^^IREN, ^^PIRD) + } } Device (LNKE) @@ -166,19 +244,33 @@ Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 5) + Name (_PRS, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) + { 3, 4, 5, 6, 10, 12, 14, 15 } + }) + Method (_CRS, 0, Serialized) { - Name (RTLE, ResourceTemplate () + Name (RTLA, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {11} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLE, 1, IRQ0) + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) /* Set the bit from PIRQ Routing Register */ ShiftLeft (1, And (^^PIRE, ^^IREM), IRQ0) - Return (RTLE) + Return (RTLA) + } + + Method (_SRS, 1, Serialized) + { + CreateWordField (Arg0, 1, IRQ0) + FindSetRightBit (IRQ0, Local0) + Decrement (Local0) + Store (Local0, ^^PIRE) } Method (_STA, 0, Serialized) @@ -189,6 +281,11 @@ Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRE, ^^IREN, ^^PIRE) + } } Device (LNKF) @@ -196,19 +293,33 @@ Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 6) + Name (_PRS, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) + { 3, 4, 5, 6, 10, 12, 14, 15 } + }) + Method (_CRS, 0, Serialized) { - Name (RTLF, ResourceTemplate () + Name (RTLA, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {11} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLF, 1, IRQ0) + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) /* Set the bit from PIRQ Routing Register */ ShiftLeft (1, And (^^PIRF, ^^IREM), IRQ0) - Return (RTLF) + Return (RTLA) + } + + Method (_SRS, 1, Serialized) + { + CreateWordField (Arg0, 1, IRQ0) + FindSetRightBit (IRQ0, Local0) + Decrement (Local0) + Store (Local0, ^^PIRF) } Method (_STA, 0, Serialized) @@ -219,6 +330,11 @@ Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRF, ^^IREN, ^^PIRF) + } } Device (LNKG) @@ -226,19 +342,33 @@ Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 7) + Name (_PRS, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) + { 3, 4, 5, 6, 10, 12, 14, 15 } + }) + Method (_CRS, 0, Serialized) { - Name (RTLG, ResourceTemplate () + Name (RTLA, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {11} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLG, 1, IRQ0) + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) /* Set the bit from PIRQ Routing Register */ ShiftLeft (1, And (^^PIRG, ^^IREM), IRQ0) - Return (RTLG) + Return (RTLA) + } + + Method (_SRS, 1, Serialized) + { + CreateWordField (Arg0, 1, IRQ0) + FindSetRightBit (IRQ0, Local0) + Decrement (Local0) + Store (Local0, ^^PIRG) } Method (_STA, 0, Serialized) @@ -249,6 +379,11 @@ Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRG, ^^IREN, ^^PIRG) + } } Device (LNKH) @@ -256,19 +391,33 @@ Name (_HID, EISAID ("PNP0C0F")) Name (_UID, 8) + Name (_PRS, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) + { 3, 4, 5, 6, 10, 12, 14, 15 } + }) + Method (_CRS, 0, Serialized) { - Name (RTLH, ResourceTemplate () + Name (RTLA, ResourceTemplate () { - IRQ (Level, ActiveLow, Shared) {11} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField (RTLH, 1, IRQ0) + CreateWordField (RTLA, 1, IRQ0) Store (Zero, IRQ0) /* Set the bit from PIRQ Routing Register */ ShiftLeft (1, And (^^PIRH, ^^IREM), IRQ0) - Return (RTLH) + Return (RTLA) + } + + Method (_SRS, 1, Serialized) + { + CreateWordField (Arg0, 1, IRQ0) + FindSetRightBit (IRQ0, Local0) + Decrement (Local0) + Store (Local0, ^^PIRH) } Method (_STA, 0, Serialized) @@ -279,4 +428,9 @@ Return (0xb) } } + + Method (_DIS, 0, Serialized) + { + Or (^^PIRH, ^^IREN, ^^PIRH) + } } -- To view, visit https://review.coreboot.org/29592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8f9c4acbc1ea029ca679ee752592ca55b8eecb8e Gerrit-Change-Number: 29592 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mediatek/mt8183: Add PMIC wrapper support
by build bot (Jenkins) (Code Review) 12 Nov '18

12 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29421 ) Change subject: mediatek/mt8183: Add PMIC wrapper support ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/29421/5/src/soc/mediatek/mt8183/pmic_wrap.c File src/soc/mediatek/mt8183/pmic_wrap.c: https://review.coreboot.org/#/c/29421/5/src/soc/mediatek/mt8183/pmic_wrap.c… PS5, Line 22: #define PRIORITY_SEL_2(name, id, priority) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/29421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idbdb15f11227ded3f5d18fe6504c8c646973b733 Gerrit-Change-Number: 29421 Gerrit-PatchSet: 5 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 12 Nov 2018 10:23:35 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Read pmic cid for check. Do not submit.
by Tristan Hsieh (Code Review) 12 Nov '18

12 Nov '18

Tristan Hsieh has abandoned this change. ( https://review.coreboot.org/29591 ) Change subject: Read pmic cid for check. Do not submit. ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/29591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I4cb1692d07fb7745d26e2aca0f40ac57dc965e4f Gerrit-Change-Number: 29591 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: Read pmic cid for check. Do not submit.
by Tristan Hsieh (Code Review) 12 Nov '18

12 Nov '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/29591 Change subject: Read pmic cid for check. Do not submit. ...................................................................... Read pmic cid for check. Do not submit. Change-Id: I4cb1692d07fb7745d26e2aca0f40ac57dc965e4f Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/soc/mediatek/mt8183/mt6358.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/29591/1 diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index c2cf259..708f8e7 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -14,6 +14,7 @@ */ #include <assert.h> +#include <console/console.h> #include <soc/pmic_wrap.h> #include <soc/mt6358.h> @@ -356,9 +357,14 @@ void mt6358_init(void) { + u16 cid; + if (pwrap_init()) die("ERROR - Failed to initialize pmic wrap!"); + cid = pwrap_read_field(PMIC_SWCID, 0xFFFF, 0); + printk(BIOS_DEBUG, "PMIC CID 0x%x\r\n", cid); + pmic_set_power_hold(true); pmic_wdt_set(); mt6358_init_setting(); -- To view, visit https://review.coreboot.org/29591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4cb1692d07fb7745d26e2aca0f40ac57dc965e4f Gerrit-Change-Number: 29591 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: src: Get rid of duplicated includes
by Elyes HAOUAS (Code Review) 12 Nov '18

12 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29582 to look at the new patch set (#4). Change subject: src: Get rid of duplicated includes ...................................................................... src: Get rid of duplicated includes Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/pirq_routing.c M src/lib/prog_loaders.c M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/get_bus_conf.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/cavium/cn8100_sff_evb/mainboard.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/lenovo/x60/dock.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/opencellular/elgon/mainboard.c M src/mainboard/packardbell/ms2290/mainboard.c M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/mainboard/via/epia-m850/romstage.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/fsp_rangeley/acpi.c M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/x4x/acpi.c M src/northbridge/via/vx900/early_vx900.h M src/northbridge/via/vx900/raminit_ddr3.c M src/northbridge/via/vx900/traf_ctrl.c M src/security/vboot/secdata_tpm.c M src/soc/cavium/cn81xx/soc.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/include/soc/pci_devs.h M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/refcode.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/northcluster.c M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra210/sor.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/fsp_rangeley/early_init.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/soc.h M src/southbridge/intel/fsp_rangeley/spi.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/nvidia/mcp55/lpc.c 87 files changed, 6 insertions(+), 109 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/29582/4 -- To view, visit https://review.coreboot.org/29582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Gerrit-Change-Number: 29582 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/fsp_broadwell_de: Add vboot support
by Philipp Deppenwiese (Code Review) 12 Nov '18

12 Nov '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29590 Change subject: soc/intel/fsp_broadwell_de: Add vboot support ...................................................................... soc/intel/fsp_broadwell_de: Add vboot support Add kconfig option and CMOS function. Change-Id: I7f1a1e8538999c5e4e54f3a4aa0cdf6d8a309c4f Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/fsp_broadwell_de/Makefile.inc M src/soc/intel/fsp_broadwell_de/pmutil.c 3 files changed, 28 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/29590/1 diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index ec010b3..457018a 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -28,6 +28,9 @@ select TSC_MONOTONIC_TIMER select TSC_CONSTANT_RATE +config VBOOT + select VBOOT_STARTS_IN_ROMSTAGE + config CBFS_SIZE hex default 0x200000 diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 5448190..2de2308 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -31,9 +31,10 @@ ramstage-y += gpio.c ramstage-y += iou_complto.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +ramstage-y += pmutil.c +romstage-y += pmutil.c ramstage-y += vtd.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c +smm-y += pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c diff --git a/src/soc/intel/fsp_broadwell_de/pmutil.c b/src/soc/intel/fsp_broadwell_de/pmutil.c index ccab1ce..94ae83e 100644 --- a/src/soc/intel/fsp_broadwell_de/pmutil.c +++ b/src/soc/intel/fsp_broadwell_de/pmutil.c @@ -27,6 +27,7 @@ #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> +#include <security/vboot/vbnv.h> /* Print status bits with descriptive names */ static void print_status_bits(u32 status, const char *const bit_names[]) @@ -171,3 +172,24 @@ smi_en &= ~mask; outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); } + +int vbnv_cmos_failed(void) +{ + u8 reg8; + int rtc_failed; +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCI_DEV(0, LPC_DEV, 0); +#else + struct device *dev = dev_find_slot(0, LPC_DEV_FUNC); +#endif + + reg8 = pci_read_config8(dev, GEN_PMCON_3); + rtc_failed = reg8 & RTC_PWR_STS; + if (rtc_failed) { + reg8 &= ~RTC_PWR_STS; + pci_write_config8(dev, GEN_PMCON_3, reg8); + printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); + } + + return !!rtc_failed; +} -- To view, visit https://review.coreboot.org/29590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7f1a1e8538999c5e4e54f3a4aa0cdf6d8a309c4f Gerrit-Change-Number: 29590 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

1 0

Change in coreboot[master]: mb/emulation/qemu-i440fx/Makefile.inc: Fix "No newline at end of file"
by Patrick Georgi (Code Review) 12 Nov '18

12 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29583 ) Change subject: mb/emulation/qemu-i440fx/Makefile.inc: Fix "No newline at end of file" ...................................................................... mb/emulation/qemu-i440fx/Makefile.inc: Fix "No newline at end of file" Change-Id: I79e9b95059f16c53767c89cfaef1e89182be9c62 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/29583 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/emulation/qemu-i440fx/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index c986667..ecc049e 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -2,4 +2,4 @@ ramstage-y += northbridge.c ramstage-y += fw_cfg.c romstage-y += memory.c -ramstage-y += memory.c \ No newline at end of file +ramstage-y += memory.c -- To view, visit https://review.coreboot.org/29583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I79e9b95059f16c53767c89cfaef1e89182be9c62 Gerrit-Change-Number: 29583 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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